JPH01186648A - Gate array integrated circuit - Google Patents

Abstract

PURPOSE:To enable comparison with a monitor diagram to be made when discovering abnormal locations by checking with a microscope etc., by providing a pattern which indicates positions of cell or wiring pattern on a chip. CONSTITUTION:A chip 1 has an I/O pad 2 and an internal cell array row 3 and a ground reinforcing wiring pattern 4 is provided at a layer 3 which is the ground reinforcing wiring layer at the upper part of the first and second layers which are normal signal wiring layers connecting each cell of the internal cell array row 3. Location target patterns 5 and 6 are provided at this ground reinforcing wiring pattern 4 and each cell position can be displayed without intriguing wiring area. It allows the same location to be easily detected when discovering an abnormal location on chip.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate array integrated circuit, and more particularly to a gate array integrated circuit having a plurality of cells.

Prior Art Conventionally, this type of gate array integrated circuit has been inspected using a microscope or the like to find abnormal locations on the chip. The conventional gate array integrated circuit will be explained using FIG. 2. FIG. 0 is a schematic diagram showing a chip 1 of the conventional gate array integrated circuit, 2 is an input/output pad, 3 is an internal cell array column, and 4 is a ground. This is a reinforced wiring pattern.

When such an abnormal location is found on chip 1, the location of the location can be determined by counting from the edge of the cell array, or by expressing the location of the cell or wiring pattern by the relative location from the input/output bat. There was no other way but to do so. Therefore, when comparing with monitor drawings, etc., there is a drawback that it is very difficult to find the same location on the drawing.

1. SUMMARY OF THE INVENTION An object of the present invention is to provide a gate array integrated circuit in which when an abnormal location is found on a chip, the same location on a drawing can be easily searched for.

A gate array integrated circuit according to the present invention is a gate array integrated circuit having a plurality of cells, and is characterized in that it has a position display pattern indicating at least the position of the cell.

K1 man Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a schematic diagram of an embodiment of a gate array integrated circuit according to the present invention. In FIG. 0, parts equivalent to those in FIG. A ground reinforcing wiring pattern 4 is provided in the third layer, which is a ground reinforcing wiring layer, above the first and second wiring layers (not shown), and location guide patterns 5 and 6 are provided on this ground reinforcing wiring pattern 4. By providing this, it is possible to display the position of each cell without encroaching on the wiring area.

In this case, the ground reinforcement wiring pattern 4 around the chip 1
Concave location guide patterns 5 are provided at intervals of 250 μs (A), and convex location guide patterns 6 are provided alternately on the left and right at intervals of 250 μs (B) in the vertical ground reinforcing wiring pattern 4. There is. These uneven location reference patterns 5 and 6 make it possible to easily and accurately represent the position of a target cell or wiring pattern. This makes it easy to find the same location on the drawing.

In this embodiment, a rectangular uneven pattern is provided, but it is obvious that a triangular or semicircular uneven pattern may be used, and the same effect can be obtained with any shape.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention provides patterns that indicate the positions of cells and wiring patterns on a chip in a gate array integrated circuit, so that when an abnormality is found by checking with a microscope etc., the chip can be easily detected. This has the advantage that the position within can be expressed accurately and easily, and comparison with the monitor diagram can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a gate array integrated circuit according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a conventional gate array integrated circuit. Explanation of symbols of main parts 1... LSI chip 2... Input/output pad 3... Internal cell array column

Claims (1)

[Claims] (1) A gate array integrated circuit having a plurality of cells, characterized in that it has a position display pattern indicating at least the position of the cell.