JPH02257655A - Gate array - Google Patents

Abstract

PURPOSE:To easily judge whether a wafer process has been finished satisfactorily or not when a defect is caused by a method wherein a pattern size for chip-monitor mounting use is formed between a pattern region for input/output buffer circuit mounting use and a pattern region for internal logic circuit mounting use. CONSTITUTION:A circuit-constituent element and a wiring part which correspond to a customer's logic circuit are arranged and wired by using a computer in a pattern region 1 for input/output buffer circuit mounting use and a pattern region 2 for internal logic circuit mounting use. On the other hand, a transistor pattern on the pattern region 2 for internal logic circuit mounting use, i.e., the pattern identical to a basic cell, is arranged in a pattern region 3 for chip- monitor mounting use; a logic circuit which can analyze a defect easily is assembled by a metal wiring process. Thereby, it is possible to monitor how a wafer process on the pattern region 2 for internal logic circuit mounting use has been finished; it is possible to easily analyze a defect of a product.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a gated array having a pattern area for mounting an input/output buffer circuit and a pattern area for mounting an internal logic circuit. This relates to gate arrays that are easy to analyze.

[Conventional technology]

As shown in FIG. 2, the conventional gate array has a chip pattern consisting of a pattern area 1 for mounting an input/output buffer circuit and a pattern area 2 for mounting an internal logic circuit.
It has a structure in which a pattern area 1 for mounting an input/output buffer circuit is arranged around this pattern area 20.

By the way, such gate arrays are stocked after completing the transistor generation process such as the diffusion process, and the pattern area 1 for mounting the input/output buffer circuit is equipped with the input/output buffer circuit elements arranged in the metal wiring process. In the internal logic circuit mounting pattern area 2, the internal logic circuit components are arranged, and the mutual wiring between the internal logic circuit components and the mutual wiring between the internal logic circuit components and the input/output buffer circuit elements are automatically performed by a computer. Common.

[Problem to be solved by the invention]

However, in the case of such a gate array, since automatic placement and wiring is performed by a computer, the placement positions of the internal logic circuit elements are random, making it difficult to trace the chip pattern during failure analysis. Furthermore, in the case of normal gate arrays, the customer creates circuit design and input/output signals for functional evaluation, making it difficult to trace the logic circuit during failure analysis and to estimate the logic circuit element that causes the failure. The problem was that failure analysis was almost impossible.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a gate array that can easily analyze defects caused by problems in the manufacturing process.

[l! ! Means to solve the problem]

In the gate array according to the present invention, a chip monitor mounting pattern area is provided between the input/output buffer 7 circuit mounting pattern area and the internal logic circuit mounting pattern area on the chip butter y.

[Effect]

In the present invention, by mounting a chip finish monitor pattern in the chip monitor mounting pattern area, it becomes possible to easily determine the quality of the Ueno process finish when a defect occurs.

〔Example〕 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual diagram of a gate array chip pattern showing one embodiment of the present invention. This embodiment is different from the conventional example shown in FIG. This is because we have established the following.

According to the gate array having the configuration of the above embodiment, the pattern area 1 for mounting seven input/output buffer circuits and the pattern area 2 for mounting internal logic circuit are provided with circuit components corresponding to one customer's logic circuit, as in the conventional example. Automatically place and route wiring using a computer. On the other hand, in the chip monitor mounting pattern area 3, the same transistor patterns (hereinafter abbreviated as basic cells) on the internal logic circuit mounting pattern area 2 are lined up to facilitate υ failure analysis during the metal wiring process. Incorporate logic circuits. This logic circuit may be any type of logic circuit such as an inverter chain or a shift register, and in short, it may be any logic circuit that the manufacturer deems easy to analyze. Normally, the causes of defects in products that have completed initial product debugging and are ready for mass production are mostly due to defects in the manufacturing process, especially in the wafer process, and also depend on the pattern shape of transistors, etc. It does not depend on Atb on the circuit itself. Therefore, in the case of a gate array, the basic cells of the same shape are lined up on the internal logic circuit mounting pattern area 2, so the same basic cells are lined up in the chip monitor mounting pattern area 3 for failure analysis. If a simple logic circuit is mounted, the wafer process finish on the internal logic circuit mounting pattern area 2 can be monitored, and product failure analysis becomes easy.

In addition, in the above embodiment, a pattern shape for mounting a chip monitor is provided on all four sides of the chip, but a pattern area for mounting a chip monitor is provided on only three sides, only two sides, or only one side of the chip. Even in this case, the defect detection sensitivity decreases, and basically the same effect as in the above embodiment is achieved.

〔Effect of the invention〕

As described above, according to the gate array of the present invention, since the pattern area for mounting the chip monitor is provided between the butter/area for mounting the input/output buffer circuit and the pattern area for mounting the internal logic circuit, the wafer process can be carried out in the event of a failure. It becomes possible to judge the quality of the finish. Therefore, gate array failure analysis, which is almost impossible on the manufacturing side because the customer is in charge of logic circuit design, etc., is performed on the chip finishing pattern area on the chip monitor mounting pattern area. This can be easily done by incorporating a logic circuit for the purpose, and the practical effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of a gate array chip pattern showing an embodiment of the present invention, and FIG. 2 is a schematic diagram of a gate array chip pattern showing a conventional example. 1. --- Pattern area for mounting input/output buffer circuit, 2
FistφFist・Pattern area for mounting internal logic circuit, 3・Fist・Φ
Pattern area for chip monitor mounting.

Claims (1)

[Claims] In a gate array chip pattern that has a pattern area for mounting an input/output buffer circuit and a pattern area for mounting internal logic circuit elements and wiring, a pattern area for mounting an input/output buffer circuit and a pattern for mounting internal logic circuit elements and wiring. A gate array characterized in that a pattern area for mounting a chip monitor is provided between areas.