JPH0480936A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avert the effect on the electrical characteristics of testing circuits due to the unstability of the pattern shape and size near a boundary line by the overlapping of exposure unit peripheral parts by a method wherein the testing circuits provided in a scribe region are arranged apart from the exposure unit, boundary line in case of the pattern formation. CONSTITUTION:Source.drain region 4 wherein the pattern size is closely related to the electrical characteristics of a field effect transistor and a gate metal 5 are arranged apart from a boundary line 3. Furthermore, in the example of the contact hole chain resistance, the patterns of diffused layers 6 and the contact holes 7 whose shape and size directly affect the resistance value are arranged apart from the boundary line 3 but the aluminum wiring 8 not affecting the whole combined resistance regardless of the slight change in shape is arranged so as to traverse the boundary line 3. In such a structure, even if the exposure unit peripheral parts are overlapped with one another near the boundary line 3 to change the pattern shape and size, the electrical characteristics of the testing circuits can not be affected by the change.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to semiconductor devices, particularly in the production of integrated circuits.
This field relates to the structure and arrangement of a test circuit for testing the electrical characteristics of individual elements such as transistors and resistors used in the circuit.

[Conventional technology]

As the degree of integration of integrated circuits becomes thicker (and the element size becomes smaller), the number of items to be tested and evaluated becomes more numerous (and the test circuits mentioned above tend to become more complex. In order to maintain the high degree of integration of the integrated circuit body, as shown in Fig. 2 (α) e Cb), the scribe area 2 outside the integrated circuit body 1, that is, the area used when cutting the completed integrated circuit chip, is It is often installed within the "cut off" area.

Since the test circuit in the scribe area 2 that is no longer needed after the evaluation is completed will turn into chips and disappear when the integrated circuit chip 1 is cut, the size of the integrated circuit chip body 1 can be reduced by the method described above. It becomes possible to install a large test circuit without making it unnecessarily large.

[Problem to be solved by the invention]

However, when a test circuit is installed in the scribe area using the conventional technology, when creating a photolithography original plate for forming an integrated circuit, that is, a photomask, or using this photomask to create a semiconductor substrate. When printing a pattern on the surface, one or several integrated circuit chips are exposed repeatedly, so a boundary line 3 of one exposure degree is created within the scribe area 2, and a boundary line s is located on this boundary line s. The shape and dimensions of the pattern of the test circuit become unstable due to double exposure caused by the overlap margin provided at the periphery of each exposure degree during repeated exposure, and the accuracy during measurement evaluation of the test circuit becomes unstable. There was a problem of damaging the This problem can be solved by the gate metal 5, the source/drain region 4, as illustrated in FIG. This is especially fatal in the case of patterns such as contact holes 7 and diffusion layers 6 whose electrical characteristics are directly affected by their shape and dimensions.

The present invention is intended to solve the problem of shape and dimensional instability caused by the conventional test circuit for semiconductor integrated circuits being exposed to the periphery of the exposed area during pattern formation, and its purpose is to: The aim is to improve the accuracy and reliability of circuit evaluation data for testing semiconductor integrated circuits.

[Means to solve the problem]

The semiconductor device of the present invention has a "cut margin", that is, a scribe area, for cutting finished product chips on the surface of the semiconductor substrate, and when forming a photomask or an integrated circuit pattern, one or several integrated circuit chips can be cut into chips. In a semiconductor device having a step of performing reverse exposure, an exposure unit boundary during this repeated exposure is located within the scribe area, and a test circuit for element characteristic testing in the scribe area, the test circuit It is characterized in that the main part of the scribe area is arranged so as to avoid the vicinity of the exposure degree boundary line within the scribe area.

[Effect]

According to the above configuration of the present invention, of the patterns constituting the test circuit, the portions whose electrical characteristics have strong shape dependence or size dependence are arranged so as to avoid the vicinity of the exposure degree boundary line. By doing so, it is possible to suppress the influence of the shape and dimensional instability of the pattern near the boundary line on the electrical characteristics of the test circuit.

〔Example〕

FIG. 1 is a plan view showing the arrangement of a test circuit for a semiconductor device in an embodiment of the present invention, and illustrates the shapes of a field effect transistor and a contact hole chain resistance.

1 is an integrated circuit main body, 2 is a scribe area, and 3 is a boundary line of an exposure unit. As shown in the figure, the source/drain region 4 and the gate metal 5, whose pattern dimensions are closely related to the electrical characteristics of the field effect transistor, are arranged avoiding the boundary line 5.

In addition, in the example of contact hole chain resistance, the pattern of the diffusion layer 6 and contact hole 7, whose shape and dimensions directly affect the resistance value, avoids the boundary line 3, and even if the shape changes slightly, the overall combined resistance does not change. is arranged so as to cross the boundary line with aluminum wiring 8 which does not affect the boundary line.

With such a structure, even if the exposure units overlap near the boundary line 5 and the dimensions of the pattern shape 9 change, the electrical characteristics of the test circuit can be prevented from being affected.

〔Effect of the invention〕

As described above, according to the present invention, by arranging the test circuit installed in the scribe area while avoiding the exposure degree boundary line during pattern creation, the pattern shape and dimensions near the boundary line can be adjusted to the periphery of the exposure unit. This has the effect of preventing instability due to overlap from affecting the electrical characteristics of the test circuit.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the arrangement of a test circuit for a semiconductor device in an embodiment of the present invention. (α) is an overall view including the integrated circuit main body, and (b) t (”) is a plan view showing the arrangement of the scribe area including the test circuit pattern in the eve area. 1... ...Integrated circuit body 2...Scribe area 6...Boundary line of exposure degree during repeated exposure 4...Test electric field Source/drain region 5 of effect transistor... Gate metal 6 of field effect transistor for test... Diffusion layer region 7 of contact hole chain resistance for test...・・・Contact hole 8・・・・・・
・・・Aluminum wiring and measurement probe electrode Figure 1

Claims (1)

[Claims] "Cut" for cutting finished product chips on the surface of the semiconductor substrate
That is, it has a scribe area, and has a step of repeatedly exposing one or several integrated circuit chips as a unit during pattern formation of a photomask or integrated circuit, and the exposure unit boundary during this repeated exposure is within the scribe area. In a semiconductor device that is located in the scribe area and has a test circuit for testing device characteristics in the scribe area, the main part of the test circuit is arranged so as to avoid the vicinity of the exposure unit boundary line in the scribe area. A semiconductor device characterized by: