KR940004993B1 - Photo and etch bias measurement display apparatus - Google Patents

Abstract

The apparatus is constructed that a plurality of depressed photoresist patterns are formed in a cutting line of a wafer, embossed photoresist patterns having sequentially increased or decreased line width are formed as compared with the line widths of the depressed photoresist patterns, and other embossed photoresist patterns are formed to act as a pattern scale, thereby rapidly checking the variation of pattern line width.

Description

Photo and etch bias display

FIG. 1B is a plan view showing an applied intaglio mask of chromium. FIG.

1C to 1D are cross-sectional views showing a photo process and an etching process along the AA ′ axis of FIG. 1B.

Figure 2b is a plan view showing an embossed mask coated with chromium.

2C to 2D are sectional views of the photo process and etching process along the B-B 'axis of FIG. 2B.

3 is a plan view showing positions of chips, cutting lines, and pattern graduations on a predetermined upper portion of the wafer;

4 is a plan view showing a pattern scale formed on a mask according to the present invention.

5A and 5B are plan views showing that the intaglio and embossed patterns of the photo or etch bias are matched at "+.2" and "-.2".

* Explanation of symbols for main parts of the drawings

1 wafer (substrate) 2 conductive layer (or insulating layer)

3: photoresist layer 4: mask

5: engraved photoresist pattern 6: embossed photoresist pattern

7: engraved pattern 8: embossed pattern

10 chip 11: cutting line

12: pattern scale 20: engraved mask pattern

21: embossed mask pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for measuring photo and etch bias of a highly integrated semiconductor device. In particular, the present invention measures a cutting line of a wafer so that a change in pattern line width can be easily read during a photo process and an etching process. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photo and etch bias measurement and display device capable of measuring a critical dimension after a photo process or an etching process by forming a display device simultaneously with a pattern in fabricating a photomask.

In the semiconductor device manufacturing process, for example, when the pattern of the conductive layer is formed, the predetermined conductive layer pattern is formed through the photo process and the etching process, and the line width is different from that of the mask pattern at the design and the pattern after the photo process or the etching process. This is because the line bomber can appear differently when changing various conditions of photo process and etching process.

To describe the patterning process in detail, reference is made to FIGS. 1b to 1d and 2b to 2d.

1A and 2A show what is formed in the mask in an arbitrary pattern shape. The hatched part here is chromium (cr).

1B and 2B show exposure of the photoresist layer 3 in a structure in which an insulating layer (or conductive layer) 2 and a photoresist layer 3 are laminated on the substrate 1 using a mask. 1b shows the cross-sectional structure along the A-A 'axis of FIG. 1a, and FIG. 2b shows the B-B' axis of FIG. 2a.

1C and 2C show the negative photoresist pattern 5 and the relief photoresist pattern 6 formed by developing the exposed photoresist layer 3, and generally the negative photoresist pattern 5 of FIG. 1C. The line width b of is larger than the line width (a) of the mask 4 pattern of FIG. 1b, and (a <b) the line width b 'of the embossed photoresist pattern 6 of FIG. 2c is the mask of FIG. 4) It becomes smaller than the line width a 'of the pattern (a'> b '). This is because the waveiness of the light during exposure is further removed during the development process.

1d and 2d show the conductive layer 2 pattern formed by etching the conductive layer 2 exposed by the above process and removing the photoresist layer 3. In general, the conductive layers of FIGS. 1d and 2d are formed. The pattern line width in (2) is a transient etching phenomenon in the edible process as in the photo process, and the pattern line width in FIG. 1d is increased and the pattern line width in FIG. 2d is reduced to form c> b and c '<b'.

When performing the photo process and the etching process as described above, the designer uses a critical size (CD) measuring device (e.g., SEM equipment) or analyzes the pattern line width (Bias) to measure whether the designer has the desired pattern line width. The reading was outlined using a Resolution Bar and a Space Pattern. In this case, the critical size is measured to appropriately re-adjust various conditions such as an appropriate exposure time or etching time.

However, measuring the pattern line width by selecting a chip of a sample wafer after a photo process or a visual process using a critical size (CD) measuring device as described above takes a lot of time and accurately using an analysis bar and a space pattern. A problem arises in that the threshold size cannot be read.

Therefore, in order to solve the above problems, the present invention forms various pattern scales provided to measure the critical size after the photo process and the etching process on the cutting line between the chip and the chip of the wafer, and the upper part of the chip through the microscope. An object of the present invention is to provide a photo and etch bias measurement display device that can be easily and quickly read by measuring a change of a pattern by the pattern scale.

According to the present invention, in order to easily read the change in the pattern line width after performing the photo process of forming a pattern on the photoresist layer using a mask, the intaglio having a predetermined line width at a predetermined portion of the wafer cutting line by the photo process A plurality of photoresist patterns are formed, and an embossed photoresist pattern is formed on the entire surface corresponding to the intaglio photoresist pattern in order of a predetermined line width than the line width of the intaglio photoresist pattern. The embossed photoresist pattern is sequentially formed by the predetermined line width, and the number reduced is patterned on the photoresist to form a pattern scale, so that the negative photoresist pattern and the embossed photoresist pattern are configured to be read. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 shows the cutting line 11 between the chip 10 and the chip 10 on the upper surface of the wafer, and the pattern scale 12 produced by the present invention is arranged at a predetermined portion of the cutting line 11. It is shown.

4 is an enlarged plan view of the pattern scale 12 formed on the chrome mask of the present invention. When the pattern of the photoresist layer of the relief pattern is formed by leaving only a predetermined portion as a photo process as shown in FIGS. 2B and 2C, FIG. The pattern line width of the zest layer is generally increased and decreased than the line width of the mask pattern. In order to measure the increase and decrease, a pattern scale having a line width increased and decreased is formed in the mask pattern. That is, a plurality of intaglio mask patterns 20 having a predetermined line width (for example, 1.2 μm) are formed, and a predetermined line width (0.05 μm) is larger than the pattern line width of the intaglio mask pattern 20 on the front surface corresponding to the intaglio mask pattern 20. ) To form an embossed mask pattern 21 that is sequentially increased or decreased as used as a pattern scale. In addition, the size of the line width of the embossed mask pattern 21 is embossed to make it easier to read the measurement of the intaglio mask pattern 20.

Therefore, when the pattern is formed on the photoresist layer of the predetermined portion of the chip by the photo process of exposure and development process using the mask having the pattern scale, the pattern of the photoresist layer is reduced or increased than the line width of the mask pattern. At this time, since the pattern scale is formed in the cutting line area, the upper and lower surfaces of the embossed photoresist pattern and the negative photoresist pattern are formed or do not coincide.

If not, reading the value of the closest match can reveal the rate of change of the pattern by the photo process.

For example, if the top and bottom surfaces of the embossed photoresist pattern and the intaglio photoresist pattern are coincident with each other (see FIG. 5A), the line width of the embossed photoresist pattern is larger than the line width (d) of the embossed mask pattern. d ') is reduced by 0.2 占 퐉. In addition, if the top and bottom surfaces of the embossed photoresist pattern and the intaglio photoresist pattern are coincident with each other (see FIG. 5B), the line width of the embossed photoresist pattern is larger than the line width e of the embossed mask pattern. ') Is increased by 0.2 µm.

It should be noted here that in the embodiment of the present invention, the line width interval of the pattern scale is formed to be 0,05 μm, but it may be further refined and the number of the pattern scales may be further increased. Further, when the embossed and intaglio pattern scales are exactly matched left and right between "+.05" and "+.1", they can be read as "+0.075" as an approximation.

Furthermore, even when the photoresist layer pattern is used as a mask and the lower conductive layer pattern is formed by the etching process, the increase and decrease of the pattern can be read by the above method. Thus, the time, temperature, gas, etc. of the etching process can be adjusted. The desired etching bias can be obtained.

As described above, the present invention can easily read the line width size change of the pattern after the photo process or the etching process by using a microscope up to about 0.025㎛, and change the line width size of the pattern inside the wafer, between runs and runs. Each run can be quickly and easily inspected to improve the reliability and productivity of the semiconductor device.

Claims (5)

A negative photoresist pattern having a predetermined line width at a predetermined portion of the cutting line of the wafer by the photo process so that the pattern line width can be easily read after the photo process of forming a pattern on the photoresist layer using a mask. A plurality of embossed photoresist patterns are formed on the entire surface corresponding to the intaglio photoresist pattern and sequentially increase or decrease by a predetermined line width than the line width of the intaglio photoresist pattern, and the embossed photoresist is formed on one side of the intaglio or embossed photoresist pattern Photo-bias measurement, characterized in that the resist pattern is sequentially increased or decremented by the predetermined line width to form a pattern scale so that the negative photoresist pattern and the embossed photoresist pattern can be read. Display. The photobias measuring display device according to claim 1, wherein the embossed photoresist pattern sequentially increased or decreased by a predetermined line width rather than the line width of the intaglio photoresist pattern is formed at a interval of 0.05 mu m. In order to easily read the change of the pattern line width due to the etching process after patterning a predetermined material by using a photoresist mask, a plurality of intaglio patterns having a predetermined line width are formed in a predetermined portion of the wafer cutting line by the etching process. On the front side corresponding to the intaglio pattern, the embossed pattern is formed by sequentially decreasing the line width of the intaglio pattern by the predetermined line width, and the number of the embossed pattern is increased or decreased by the predetermined line width on the one side of the intaglio or embossed pattern to form the pattern scale. Etch bias measurement display device characterized in that the configuration to be configured to read the intaglio pattern and the embossed pattern. The apparatus of claim 3, wherein the embossed pattern sequentially increased or decreased by a predetermined line width rather than the line width of the intaglio pattern is formed at intervals of 0.05 μm. The display device as claimed in claim 3, wherein the predetermined material patterned by the etching process is a conductive layer or an insulating layer.