JPH01270244A - Gate array integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to easily search for the same place on a drawing when an abnormal part is found on a chip by providing a character pattern that indicates the positions of cells and wiring patterns on the chip. CONSTITUTION:A ground reinforcing wiring pattern 4 is provided at the third layer being a ground reinforcing wiring layer above the first and second layers being normal signal wiring layers that connect each cell on an internal cell array row 3. Accordingly, the position of each cell can be displayed without invading wiring area by providing character patterns 5 and 6 that become aims of location at this ground reinforcing wiring pattern 4. Since cut character patterns 5 and 6 of number are provided in the longitudinal direction and in the horizontal direction in this way, the positions of objective cells and wiring patterns can be expressed easily and accurately. Hereby, when an abnormal part is found on a chip, the corresponding part on the drawing can be searched for easily.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate array integrated circuit, and more particularly to a gate array integrated circuit having a plurality of cells.

Ryodochi Conventionally, in this type of gate array integrated circuit, the
They inspected the chip using a mirror and found any abnormalities on the chip. The conventional gate array integrated circuit will be explained using FIG. 2. FIG. 6 is a schematic diagram showing a chip 1 of the conventional gate array integrated circuit, 2 is an input/output pad, 3 is an internal cell array column, and 4 is a ground. This is a reinforced wiring pattern.

When such an abnormal location is found on chip 1, the best way to find the location is to count from the edge of the cell array, or express the location of the cell or wiring pattern by the relative position from the input/output bat. There was no other way but to do so. Therefore, when comparing with monitor drawings, etc., there is a drawback that it is very difficult to find the same location on the drawing.

An object of the present invention is to provide a gate array integrated circuit in which when an abnormal location is found on a chip, the same location on a drawing can be easily searched for.

A gate array integrated circuit according to the present invention is a gate array integrated circuit having a plurality of cells, and is characterized in that it has a character pattern indicating at least the position of the cell.

"Shakushu" Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a schematic diagram of an embodiment of a gate array integrated circuit according to the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals. In the figure, a ground reinforcing wiring pattern 4 is provided in the third layer, which is a ground reinforcing wiring layer, above the first and second layers (not shown), which are normal signal wiring layers connecting each cell of the internal cell array column 3. The position of each cell can be displayed without encroaching on the wiring area by providing character patterns 5 and 6 (however, they are actually blank characters) that serve as a guide for rogation in this ground reinforcement wiring pattern 4. This is possible.

In this case, the ground reinforcement wiring pattern 4 around the inside of the chip
Numeral cut-out character patterns 5 and 6 are provided in the vertical and horizontal directions at intervals of 200[/Jfi] (A). These character patterns 5 and 6 make it possible to easily and accurately represent the position of a target cell or wiring pattern. Therefore, it is possible to easily find the same location on the drawing.

Further, in this embodiment, since the character pattern of cut-out characters is provided on the ground reinforcing wiring pattern, it can be easily realized, and there is no need to create a new layer for the character pattern.

In addition, in this embodiment, arithmetic numerals are used as character patterns, but alphabets are used instead, such as rA,
It is clear that similar effects can be obtained by using the patterns "B, C..." or by using both in combination.

As explained above, the present invention provides a gate array integrated circuit with character patterns indicating the positions of cells and wiring patterns on the chip so that abnormalities can be detected by checking with a microscope or the like. When doing so, the position within the chip can be expressed accurately and easily, and the comparison with the monitor diagram can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a gate array integrated circuit according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a conventional gate array integrated circuit. Explanation of symbols of main parts 1... LSI chip 2... Input/output pad 3... Internal cell array column 4... Ground reinforcement wiring pattern 5.6.・・・
...Character pattern

Claims (1)

[Claims] (1) A gate array integrated circuit having a plurality of cells, the gate array integrated circuit having at least a character pattern indicating the position of the cell.