JPH021974A - Gate array integrated circuit - Google Patents
Gate array integrated circuitInfo
- Publication number
- JPH021974A JPH021974A JP14313288A JP14313288A JPH021974A JP H021974 A JPH021974 A JP H021974A JP 14313288 A JP14313288 A JP 14313288A JP 14313288 A JP14313288 A JP 14313288A JP H021974 A JPH021974 A JP H021974A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- location
- wiring pattern
- insulating layer
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract description 5
- 230000003014 reinforcing effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ゲートアレイ集積回路に関し、特にスム及び
配線パターンのロケーションを表示したゲートアレイ集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array integrated circuit, and more particularly to a gate array integrated circuit in which sums and wiring pattern locations are displayed.
Ｕ従来の技術］
従来、ゲートアレイ集積回路において、第２図に示す様
にＬＳＩチップ１０上には、ロケーションの表示は存在
しなかった。従って、任意のスム及び配線パターンのロ
ケーションを知るには、スムアレイの端から数えるか、
もしくは入出力パッドからの相対的な位置より調べる様
になっていた。U Prior Art] Conventionally, in a gate array integrated circuit, there has been no location indication on the LSI chip 10 as shown in FIG. Therefore, to know the location of any sum and wiring pattern, you can count from the edge of the sum array, or
Or, it was supposed to be checked based on the relative position from the input/output pad.
［発明か解決しようとする課題］
上述した従来のゲートアレイ集積回路は、ＬＳＩチップ
１０上にロケーションを示す表示がされていない為、顕
微鏡などにより集積回路をチエツクし異常な箇所を発見
した際に、チップ内の位置を正確に指標する手段か存在
していなかった。そこで、異常な箇所を指標する為に、
スムアレイの端から数えるか、もしくは入出力パッドか
らの相対的な位置より目的のスム及び配線パターンのロ
ケーションを表現していた。しかし、これは、モニタ図
等との照合を行う際、図面上の同一箇所を探すのに時間
と手間かかかり、繁雑であるという欠点かある。[Problem to be solved by the invention] In the conventional gate array integrated circuit described above, there is no display indicating the location on the LSI chip 10, so when checking the integrated circuit with a microscope or the like and finding an abnormal location, However, there was no way to accurately index the position within the chip. Therefore, in order to indicate abnormal points,
The location of the target sum and wiring pattern was expressed by counting from the end of the sum array or by relative position from the input/output pad. However, this method has the disadvantage that it is time consuming and complicated to search for the same location on the drawing when comparing it with a monitor drawing or the like.
［問題点を解決するための手段コ
本発明は、上述の課題を解決し、顕微鏡などにより集積
回路をチエツクし異常な箇所を発見した際に、簡単且つ
正確に当該位置を指標し得るゲートアレイ集積回路を提
供する事を目的としたもので、上記目的を達成するため
チップ上にスム及び配線パターンのロケーションを示す
パターンを設けな゛ことを特徴とする。[Means for Solving the Problems] The present invention solves the above-mentioned problems and provides a gate array that can easily and accurately indicate an abnormal position when checking an integrated circuit using a microscope or the like and discovering an abnormal position. The present invention is intended to provide an integrated circuit, and in order to achieve the above object, it is characterized in that no pattern indicating the location of sums or wiring patterns is provided on the chip.
［実施例］ 次に、本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第１図（ａ）及び（ｂ）は、本発明のゲートアレイ集積
回路の一実施例の断面図及び平面図である。FIGS. 1(a) and 1(b) are a cross-sectional view and a plan view of an embodiment of the gate array integrated circuit of the present invention.
図面中、１０は、本発明のＬＳＩチップであり、以下の
各構成要素からなっている。１は、ロケーション目安絶
縁パターンである。２は、ロケーション目安絶縁パター
ン１を設ける透明性の有る第３絶縁層である。３は、第
３絶縁層２内に形成されたグランド強化配線パターンで
ある。４は、第３絶縁層２の下に配置された透明性の有
る第２絶縁層である。５は、第２絶縁層４内に形成され
た２層配線パターンである。６は、第２絶縁層４の下に
配置された透明性の有る第１絶縁層である。In the drawing, 10 is an LSI chip of the present invention, which is composed of the following components. 1 is a location guide insulation pattern. 2 is a transparent third insulating layer on which the location guide insulating pattern 1 is provided. 3 is a ground reinforcing wiring pattern formed in the third insulating layer 2. 4 is a transparent second insulating layer disposed under the third insulating layer 2. 5 is a two-layer wiring pattern formed within the second insulating layer 4. Reference numeral 6 denotes a transparent first insulating layer disposed under the second insulating layer 4.
８は、第１絶縁層６内に形成された１層配線パターンで
ある。７は、１層配線パターン８と２層配線パターン５
とを接続する１−２スルーホールである。９は、第１絶
縁層６の下に配置された素子形成領域である。１１は、
ＬＳＩチップ１０の周辺部に設けられた複数のＩ１０パ
ッドであり、ＬＳＩチップ１０内部の配線パターンに接
続している。8 is a one-layer wiring pattern formed within the first insulating layer 6. 7 is a first-layer wiring pattern 8 and a second-layer wiring pattern 5.
This is a 1-2 through hole that connects the Reference numeral 9 denotes an element formation region arranged under the first insulating layer 6. 11 is
These are a plurality of I10 pads provided on the periphery of the LSI chip 10 and connected to the wiring pattern inside the LSI chip 10.
例えば、第１図（ａ）では、グランド強化配線パターン
３を内部に持つ第３絶縁層２上にロケーション目安絶縁
パターン１が設けられている。これにより、配線パター
ン領域を侵すことなく、絶縁層の厚みの変化による色の
変化により形成される格子状のパターンによりロケーシ
ョンを表示することか可能である。ロケーション目安絶
縁パターン１は、この場合、ＬＳＩチップ上に５００μ
ｍ間隔で格子状にパターンか設けられている。このパタ
ーンにより目的とするスムおよび配線パターンの位置を
容易に正確に表わすことが可能である。又、ロケーショ
ン目安絶縁パターン１は、透明な絶縁層上に形成されて
いる為、ロケーション目安絶縁パターン１下にある配線
パターン等を見ることも可能である。For example, in FIG. 1(a), a location guide insulating pattern 1 is provided on a third insulating layer 2 having a ground reinforcing wiring pattern 3 therein. This makes it possible to display locations using a grid pattern formed by changing colors due to changes in the thickness of the insulating layer, without encroaching on the wiring pattern area. In this case, the location guideline insulation pattern 1 is 500μ on the LSI chip.
A grid pattern is provided at m intervals. With this pattern, it is possible to easily and accurately represent the position of the intended sum and wiring pattern. Further, since the location guide insulating pattern 1 is formed on a transparent insulating layer, it is also possible to see the wiring pattern and the like under the location guide insulating pattern 1.
［発明の効果］
以上説明したように、本発明は、ゲートアレイ集積回路
において、ＬＳＩチップ上にスム及び配線パターンのロ
ケーションを示すパターンを設けることにより、顕微鏡
などにより集積回路をチエツクし異常な箇所を発見した
際に、チップ内の位置を正確、且つ容易に判断すること
かでき、モニタ図との照合も容易となる効果がある。[Effects of the Invention] As explained above, the present invention provides a gate array integrated circuit with a pattern indicating the location of sums and wiring patterns on an LSI chip, so that the integrated circuit can be checked using a microscope or the like to identify abnormal locations. When a chip is discovered, the position within the chip can be determined accurately and easily, and comparison with the monitor diagram is also facilitated.
第１図（ａ）及び（ｂ）は、本発明のゲートアレイ集積
回路の一実施例の断面図及び平面図である６
第２図は、従来のゲートアレイ集積回路の平面図である
。
１・・・ロケーション目安絶縁パターン２・・・第３絶
縁層
３・・・グランド強化配線パターン
４・・・第２絶縁層
５・・・２ ）？４配線パターン
ｂ・・・第１配線層
７・・１−２スルーホール
８・・１１−配線パターン
９・・・素子形成領域
ＩＯ・・・ＬＳＩチップ
１１・・・Ｉ１０パッド1A and 1B are a cross-sectional view and a plan view of an embodiment of a gate array integrated circuit according to the present invention.6 FIG. 2 is a plan view of a conventional gate array integrated circuit. 1... Location guide insulation pattern 2... Third insulating layer 3... Ground reinforcement wiring pattern 4... Second insulating layer 5... 2)? 4 wiring pattern b...first wiring layer 7...1-2 through hole 8...11-wiring pattern 9...element formation area IO...LSI chip 11...I10 pad
Claims (1)
配線パターンのロケーションを示すパターンを有するこ
とを特徴とするゲートアレイ集積回路。A gate array integrated circuit characterized in that the gate array integrated circuit has a pattern on a chip indicating the location of a sum and a wiring pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14313288A JPH021974A (en) | 1988-10-31 | 1988-06-10 | Gate array integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14313288A JPH021974A (en) | 1988-10-31 | 1988-06-10 | Gate array integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH021974A true JPH021974A (en) | 1990-01-08 |
Family
ID=15331660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14313288A Pending JPH021974A (en) | 1988-10-31 | 1988-06-10 | Gate array integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH021974A (en) |
-
1988
- 1988-06-10 JP JP14313288A patent/JPH021974A/en active Pending
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