JPS6120163A - Use recording mechanism of main memory area - Google Patents

Abstract

PURPOSE:To prevent main memory using record collecting processing from the increase of overhead even if the capacity of the main memory is extremely increased by reading out simultaneously using record bits for plural pages and recording the bits in a resettable memory device. CONSTITUTION:Memory elements 7-0-7-63 are arrayed in parallel so that the using recording bits for 64 pages can be read out simultaneously and also reset. Page using record is executed when the reading of data in a main memory area specified by an address bus 101 is specified from an instruction control part 1 through a bus 102-1 or the writing of data on a data bus 104 in the main memory area specified by an address bus 101 is specified through a bus 102-2. When the reading of page using record is specified from the instruction control part 1 through a bus 102-3, reading address bits are sent to all the page memory elements 7-0-7-63.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a main storage area usage recording mechanism that records for each main storage area whether or not a certain unit of main storage area is used by an information processing device. be.

[Background of the invention]

Conventionally, in order to realize the virtual memory method in information processing devices using virtual memory, the main memory area is divided into units called pages (usually 4 KB), and these pages are used as basic units for processing from an external storage device. The information is read in when it is no longer needed (called page-in), and it is removed when it is no longer needed (page-out).

In this case, in order to effectively use the limited main storage area, the hardware includes a mechanism that records whether each page of the main storage device is used by the information processing device, and the use of the page addressed by the operand. It has instructions to read the record and then reset the usage record bit, and the software (operating system) records the usage of all the areas that can be paged in and out at certain time intervals, and records the usage of all the page-in and page-out areas necessary for processing. When securing the main storage area, the oldest used main storage area (page) is allocated using the Ll(,U method).

However, the usage record bits provided in conventional hardware are usually assigned as part of the storage key for each page for the purpose of memory protection, and the command to read and set the usage record bits is done only once. Each time it is executed, only one page of usage records can be read and reset.

On the other hand, in recent years, the capacity of main storage devices has tended to increase on a large scale, and in order to make effective use of main storage space, the overhead of periodically collecting usage records of all pages in and out possible areas has increased. There's a problem.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a main storage area usage recording mechanism that eliminates the above-mentioned conventional drawbacks and can collect usage records of the main storage area without increasing overhead.

[Summary of the invention]

The present invention separates the main storage area usage record bit from the conventional storage key, and allows the usage record bit for multiple pages to be read and reset at once.

By providing instructions that can read and reset multiple pages of usage records on a storage device configured to do so, the capacity of the main storage device can be greatly increased.

In addition, this prevents an increase in the overhead of main memory usage record collection processing.

[Embodiments of the invention]

FIG. 1 is a block diagram of an embodiment of the present invention, in which a storage area usage recording mechanism 48 is provided in the main memory control section 2. As shown in FIG.

FIG. 2 is a detailed diagram of the storage area usage recording mechanism, and will be described below with reference to FIG.

In this embodiment, storage elements 7-0 to 7- with a capacity of 8 Kbit are used.
63 are arranged in parallel so that 64 pages can be read and reset at one time. Therefore, 8192 (8Kb) divided into pages
it storage element) X 4096 (1 page - 4K By
te)X 64 = 20 Bytes It has storage area (page) usage recording bits for a main storage capacity of 2 GB.

This page usage record is normally sent from the command control unit 1 to the bus line 10.
2-1, a data read instruction for the main storage area specified by the address bus 101, or a bus line 102-2.
The data is recorded when an instruction to write data on the data bus 104 is given to the main storage area designated by the address bus 101 via the address bus 101.

In other words, bits 14 to 19 of the address (address bus 101) at the time of main memory access are decoded by the decoder 5, and the page usage recording memory elements 7-0 to 7-63 are stored in the corresponding memory elements 7-7-1 (i to 63). ) Select (CEi) (,
, furthermore, the bus line 10 is placed in the area indicated by bits 1 to 13 of the address of the storage element selected via the bus line 101-1.
'1' is recorded (WP) by the main memory device read or write instruction pulse via bus 102-4. A signal obtained by inverting the reset instruction signal of
Except for the reset instruction, '1'' is input (WDi) to the page usage record storage element 7-i. In this way, the page usage information corresponding to the main memory area accessed by the instruction control unit is Records use pages.

It is recorded in the recording storage element each time it is accessed.

Next, an instruction to read the page usage record addressed by the address bus 101 is sent from the instruction control unit 1 to the bus 102-3.
bits 1 to 13 of the address are transmitted to all page storage elements 7-0 to 7 via bus 101-1.
-63, and all page storage elements 7-0
~7-63 is selected via bus 102-3 ((Jo~C
Ee3) As a result, page usage record information for one page is read to 64 in the area indicated by bits 1 to 13 of the atto 1 NOS bus 101 (DO to D63) and is sent to the command control unit via the bus 105 and the bus 1038. 1. Further, after reading, when a reset instruction is sent from the instruction control unit 1 via the bus 102-4 at the same address as the reading, C of all the page usage record storage elements 7-0 to 7-63 is
Eo~63 and WP double signal input, wDO~63 receives 10" from bus 102-4 through 108, and 64 in the area indicated by bits 1 to 13 of address bus 101.
The page usage record for one page is reset.

Therefore, in this embodiment, the page usage record information for 64 pages can be read and reset with one instruction, and the page usage record information can be read out for 1 page with one instruction in the past. , has 64 times the ability for reset operations.

〔Effect of the invention〕

According to the present invention, main memory area (page) 8 - Regarding reading and resetting of main memory area (page) usage record information for effective use, it is possible to process multiple pages at a time. The effect of improving performance is Δ5.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of its main storage area usage recording mechanism. 1... Instruction control unit 2... Main memory control unit 3.
・・Main storage device 4 ・Main fk area usage record @structure 5 ・Decoder 8 ・'01 (, circuit 9
...Inverter

Claims (1)

[Claims] 1. A device that records usage records for each area of a main storage area accessed by an information processing device, which has a usage record storage device configured to read and reset usage record information for a plurality of main storage areas at once. A main storage area usage recording mechanism characterized in that a plurality of pieces of main storage area usage recording information are read out and reset by a single read instruction or a reset instruction.