JPS61199121A - Converting circuit for speed conversion system - Google Patents

Abstract

PURPOSE:To realize the small scale converting circuit of a speed conversion system by converting data, which are subjected to speed conversion systems different from each other, to data subjected to each other's speed conversion systems. CONSTITUTION:A memory 7a stores successively high speed data subjected to speed conversion A and outputs successively high speed data in accordance with the address given from a control circuit 7aa for the purpose of taking out high speed data subjected to speed conversion B. A memory 7b stores successively high speed data subjected to speed conversion B and outputs successively high speed data in accordance with the address given from a control circuit 7bb for the purpose of taking out high speed data subjected to speed conversion A. When this converting circuit is applied to a data communication system, low speed data from a low speed data terminal 1 is converted to high speed data subjected to speed conversion A by a speed converting circuit 2 and is converted to high speed data subjected to speed conversion B by a converting circuit 7 and passes a speed converting circuit 5 to become low speed data and is processed in a low speed data terminal 6.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to data communication when two terminals that handle low-speed data at the same speed are connected at high speed, and when the speed conversion methods of both terminals are different. The present invention relates to a conversion circuit using a speed conversion method, which is necessary for this purpose.

[Conventional technology]

Conventionally, in order to send and receive low-speed data that has been subjected to different speed conversion methods at high speed, the speed conversion method is changed by first inverting the speed of the high-speed data to low-speed data and then converting it back to high-speed data using another method. This was done through a circuit.

FIG. 3 shows a data communication system to which a conventional speed conversion type conversion circuit is applied. In Figure 3, 1.6 is a low-speed data terminal that outputs low-speed data, 2.5 is a speed conversion circuit that converts low-speed data output from low-speed data terminal 1.6 into high-speed data, and 3 is a first speed. The high-speed data that has been subjected to speed conversion using speed conversion method A as a conversion method (hereinafter referred to as "speed conversion A") is subjected to speed conversion using speed conversion method B as a second speed conversion method (hereinafter referred to as "speed conversion B"). ) method conversion circuit that converts to low-speed data,
Reference numeral 4 denotes a system conversion circuit that converts high-speed data subjected to speed conversion B to low-speed data subjected to speed conversion A.

Next, the operation of such system conversion circuits 3 and 4 will be explained. First, the operation of the system conversion circuit 3 will be explained. The system conversion circuit 3 stores data whose speed has been converted from low speed to high speed according to speed conversion system A to a memory AI (not shown).
The speed conversion method A is temporarily stored in the memory A1.
The data is read out by the control circuit AI (not shown) according to the inverse conversion of , the data read out from the memory A1 is temporarily stored in the memory A2 (not shown), and the data is read out from the memory A2 by the control circuit A2 according to the speed conversion method B.
(not shown) reads the data. In this manner, the system conversion circuit 3 converts high-speed data subjected to speed conversion A to low-speed data subjected to speed conversion B.

Next, the operation of the system conversion circuit 4 will be explained.

The system conversion circuit 4 temporarily stores data whose speed has been converted from low speed to high speed according to the speed conversion system B in a memory Bl (not shown), and from this memory B1, data is converted from a low speed to a high speed according to the speed conversion system B, and is stored in a control circuit Bl (not shown) according to the inverse conversion of the speed conversion system B. ), the data read from the memory B1 is temporarily stored in the memory B2 (not shown), and the data is read out from the memory B2 according to the speed conversion method A by the control circuit B2.
(not shown) reads the data. In this way, the system conversion circuit 4 converts the high speed data subjected to speed conversion B to the low speed data subjected to speed conversion A.

Next, the operation when the system conversion circuits 3 and 4 are applied to a data communication system will be explained using FIG.

Low-speed data output from the low-speed data terminal 1 is converted into high-speed data subjected to speed conversion A by the speed conversion circuit 2. This high-speed data is converted into low-speed data subjected to speed conversion B in the system conversion circuit 3 as described above, and is output from the system conversion circuit 3. The low-speed data is input to the system conversion circuit 4 and subjected to speed conversion B to be converted into high-speed data again. This high-speed data is converted into low-speed data subjected to speed conversion B by the speed conversion circuit 5. The above-mentioned low-speed data is input to the low-speed data terminal 6 and undergoes processing.

In the above case, the case where data outputted from the low-speed data terminal 1 is inputted to the low-speed data terminal 6 has been described, but the operation is similar in the reverse case.

[Problem that the invention seeks to solve]

As described above, the conventional format conversion circuits 3 and 4 have memories A1 . A2. Control circuit At, A2 and memory B1.
B2. Since it is composed of control circuits Bl and B2, there is a problem in that the circuit scale becomes large.

[Means for solving problems]

In order to solve these problems, the present invention provides a first memory that temporarily stores data whose speed has been converted from low speed to high speed according to a first speed conversion method, and a
A first control circuit reads data according to a second speed conversion method that handles data at the same speed as the speed conversion method but differs only in the conversion method; A second memory for temporary storage and a second control circuit for reading data from this memory according to the first speed conversion method are provided.

[Effect]

In the present invention, data that has been subjected to different speed conversion methods is converted into data that has been subjected to other speed conversion methods.

〔Example〕

FIG. 1 shows an embodiment of the conversion circuit of the speed conversion method according to the present invention, and FIG. 2 shows the case where this embodiment is applied to a data communication system.
As shown in the figure. In FIGS. 1 and 2, 7 is a conversion circuit of the speed conversion method, 7a is a first memory, 7aa is a first control circuit, 7b is a second memory, and 7bb is a second control circuit. In FIG. 2, the same or equivalent parts as in FIG. 3 are given the same reference numerals.

Next, the operation of this embodiment shown in FIG. 1 will be explained. The memory 7a sequentially stores the high speed data subjected to the speed conversion A, and sequentially outputs the high speed data according to the address given by the control circuit 7aa in order to retrieve the high speed data subjected to the speed conversion B. The memory 7b sequentially stores the high-speed data subjected to speed conversion B, and sequentially outputs the high-speed data according to the address given by the control circuit 7bb in order to retrieve the high-speed data subjected to speed conversion A.

Next, a case where this embodiment is applied to a data communication system will be explained using FIG. 2. Low-speed data output from the low-speed data terminal 1 is converted into high-speed data subjected to speed conversion A by the speed conversion circuit 2. The high-speed data subjected to speed conversion A is converted into high-speed data subjected to speed conversion B by the conversion circuit 7 of the speed conversion method, and inputted to the speed conversion circuit 5, and converted to low-speed data subjected to speed conversion B. This low-speed data is then processed by the low-speed data terminal 6.

〔Effect of the invention〕

As explained above, the present invention temporarily stores data whose speed has been converted from low speed to high speed according to the first speed conversion method in the first memory, and from this memory by the first control circuit, converts the data into the second speed conversion method. The second memory temporarily stores the data whose speed has been converted from low speed to high speed according to the second speed conversion method, and the second control circuit reads the data from this memory according to the first speed conversion method. As a result, data that has been subjected to different speed conversion methods can be converted into data that has been subjected to another speed conversion method, and there is an effect that a small-scale conversion circuit of the speed conversion method can be realized.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of a conversion circuit of a speed conversion method according to the present invention, Fig. 2 is a system diagram showing a case where this embodiment is applied to a data communication system, and Fig. 3 is a circuit diagram showing a case where this embodiment is applied to a data communication system. It is a system diagram showing a communication system. 1.6...Low speed data terminal, 2.5...Speed conversion circuit, 7...Speed conversion method conversion circuit, 7a, 7
b-...Memory, 7aa, 7bb...Control circuit.

Claims (1)

[Claims] A first memory that temporarily stores data that has been speed-converted from low speed to high speed according to the first speed conversion method, and a second memory that temporarily stores data that has been speed-converted from low speed to high speed according to the first speed conversion method; a first control circuit that reads data according to a speed conversion method; a second memory that temporarily stores data that has been speed-converted from low speed to high speed according to a second speed conversion method; A conversion circuit using a speed conversion method, comprising: a second control circuit that reads data according to the speed conversion method.