JPS6061849A - Storage circuit for input and output history information - Google Patents

Storage circuit for input and output history information

Info

Publication number
JPS6061849A
JPS6061849A JP58168704A JP16870483A JPS6061849A JP S6061849 A JPS6061849 A JP S6061849A JP 58168704 A JP58168704 A JP 58168704A JP 16870483 A JP16870483 A JP 16870483A JP S6061849 A JPS6061849 A JP S6061849A
Authority
JP
Japan
Prior art keywords
input
output
history information
information
processing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58168704A
Other languages
Japanese (ja)
Inventor
Shinjiro Tsumura
津村　信二郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58168704A priority Critical patent/JPS6061849A/en
Publication of JPS6061849A publication Critical patent/JPS6061849A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To easily output input and output history information to external equipment at a high speed on correspondence basis by providing an input and an output memory separately and independently, and storing corresponding input and output pieces of history information in the same addresses of those memories. CONSTITUTION:Input information 2 from external input equipment 1 is received by a reception processing circuit 3 and branched into two and sent to an editing processing circuit 4 while stored in an input history information storage memory 5 in time series. The editing processing circuit 4 receiving the input information 2, on the other hand, performs editing processing for external output equipment 9 and sends the result to a transmission processing circuit 6; one is outputted as output information 8 to the external output equipment 9, and the other is stored in the output history information storage memory 7. An input/output history editing processing circuit 12 reads the same addresses of input and output history information storage memories 5 and 7 at an input/output history information output request from an external output equipment 13, and receives and outputs input history information 10 and output history information 11 to the external output equipment 13 on correspondence basis.

Description

【発明の詳細な説明】 本発明は入出力情報をメモリに蓄積して外部機器に処理
内容の履歴情報を出力する方法に関し、入力履歴情報お
よび出力履歴情報を容易に並記対応して出力可能とした
入出力履歴情報蓄積回路に関するものである。[Detailed Description of the Invention] The present invention relates to a method of storing input/output information in a memory and outputting history information of processing contents to an external device, which allows input history information and output history information to be easily written in parallel and output. The present invention relates to an input/output history information storage circuit.

従来、この種の入出力履歴情報蓄積回路は１個のメモリ
で構成され、そのメモリに蓄積される入力ＦｉＮ情報お
よび出力履歴情報は入力機器および出力機器の処理速度
の相違によシ入力履歴情報、出力履歴情報交互に発生し
ないため、入出力対応の関係なく発生順にメモリに蓄積
される。この蓄積された入出力履歴情報を入力、出力と
を並記対応させて外部機器へ出力する場合、全メモリを
横飛して対応関係を深す処理が必要であり処理速度が遅
くなるという欠点があった。Conventionally, this type of input/output history information storage circuit has been configured with one memory, and the input FiN information and output history information stored in the memory are different from each other due to the difference in processing speed between the input device and the output device. , since the output history information does not occur alternately, it is stored in the memory in the order of occurrence, regardless of input/output correspondence. When outputting this accumulated input/output history information to an external device with parallel correspondence between input and output, it is necessary to skip all memory to deepen the correspondence, which slows down the processing speed. was there.

本発明は入力用、出力用各々メモリを分離独立し、入力
履歴情報および出力Ｈ層情報を対応するメモリに蓄積し
、各々のメモリの同一番地には入出力対応した履歴情報
を蓄積することによって入出力履歴情報を並記対応して
外部機器に出力する場合処理を容易とし、上記欠点を解
決するとともに処理速度が早い入出力履歴情報蓄積回路
を提供するものである。The present invention separates and independent memories for input and output, stores input history information and output H layer information in the corresponding memories, and stores history information corresponding to input and output in the same location of each memory. It is an object of the present invention to provide an input/output history information storage circuit that facilitates processing when outputting input/output history information to an external device in parallel correspondence, solves the above-mentioned drawbacks, and has a high processing speed.

本発明を構成するには外部入力機器から入力情報を受信
し該入力情報を２分岐する受信処理回路と、２分岐され
た一方の入力情報を受信する編集処理回路と、他方の入
力情報を入力履歴情報として発生順に蓄積するメモリ回
路１と、前記編集処理回路から送出される出力情報を受
信し、該出力情報を２分岐し一方を外部出力機器１へ送
出する送信処理回路と、他方の出力情報を出力履歴情報
として発生順ＶＣ蓄積するメモリ回路２と、該メモリ１
，２から前記入出力履歴情報゛を読出し外部出力機器２
へ出力する入出力履歴情報編集処理回路が必要である。The present invention includes a reception processing circuit that receives input information from an external input device and branches the input information into two, an editing processing circuit that receives one of the two branched input information, and inputs the other input information. A memory circuit 1 that stores historical information in the order of occurrence; a transmission processing circuit that receives the output information sent from the editing processing circuit, branches the output information into two, and sends one to the external output device 1; and the other output. A memory circuit 2 that stores information as output history information in VC in the order of occurrence, and the memory 1
, 2 reads the input/output history information from the external output device 2.
An input/output history information editing processing circuit is required.

次だ本発明の一実施例について図面を参照して説明する
。Next, one embodiment of the present invention will be described with reference to the drawings.

本発明は外部入力様器Ａ１と、入力情報２と、受信処理
回路３と、編集処理回路４と、入力履歴情報蓄積メモリ
５と、送信処理回路６と、出力履歴情報蓄積メモリ７と
、出力情報８と、外部出力機器Ａ９と、入力履歴情報１
０と、出力Ｐ１５．！Ｉ！￥：情報１１と、入出力履歴
情報編集処理回路１２と、外部出力機器Ｂ１３とを含む
。The present invention includes an external input device A1, input information 2, reception processing circuit 3, editing processing circuit 4, input history information storage memory 5, transmission processing circuit 6, output history information storage memory 7, and output Information 8, external output device A9, and input history information 1
0 and output P15. ! I! ¥: Includes information 11, input/output history information editing processing circuit 12, and external output device B13.

外部入力機器Ａ１から入力する入力情報２を受信処理回
路３で受信しこの入力情報２を２分岐し編集処理回路４
に送出すると同時に入力履歴情報蓄積メモリ５に時系列
順尤蓄積してゆく。一方、入力情報２を受信した編集処
理回路４は外部出力機器Ａ９に対する編集地理を行ない
送信処理回路６に送出する。送信処理回路６では、この
情報を２分岐して一方は出力情報８として外部出力機器
Ａ９に出力し、他方は出力履歴情報蓄積メモリ７に蓄積
される。この状態で外部出力機器Ｂ　］、　３からの入
出力履歴情報出力要求によシ、入出力履歴情報編集処理
回路１２は入力履歴情報蓄積メモリ５および出力履歴情
報蓄積メモリ７から各々同一番地の内容を読出し入力履
歴情報１０および出力履歴情報１１を受信して並記対応
して外部出力機器１３へ出力する。A reception processing circuit 3 receives input information 2 input from an external input device A1, branches this input information 2 into two, and sends it to an editing processing circuit 4.
At the same time, the input history information is stored in the input history information storage memory 5 in chronological order. On the other hand, the editing processing circuit 4 that has received the input information 2 performs editing geography on the external output device A9 and sends it to the transmission processing circuit 6. The transmission processing circuit 6 branches this information into two parts, one of which is output as output information 8 to the external output device A9, and the other is stored in the output history information storage memory 7. In this state, in response to an input/output history information output request from the external output device B], 3, the input/output history information editing processing circuit 12 retrieves the contents at the same location from the input history information storage memory 5 and the output history information storage memory 7, respectively. It reads out input history information 10 and output history information 11, and outputs them to external output device 13 in parallel correspondence.

以上説明したように人力用および出力用、各々、履歴情
味蓄積メモリを有することによシ入力履歴情と出力履歴
情報を並記対応させる処理が旧年になシ、処理速度を向
上できる効果がある。As explained above, by having historical information storage memories for human power and output, the process of parallelizing input historical information and output historical information is not required in the past, and the processing speed can be improved. There is.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例ン示す構成図である。 １・・・・・・外部入力機器、２・・・・・・入力情報
、３・・・・・・受信処理回路、４・・・・・・編集処
理回路、５・・・・・・入力履歴情報蓄積メモリ、６・
・・・・・送信処理回路、７・・・・・・出力履歴情報
蓄積メモリ、８・・・・・・出力情報、１０・・・・・
・入力履歴情報、１１・・・・・・出力履歴情報、１２
・・・・・・入出力履歴情報編集処理回路、１３・・・
・・・外部出力機器Ｂ０The figure is a configuration diagram showing one embodiment of the present invention. 1... External input device, 2... Input information, 3... Reception processing circuit, 4... Editing processing circuit, 5... Input history information storage memory, 6.
...Transmission processing circuit, 7...Output history information storage memory, 8...Output information, 10...
・Input history information, 11... Output history information, 12
...Input/output history information editing processing circuit, 13...
...External output device B0

Claims (1)

【特許請求の範囲】[Claims] 外部入力機器から入力情報を受信し該入力情報を２分岐
する受信処理回路と、２分岐された一方の入力情報を受
信する編集処理回路と、他方の入力情報を入力履歴情報
として発生順に蓄積する第１のメモリ回路と、前記編集
処理回路から送出される出力情報を受信し該出力情報を
２分岐し一方を第１の外部出力機器へ送出する送信処理
回路と、他方の出力情報を出力履歴情報として発生順に
蓄積する第２のメモリ回路２と、前記第１と第２のメモ
リから前記入出力履歴情報を読出し第２の外部出力機器
へ出力する入出力履歴情報編集処理回路とを有すること
を特徴とする入出力履歴情報蓄積回路。A reception processing circuit receives input information from an external input device and branches the input information into two, an editing processing circuit receives one of the two branched input information, and stores the other input information as input history information in the order of occurrence. a first memory circuit, a transmission processing circuit that receives output information sent from the editing processing circuit, branches the output information into two, and sends one to a first external output device; and an output history that records the other output information. It has a second memory circuit 2 that stores information in the order of occurrence, and an input/output history information editing circuit that reads out the input/output history information from the first and second memories and outputs it to a second external output device. An input/output history information storage circuit characterized by:
JP58168704A 1983-09-13 1983-09-13 Storage circuit for input and output history information Pending JPS6061849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58168704A JPS6061849A (en) 1983-09-13 1983-09-13 Storage circuit for input and output history information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58168704A JPS6061849A (en) 1983-09-13 1983-09-13 Storage circuit for input and output history information

Publications (1)

Publication Number Publication Date
JPS6061849A true JPS6061849A (en) 1985-04-09

Family

ID=15872900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58168704A Pending JPS6061849A (en) 1983-09-13 1983-09-13 Storage circuit for input and output history information

Country Status (1)

Country Link
JP (1) JPS6061849A (en)

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