JPS60139343U - High speed code conversion circuit - Google Patents
High speed code conversion circuitInfo
- Publication number
- JPS60139343U JPS60139343U JP2691084U JP2691084U JPS60139343U JP S60139343 U JPS60139343 U JP S60139343U JP 2691084 U JP2691084 U JP 2691084U JP 2691084 U JP2691084 U JP 2691084U JP S60139343 U JPS60139343 U JP S60139343U
- Authority
- JP
- Japan
- Prior art keywords
- digit
- storage means
- addition
- high speed
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例のブロック図、第２図は第１図
の部分う゛ロック図、第３図は第１図の動作を説明する
フローチャート、第４図は本考案の他の実施例のＲＯＭ
アドレスを示す構成図であ一〇お５．７．１０００、。
８．２００．ヵ。ニヤ、３−Ｌ／−ジスタ（ＲＡＭ）、
４・・・コントローラ、５・・・切換器、６・・・デー
タレジスタ、７・・・バッファ、訃・・し ′ジスタ、
９・・・アドレスデコーダ、１０・・・マイクロコンピ
ュータ、１１・・・アドレスバス、１２・・・デーータ
バス、１３・・・桁データ（Ｂｂｙ Ｂ□）、１４・・
・変換 。
（アドレス）データ山トＢ５）、１５−・・・スタート
Ｘ信号、１６・・・スイッチ切換信号、２１・・・桁
コント −ロール信号、２２・・・レジスタア
ドレス信号、である。FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a partial block diagram of FIG. 1, FIG. 3 is a flowchart explaining the operation of FIG. 1, and FIG. 4 is another embodiment of the present invention. Example ROM
A configuration diagram showing the address 1005.7.1000. 8.200. Ka. Niya, 3-L/-Jista (RAM),
4...Controller, 5...Switcher, 6...Data register, 7...Buffer,
9... Address decoder, 10... Microcomputer, 11... Address bus, 12... Data bus, 13... Digit data (Bby B□), 14...
·conversion . (address) data mountain B5), 15--...start X signal, 16--switch switching signal, 21--digit control signal, 22--register address signal.
Claims (1)
１の記憶手段と、この第１の記憶手段から入力された数
値に対応した前記変換データを桁毎に読出す−よう制御
する制御手段と、前記第１の、記憶手段の読出された出
力を一方の入力として加算する加算手段と、この加算手
段の加算出力を一時記憶し出力を前記加算手段の他方の
入力として、供給する第２の記憶手段とを含み、前些第
１の記憶手段から出力された前記変換デー７を前記加算
手段において桁毎にワードシリアルに加算してコード変
換することを特徴とする高速コード変換口−路。A first storage means in which conversion data corresponding to the numerical value of that digit is written for each digit, and control to read out the conversion data corresponding to the numerical value inputted from this first storage means for each digit. a control means; an addition means for adding the read output of the first storage means as one input; temporarily storing the addition output of the addition means; supplying the output as the other input of the addition means; and a second storage means, the conversion data 7 outputted from the first storage means is word-serially added digit by digit in the addition means to convert the code. -Route.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2691084U JPS60139343U (en) | 1984-02-27 | 1984-02-27 | High speed code conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2691084U JPS60139343U (en) | 1984-02-27 | 1984-02-27 | High speed code conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60139343U true JPS60139343U (en) | 1985-09-14 |
Family
ID=30523365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2691084U Pending JPS60139343U (en) | 1984-02-27 | 1984-02-27 | High speed code conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60139343U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58181142A (en) * | 1982-04-15 | 1983-10-22 | Toshiba Corp | M notation-n notation converting device |
-
1984
- 1984-02-27 JP JP2691084U patent/JPS60139343U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58181142A (en) * | 1982-04-15 | 1983-10-22 | Toshiba Corp | M notation-n notation converting device |
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