JPS58181142A - M notation-n notation converting device - Google Patents

Abstract

PURPOSE:To perform the (m)-notation-(n)-notation conversion in a high speed, by using outputs of a code flag for an (m)-notation number, an entery register for an (m)-notation number, and a digit display means as an address to read out the output of an ROM provided with an (n)-notation number conversion table and processing this output. CONSTITUTION:The (m)-notation (binary in this example) code inputted from a terminal Ti is inputted to a code flag register 1 and an entry register 2. The MSB indicating the positive or negative sign of the (m)-notation code is taken into the register 1. The input signal of the register 2 is divided by (q)-number (=4) bits and is shifted to the lower side in units of (q)-number of bits, and lowest (q)-number of bits are taken out to the external, and the taken-out digit is displayed in a digit pointer 3. Outputs of registers 1 and 2 and the pointer 3 are used as an address to read out corresponding contents of an ROM 4 provided with the conversion table of (n)-notation (decimal) numbers, and an output Vp is inputted to an adder 5 and is added to the output of an accumulating register 6. The output of the adder 5 is inputted to the register 6, and this operation is repeated until the value of the pointer 3 becomes 0, and the output of the register 6 is taken out from a terminal To.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an m-adic-n-adic (m,
(n is a natural number) Concerning the conversion device.

When converting an m-value number into an n-ary number in a digital data processing device, for example, as a method for converting from a binary number to a decimal number (for example, one encoded by the binary coded decimal system (J30D)), A known method is to divide a binary number into digits each consisting of several bits, convert each digit to a decimal number, and then calculate the phase of the 10-decimal number obtained by simplification, taking into account each digit. ing. However, in this method, when the binary number is negative, it is common to first take the complement of the binary number and then perform the above conversion, which is rare. For this reason, the time it takes to take the complement becomes an overhead time that cannot be ignored as a high-speed conversion device. In addition, if the above Ryohou operation is to be executed on dedicated hardware without using an arithmetic circuit for the four arithmetic operations, it is necessary to incorporate a separate means for taking the complement, which would complicate the p1 device. However, it had the disadvantage of being expensive.

An object of the present invention is to provide a conversion device that has a simple circuit configuration and can perform m-ary to n-ary conversion at high speed.

FIG. 1 shows an embodiment of the present invention. In the figure, T] is a binary number, in the example shown, a 15-bit 2
This is a terminal that receives a base number code and a 1-bit code that represents the code. It is assumed that the binary code represents a binary number or, in the case of a negative value, a one's complement number. The code is MEIB (most significant bit) of the 16-bit code.
The sign flag register 1 receives and holds a sign code of 1. 2 is a numeric register with a capacity of 16 bits, divided into digits of 4 bits each, so that each bit can be shifted toward the lower side in the figure in 4-bit positions. ing. The lowest 4 bits can then be taken out. 3 is a digit pointer which is controlled by a control device (not shown) and displays the digit taken out from the number register 2. 4 is a read-only storage device (ROM) that stores the code code S sent from the code flag register 1, the digit code P sent from the digit pointer 3, and the digit register 2.
The code 1-H representing a one-digit numerical value (absolute value) sent from V is received as an address, and the contents of that address V
Output p as a decimal number expressed as an absolute value. In order to play such a role, the ROM 4 stores lO base numbers <
e-vs-value expression) V is stored in the form of a conversion table that can be converted into a value. The output of the ROM 4 is supplied to the 10,000 inputs of the adder 5. The output of adder 5 is fed to the input of accumulating register lo, and the output of accumulating register lo is fed to adder 5.
The output terminal T0 is supplied to the other input of the output terminal T0. Accumulation register 6 has six digits B as shown.
Each digit consists of 4 bits. The adder 5 is capable of adding 6-digit BOD.

Table 1 The binary number BGo""811 (of which B.o is the sign bit in MSfl) is divided into 4-bit hexadecimal numbers, and the 16a number of each digit is Hp (p is θ ~ 3゜However, p=
When it is Q, it consists of a 3-bit binary number and a sign bit.

), then the decimal number X corresponding to Ba1l”BIll
is the following equation (1)′! ! It is expressed as Take(2).

When binary number ≧O, X = HoXJ6”+ H,X16” XH,XI6
'10H, (l'X16"
+H,"1)X+6'+ (H,")X16°+1)・
・・・・・・Scream・・・・・・・・・・・・ (2) Here,
■■p O+1) represents the one's complement of Hp. R.O.
M4 is the BOD expression (i.e. 1
It can be said that it stores the decimal conversion value for each hexadecimal digit. Then, the adder 5 uses the above formula (1), (
It was used to find the sum of each term in 2).

Further, the accumulation register 6 is used to hold intermediate zeros. Furthermore, digit pointer 3 is used to indicate the hexadecimal digit.

The process of conversion operation is as shown in FIG. That is, when the conversion operation is started (101), the cumulative V distal is set to zero and the digit pointer is set to 3 (102).
. The lowest 4 bits of digit register 2, along with the output of digit pointer 3 and the output of sign flag register 1, are R(l
M4, the corresponding decimal number is taken out, and the adder 5 multiplies it with the contents of the accumulation register 6, and the addition result (
1) is taken as the new content of the accumulation register 6 (103
). Next, the content of digit pointer 3 is checked and if it is not zero, the content of digit pointer 3 is decreased by 1, and
The contents of the numeric register 2 are shifted to a one-digit (4-bit) distributed quantity, ie, to the smallest digit (10). Thereafter, steps 103 to 105 are repeated, and the conversion operation ends when it is confirmed that the contents of the one stone pointer 3 have become zero (106).

As described above, 2 of the complement representation given to the terminal T1
The base number is connected to terminal T. It can be extracted as a 0-decimal number expressed as an absolute value. In addition, the output of sign flag register 1 is
By using it as it is as the output of the conversion device, 1
A code representing the sign of a 0-decimal number can be obtained.

Above, we have described the case of converting a binary number into an IO value number, but a table for converting a decimal number (BOD) to a binary number is prepared in ROM4, and a binary adder is added instead of the IO base addition $65. If we use

In addition to converting between binary numbers and tO base numbers, m,
When n is an arbitrary natural number, it can be applied to conversion between m-ary numbers and n-ary numbers.

As mentioned above, in the conversion table, m-ary numbers (or lO
Since the converted value (n-adic number) is prepared by converting the m-adic number (a number), a complementer is not required even when the m-adic number is negative. Further, since the operation corresponding to the creation of the complement and the addition operation can be performed simultaneously, the overhead time required for the creation of the complement is unnecessary. Therefore, the conversion operation is correspondingly faster.

[Brief explanation of drawings]

FIG. 1 is a butchiard showing an embodiment of the converting device of the present invention. 1... Sign flag register, 2... Arrangement register,
3... Digit pointer, 4... Read-only storage device, 5
... Adder, 6... Accumulation register. Applicant's agent Kiyoshi Inomata

Claims (1)

[Claims] code flag holding means for holding a code flag of an m-ary number (m is a natural number); m-ary number holding means for outputting in order from the digit, digit display means for outputting a code indicating the digit position output from the m-ary number holding means, the code flag holding means, the m-ary number holding means, and the digit display. a read-only storage device that receives the output of the means as an address and outputs the contents of the address as a converted n-ary number (n is a natural number), an accumulation register, and the contents of the accumulation register and the storage device. An m-ary to n-ary conversion device comprising an adder for adding, and a control means for causing the adder to perform addition until all the contents held in the m-ary number holding means are outputted.