JPS6486624A - Hexadecimal converter - Google Patents

Hexadecimal converter

Info

Publication number
JPS6486624A
JPS6486624A JP24283987A JP24283987A JPS6486624A JP S6486624 A JPS6486624 A JP S6486624A JP 24283987 A JP24283987 A JP 24283987A JP 24283987 A JP24283987 A JP 24283987A JP S6486624 A JPS6486624 A JP S6486624A
Authority
JP
Japan
Prior art keywords
data
input
section
decimal
hexadecimal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24283987A
Other languages
Japanese (ja)
Other versions
JPH0783268B2 (en
Inventor
Hiroaki Kawada
Noboru Tamai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI OFFICE SYST
NEC Corp
NEC Office Systems Ltd
Original Assignee
NIPPON DENKI OFFICE SYST
NEC Corp
NEC Office Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON DENKI OFFICE SYST, NEC Corp, NEC Office Systems Ltd filed Critical NIPPON DENKI OFFICE SYST
Priority to JP62242839A priority Critical patent/JPH0783268B2/en
Publication of JPS6486624A publication Critical patent/JPS6486624A/en
Publication of JPH0783268B2 publication Critical patent/JPH0783268B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To reduce an overall conversion time by applying sequential arithmetic processing at the time of input of each digit data of a decimal data. CONSTITUTION:After in output data of a 2-input adder section 1 receiving an input decimal data at its input terminal 1a is stored in a register section 2, the data is multiplied by 10 at an arithmetic section 3 and the result is to other input of the 2-input adder section 1, and the register section 2 is configurated in a way that an output hexadecimal data is obtained at an output terminal of the adder section 1 or the register section 2 by revising the stored data in receiving each digital data of the O input decimal data sequentially. That is, the arithmetic processing of the decimal/hexadecimal conversion is applied sequentially synchronously with the input of each digit data. Thus, the processing time is reduced.
JP62242839A 1987-09-29 1987-09-29 Hexadecimal converter Expired - Lifetime JPH0783268B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242839A JPH0783268B2 (en) 1987-09-29 1987-09-29 Hexadecimal converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242839A JPH0783268B2 (en) 1987-09-29 1987-09-29 Hexadecimal converter

Publications (2)

Publication Number Publication Date
JPS6486624A true JPS6486624A (en) 1989-03-31
JPH0783268B2 JPH0783268B2 (en) 1995-09-06

Family

ID=17095060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242839A Expired - Lifetime JPH0783268B2 (en) 1987-09-29 1987-09-29 Hexadecimal converter

Country Status (1)

Country Link
JP (1) JPH0783268B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181142A (en) * 1982-04-15 1983-10-22 Toshiba Corp M notation-n notation converting device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181142A (en) * 1982-04-15 1983-10-22 Toshiba Corp M notation-n notation converting device

Also Published As

Publication number Publication date
JPH0783268B2 (en) 1995-09-06

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