JPS61191177A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To widen dynamic ranges by making the time of accumulation of respective charges different to prevent the amount of charge of at least two picture elements for which charge is to be mixed from arriving at the overflow level. CONSTITUTION:The time of accumulation of charge of two picture elements is made different to prevent at least one of them from becoming the state of saturation. For instance, out of two picture elements to be mixed, accumulation of charge is made in patterns of P0P1P2 for one picture element, and accumulation of charge is made in patterns of P0P7P2, shortened in time of accumulation of charge than the former pattern, for another picture element. Thus, when the two picture elements are mixed, the intensity of illumination of light becomes the state of saturation for the first time at a point P8. Accordingly, the saturated intensity of illumination of light, that is, its dynamic range can be widened remarkably.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a CCD (Ch
(coupled device) relates to a solid-state image sensor.

[Prior art]

FIG. 6 is a potential diagram of a CCD solid-state image sensing device with a conventional cross-gate structure and a frame transfer method.
c3. c4 and the corresponding clock pulse voltage φ1
．． φ2. φ3. The schematic diagrams 6(b) and 6(c) showing φ4 show the potentials of the portions corresponding to the gate electrodes G, .about.G4.

During the charge conversion period, high-level voltages are applied as clock pulse voltages φ1 and φ3 to the upper layer gate electrodes C, C3 shown in FIG. 6(a), respectively, and the voltages shown in FIG. 6(b) are applied to the corresponding portions. Potential wells W, , W3 as shown in FIG. ,, Charges accumulated in W3 that reach and exceed the overflow level shown by the broken line are absorbed and removed by the overflow drain, and blooming is suppressed.

At the end of the photoelectric conversion period, the clock pulse voltage φ2 for the gate electrode G2 in the lower layer is set to a high level, and a potential well W2 of approximately twice the depth is placed at a position opposite to this as shown in FIG. 6(c). is formed, and charges in the potential wells Wi, W3 formed under the gate electrode G I + 03 are collected here, so that the so-called two pixels are mixed and transferred to the storage section (not shown). It has become.

[Problem that the invention seeks to solve]

By the way, the relationship between the output and light illuminance in a CCD solid-state image sensor of the type that mixes two pixels as described above is shown in the seventh figure.
The result will be as shown in the figure. Figure 7 shows the light illuminance on the horizontal axis and the output on the vertical axis, and the relationship between the light illuminance and the output at a single pixel is as shown by lines Pa P and p2, and the light illuminance increases from Po to P5. The output increases as the light illuminance increases, but when the light illuminance exceeds 25, the overflow level is reached and the charge exceeding this level is absorbed and removed by the overflow drain, resulting in a so-called saturated state in which the output does not increase. Next, if we look at the case where two pixels are mixed, the line PoP
It becomes like 3P4, and the output is doubled, but the saturation light illuminance is still P5, and for light illuminance exceeding P5, the output does not increase, in other words, the dynamic range is narrow and the contrast is low. This means that it cannot be expressed.

For this reason, conventionally, in order to expand the dynamic range, an interline type CCD solid-state image sensor uses the readout voltage from the light receiving section, and a frame transfer type CCD solid-state image sensor uses surface channel accumulation. A method using the method has already been proposed (Proceedings of the 1984 National Conference of the Television Society 3-14゜j Proceedings of the 1978 National Conference of the Television Society 2-1.2).

By the way, as mentioned above, in the former case, the conventional method has a structure in which the opening and closing of the gate from the light receiving section to the vertical transfer channel can be freely controlled, that is, it is effective only for the interline method, and it is effective only for the accumulation of video signal charge and the vertical transfer channel. There is a problem that it cannot be applied to a frame transfer method that uses the same gate to perform both gate and gate i-.Furthermore, although the latter method uses surface channels, the transfer efficiency is low, and the use of embedded channels has become widespread. Currently, the scope of its application is narrow.

[Means for solving problems]

The present invention has been made in view of the above circumstances, and its purpose is to increase the charge accumulation time so that the charge of at least one of the two pixels to be mixed does not reach an overflow state when two pixels are mixed and output. It is an object of the present invention to provide a solid-state imaging device which can significantly expand the dynamic range and improve image quality by changing the structure, and can be applied not only to interline type but also to frame transfer type CCD solid-state image sensing devices.

A solid-state image sensor according to the present invention is a solid-state image sensor that mixes charges of two adjacent pixels and outputs the mixture. It is characterized by having different charge accumulation times.

〔principle〕

FIG. 1 is a graph showing the relationship between light illuminance and output of a CCD solid-state image pickup device configured to output a mixture of two pixels. The horizontal axis represents the light illuminance, and the vertical axis represents the output. The broken line shows the relationship in the conventional case shown in FIG. 7, and when the charges generated in two pixels to be mixed are accumulated for the same amount of time, the light illuminance and output in one pixel, as described above, are The relationship is P. P and P2, and when these are mixed, it becomes PoP3P4 and the saturated light illuminance becomes P5.

Therefore, the charge accumulation times of the two pixels to be mixed are made different so that at least one of them does not become saturated. For example, in one of the two pixels to be mixed, charge is accumulated in a pop, p2 pattern as shown by the dashed line, as in the conventional case, and in the other pixel, the charge accumulation time is shortened. Charges are accumulated in a pattern of <POp7p2 as shown by the two-dot chain line. As a result, when two pixels are mixed, it becomes as shown by the solid line, and the light illuminance reaches a saturated state for the first time at P9. Therefore, the saturated light illuminance, that is, the dynamic range, can be greatly expanded compared to the conventional case where the saturated state is reached at P5.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 2 is a schematic plan view of an imaging section in a frame transfer CCD fixed imaging device having a cross-gate structure, and numeral 10 in the figure indicates a SiM substrate. On this substrate 10, channel stoppers 11, 11, . In the center there is an overflow drain 12. along its length. ．． 12... are formed.

On the substrate 10 on which the channel stoppers 11, overflow drains 12, and so on are formed, lower gate electrodes 13 and 13, which extend in the lateral direction (horizontal direction) across an insulating film (not shown), are vertically disposed. Upper layer gate electrodes 14, 14, . . . are formed at regular intervals in the direction, and extend vertically at positions corresponding to the channel stopper 11 and the overflow drain 12, with an insulating film (not shown) therebetween. are formed at regular intervals in the lateral direction, and light receiving portions 15 are formed in the lattice portions formed by the upper and lower gate electrodes 13 and 14. This upper layer gate electrode 14. ．． 14... has a narrow part 1 in its longitudinal direction.
4a and wide width portions 14b are formed alternately at a predetermined pitch, and the narrow width portions 14a and wide width portions 14b are alternated between adjacent upper layer gate electrodes 14 and 14,
Each wide portion 14b is formed so as to span both adjacent lower layer electrodes 13, 13, and serves as an accumulation portion for charges generated in the light receiving portion 15.

Now, the lower layer gate electrode 13..., the upper layer gate electrode 14...
... are electrically connected to each other, and the set of electrodes connected in this way is connected to the lower gate electrode 13.
..., the first gate electrode G1, the third gate electrode G
3, and the upper layer gate electrode] 4...
A gate electrode G2, a fourth gate electrode G, and each of the first to fourth gate electrodes 61 to G.

The clock pulse voltage applied to φ1. φ2. φ3゜φ
Set it to 4. The clock pulse voltage and the timing of application are controlled by a drive circuit (not shown), so that the charge in each pixel is accumulated as shown by the dashed line in FIG. 2, and is further transferred.

Figures 3 (a), (b), (c), and (d) show clock pulse waveform diagrams during charge accumulation, and Figure 4 (a)
Figures 4 (b), (c), (d) are schematic diagrams of gate electrodes.
(1), (IT) when controlled by clock pulses with waveforms as shown in FIGS. 3 (a) to (d) above.
, (Iff) at each position.

At the beginning of the charge accumulation period, as shown in FIG. 3(a), the clock pulse voltage φ1 is at a high level, and the other clock pulse voltages φ2 . φ3. φ4 is set to low level. As a result, a deep potential well W1 is formed at a position facing the first gate electrode G1, as shown in FIG.
．． The potential at the position facing the fourth gate electrode G 2 + 04 is low, and the potential at the position facing the third gate electrode G3 is set and maintained even lower. As a result, there is a te area in Fig. 4 (b) which is wider than the conventional one shown in Fig. 6 (b).
Charges are accumulated from the range indicated by l and are accumulated in the potential well W1. At this time, when the intensity of the incident light is high, the charge level within the potential well has reached an overflow level (a position indicated by C1), and blooming is suppressed.

This state is called t. After maintaining the voltage for a period from to tl, the clock pulse voltage φ3 of the third gate electrode G3 is then set to a high level. As a result, as shown in Figure 4 (c),
A potential well W3 similar to that at the position facing the first gate electrode G1 is formed at a position facing the third gate electrode G3, and charges begin to be accumulated here as well with a delay. However, since the charge accumulated in this potential well W3 has a short accumulation time, it has not yet reached the overflow level (C1).

After maintaining the above state from tl to t2, the clock pulse voltage φ2 of the second gate electrode G2 is set to high level. As a result, as shown in FIG. 4(d), a potential well W2 deeper than both potential wells described above is formed at a position facing the second gate electrode G2, and all the accumulated charges are mixed in this potential well W2. In the potential diagram shown in FIG. 4(c), one pixel to be mixed is The charges accumulated in the potential well Wl formed at the position facing the first gate electrode G1 in the pixel are in an overflow state, and the relationship between the light illuminance and the output for this pixel is shown in FIG.
p, in the state of P2.

On the other hand, the charges accumulated in the potential well W3 formed at a position facing the third gate electrode G3 have not yet reached the overflow level, and the relationship between the light illuminance and the output for this pixel is shown in FIG. It is in the pop, p2 state.

Therefore, the relationship between the light illuminance and the output at the potential W2, which stores the charges collected from the potential well, which is the re-output charge amount, is as shown in P, P6P8P4 in Fig. 1, and the saturated light illuminance increases from Ps to Ps. It is clear that Namino Cleanse will be greatly expanded.

Although it is desirable to set the charge accumulation time in the potential well W3 so that the charge level here does not reach at least the overflow level, it is not necessary to set the charge level of all potential wells W3 below the overflow level. It's okay.

The charge accumulation time in the potential well W3 can be changed by adjusting the period from time t1 to t2 shown in FIG. It is a diagram.

Figure 5 shows the light illuminance on the horizontal axis and the output on the vertical axis.If the period from t to t2 is made small, the graph changes as indicated by a, b, and c, and in the low light illuminance region, the slope In other words, the light sensitivity at low illuminance is large, and the slope is gentle in the high illuminance region, in other words, the saturated light illuminance is large, and the contrast I can be clearly expressed.

Note that the above two explanations have been made regarding CCD solid-state imaging devices that have a cross-gate structure and use a frame transfer method, but are not limited to this.
Of course, the present invention can also be applied to a 1'l solid-state image sensor.

〔effect〕

As described above, in the device of the present invention, since the time for accumulating charges of adjacent pixels is different, it is possible to increase the saturated light illuminance and expand the Guinamin range, which allows for high illumination. The present invention has excellent effects, such as obtaining sufficient contrast for the subject, and being able to adjust the charge accumulation time simply by changing the length of the clock, simplifying control and stabilizing the operation. It is something.

[Brief explanation of drawings]

Fig. 1 is a photoelectric conversion characteristic diagram of the device of the present invention, Fig. 2 is a schematic plan view showing the imaging section of the device of the invention, Fig. 3 is a clock waveform diagram of the imaging section of the device of the invention, and Fig. 4 is the same. FIG. 5 is a potential diagram showing the manner of charge accumulation, FIG. 5 is a photoelectric conversion characteristic diagram of the device of the present invention, FIG. 6 is a photoelectric conversion characteristic diagram of the conventional device, and FIG. 7 is a clock waveform diagram of the conventional device. 10... Substrate 11... Channel stopper 12.
...Overflow drain 13...Lower layer gate electrode 14...Upper] 2 layer gate electrode GI, G2, G3, G4
...Gate electrode φ1. φ2. φ3. φ4... Clock pulse voltage patent Applicant Sanyo Electric Co., Ltd. Agent Patent Attorney Noboru Kono
month 9th country

Claims (1)

[Claims] 1. In a solid-state image sensor that mixes and outputs the charges of two adjacent pixels, the accumulation time of each charge is different so that the amount of charge of at least one of the two pixels whose charges are to be mixed does not reach an overflow level. A solid-state image sensor characterized by a solid state.