JPS5952873A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To increase the maximun quantity of signal charge of a vertical shift register as well as to expand the dynamic range of the titled device by a method wherein the transfer of charge is controlled by the extended part of one of the two layer shift register transistors and a photo diode and the shift register of the extended part of the other electrode are separated by forming a channel stop on the substrate region located directly below said extended part. CONSTITUTION:A channel stop region 14, which is located between the n type layer 3 of a photo diode and the n type layer 2 of a vertical shift register, is widely formed, and a transfer gate region 15 is provided in such a shape that it is formed in the region located directly below electrodes 7 and 9. Clock pulses phi'1, phi2, phi'3 and phi4 are applied to electrodes, 7, 8, 9 and 10. The clock pulses phi'1 and phi'3 are binary pulses of VL and VH. When the clock pulse phi2 or phi4 is VH, the signal charge accumulated on a photo diode 3 passes the transfer gate region 15 and transfered to a vertical shift register 2. On the other hand, when phi2 and phi4 are VL or VI, the signal charge in the shift register is transferred from the lower part to the upper part.

Description

[Detailed Description of the Invention] Technical Field> The present invention is based on a CCD (Charge Coupled Detailed Description).
0 <Prior art> In recent years, the development of solid-state imaging devices has made remarkable progress. Color video cameras using solid-state imaging devices are approaching the stage of practical use. There are two main types of solid-state imaging devices: the XY address method and the CCD method.
Since the D method essentially has a small output capacity, research is being focused on it because it is advantageous in terms of $4. Among the CCD systems, the interline transfer system, which uses a pn junction photodiode in the light receiving section, is becoming the mainstream for solid-state imaging devices because it has high blue sensitivity and can use mosaic color filters to provide high resolution.

However, in the interline transfer method, since the light receiving section and the transfer section coexist, the areas of these sections are restricted, and the drawback is that the maximum signal charge amount is small and the dynamic range is therefore narrow.

First, Fig. 1 shows a conventional example of an interline transfer type CCD solid-state imaging device using a pn junction photodiode in the light receiving part. Here, (a) is a plan view, and (bXc) and (d) are respectively ■-■1n -n<m- is a cross-sectional view in the direction. That is, an n-type layer 2 is formed on a p-substrate 1 as a buried channel for a vertical shift register, and an n-type layer 3 is formed at a predetermined distance from the n-type layer 2 to form a pn junction that becomes a photodiode. has been done. A two-dimensional imaging device is constructed by forming a plurality of columns of vertical shift registers on the same semiconductor chip, and forming a plurality of photodiodes for one vertical shift register.

The n-type layer 2 and the n-type layer 3 are connected by a transfer gate region 5 which remains in the substrate. n-type layer 2, n-type layer 3.
In a portion other than the transfer gate region 5, a channel stop 4 made of a highly doped p-type layer is formed. On the other hand, the silicon substrate is covered with an insulating layer, and electrodes 7, 8, 9, and 10 for vertical shift registers are formed on top of the insulating layer using polysilicon. Electrodes 7 and 9 are formed as a first layer of polysilicon, electrodes 8 and IO are formed as a second layer of polysilicon, and an insulating film 11 is formed between the polysilicon layers of different layers.
separated by. The electrodes 7.8.9.10 cover the top of the vertical shift register n-type layer 2 and also cover the top of the transfer gate region 5.

The upper portions of the vertical shift register n-type layer 2 and the transfer region 5 are covered with At 12 for light shielding.

The clock pulse φ1. shown in FIG. 2 is applied to the electrode +0.7.8.9. φ2. φ3. φ4 is applied respectively. These clock pulses φ1 to φ4 are signals with three levels, VL"I"H, and when the clock pulses are VL, the signal charge in the vertical shift register is transferred from the bottom to the top in Figure 1 (a). be done. On the other hand, in case (11), the signal charge accumulated in the photodiode 3 is transferred to the vertical shift register 2 through the transfer gate region 5.

In this method, although the amplitude of the clock pulse is from ■1 to ■H, the maximum signal charge of the vertical shift register is the level difference between VL and vl, and the maximum signal charge of the photodiode is between ■1 and ■1. (It is determined by the level difference between

<Object of the Invention> The present invention has been made to solve the problems of the conventional solid-state imaging device described above, and provides a solid-state imaging device in which the maximum signal charge amount of the vertical shift register is increased and the dynamic range is expanded. It is something.

<Example> The details of the present invention will be explained below using examples.

FIG. 3 is a configuration diagram of a solid-state imaging device showing an embodiment to which the present invention is applied. Here (a) is a plan view, (b) (c)
(d) are II-I', II-II', lll, respectively
It is a sectional view taken in the -111'j5 direction. Figure 3 and above-mentioned 1st
The difference between the figures is that in the conventional substrate structure, the n-type layer 3 of the photodiode has approximately the same dimensions and is continuous with the transfer gate region 5, as is clear from the comparison between FIG. 1(d) and FIG. 3(d). It reaches the n-type layer 2 of the vertical shift register, but in the embodiment shown in 3rd p(d), the n-type layer 2 of the photodiode
The region of the channel stop 14 located between the type layer 3 and the n-type layer 2 of the vertical shift register and in contact with the transfer gate region 15 is expanded and formed, and the transfer gate region 15 is formed directly under the electrode 7 and the electrode 9. It has a limited shape.

For example, the clock pulses -1, φ2, . . . shown in FIG. φ4 is applied. The difference between Fig. 4 and the above-mentioned Fig. 2 is that the clock pulses φ1 and φ6 are binary pulses of VL and VI (V/ is a voltage larger than ■, and is the same voltage as ■□. However, the voltage may be different.

That is, when the clock pulse φ2 or φ4 is V1□, the signal charge accumulated in the photodiode 3 is transferred to the vertical shift register 2 through the transfer gate region 15. On the other hand, when φ2 and φ4 are VL or Vl, the signal charges in the vertical shift lens are transferred from the bottom to the top in FIG. 3(a). At this time, the clock pulses φ; and φ6 have amplitudes between ■1 and V1'1, but the channel top 14 is located between the photodiode directly below the electrode 8 and lO to which these clock pulses are applied, and the vertical shift register. Since it exists, it does not affect the signal charge accumulated in the photodiode. Also, while the signal charge is being transferred in the vertical shift register, the amplitude of φ1 and the bow are ■, and V/
Since this is large, the maximum signal charge amount of the vertical shift register increases.

Effects> As described above, by applying the present invention, it is possible to increase the maximum signal charge amount of the transfer section and widen the dynamic range.

[Brief explanation of drawings]

Figure 1 is a structural diagram of a conventional interline transfer type solid-state imaging device, Figure 2 is a timing diagram of its clock pulses,
FIG. 3 is a structural diagram of an interline transfer type solid-state imaging device to which the present invention is applied, and FIG. 4 is a timing chart of tarock pulses thereof. l...p substrate, 2...n type layer, 3...n type layer, 14...
...Channel top, 15...Transfer gate region. 6... Insulating film, 7.8.9.10... Polysilicon electrode. 11. Insulating film, 12.. At for light shielding (G) -S-7 Fig. 1 359- (C) (

Claims (1)

[Claims] l) Pn junction photodiodes are arranged at a predetermined pitch on the same semiconductor substrate, and a CCD is placed close to the photodiodes.
In a solid-state imaging device equipped with a shift register based on a charge-coupled device (charge-coupled device), two layers of shift register electrodes are provided that are partially overlapped in order to transfer signal charges of the shift register, and one shift register electrode The extended part of the shift register electrode is located on the transfer gate region between the photodiode and the shift register to control charge transfer, and the extended part of the other shift register electrode is located on the transfer gate region between the photodiode and the shift register with a channel stop formed in the substrate region directly below. The registers are separated, and one of the shift register electrodes has low, medium,
A high ternary pulse is applied to the other shift register electrode, and a low,
A solid-state imaging device characterized by applying a high binary pulse.