JPS6079773A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To inhibit dark currents and blooming by storing charges having conductivity reverse to signal charges in a light-receiving region in a CCD solid- state image pickup device using an MOS diode as a light-receiving section. CONSTITUTION:An n type layer 2 constituting a buried channel for a vertical shift register and an n type layer 13 constituting a light-receiving section are connected by a region 4 left as it is a p layer, and channel stops 7 are formed to sections except the layer 2 and the layer 13. An electrode 9 for the vertical shift register is shaped to the upper section of the n type layer 2, and a photo- gate electrode 10 is formed to the upper section of the light-receiving section 13 through an insulating film 8. Reverse bias is applied among the channel stops by the p type layer and an n substrate 14. Negative voltage is applied to the electrode 10, and charges having conductivity reverse to signal charges are stored on the interface between the layer 13 and the insulating film 8. An interface level is buried by the storage of charges, and the generation of dark currents is inhibited. Signal charges are stored while the potential of the layer 13 is shallowed, excessive signal charges flow out to the n substrate side, and blooming is inhibited.

Description

[Detailed Description of the Invention] Technical Field> The present invention relates to a CCD (Charge-Coupled Duel).
The present invention relates to a solid-state imaging device using a charge transfer device (ice: charge transfer device), and particularly to a solid-state imaging device using a MOS diode as a light receiving section, such as an interline transfer type CCD.

<Prior art> In recent years, the development of solid-state imaging devices has made remarkable progress.
Color video cameras using solid-state imaging devices are approaching the stage of practical use. There are two main types of solid-state imaging devices: the XY address method and the CCD method. In particular, the CCD method inherently has a low output capacity. Due to its small size, it has an advantage in terms of signal-to-noise ratio, so much effort is being put into research. Among the CCD systems, the interline transfer system is becoming mainstream in solid-state imaging devices because it is advantageous in terms of cost because it allows for a small chip size, and it is relatively easy to improve blue sensitivity.

There are two methods for forming the light receiving section of the in-line transfer method: one using a MOS diode and one using a p-1 junction diode.The former is characterized by no afterimage. The present invention relates to the former, and first, a conventional CCD solid-state imaging device using a MOS diode as a light receiving section will be explained.

FIG. 1 is a cross-sectional view of a unit pixel. That is, an n-type layer 2 is formed on a p-substrate 1 as a buried channel for a vertical shift register. A vertical shift register electrode 9 is provided over the n-type layer 2 and the edge region 4 of the substrate adjacent to the n-type layer 2 with an insulating film 8 interposed therebetween. Board 1
A region 3, which is also a substrate, is provided adjacent to the main region 4, and this portion operates as a light receiving section. A p-region 5 having a higher impurity concentration than the substrate is provided adjacent to the substrate's regular region 3 as a potential barrier, and an n-region 6 forming an overflow drain is provided adjacent to the p-region 5. Board size area 3. p region5. A photogate electrode 10 is provided above the n'- region 6 with an insulating film 8 interposed therebetween. 1] Region 2°, board bend region 3, 4. p region 5, 1] Except for region 6, p+ region 7 is formed, and 1' flt is performed for each pixel. Further, an aluminum layer 11 is provided on the upper part except for the light receiving part for light shielding. A binary clock pulse is applied to the vertical shift register electrode 9 and the photogate electrode 10, respectively.C) A low level is applied to the photogate electrode 10 and a high level is applied to the vertical shift register electrode 9. Then, the signal charges accumulated in region 3, which is the same as the substrate, are transferred to region 4, which is the same as the substrate.
is transferred to the n-type layer 2 forming the vertical shift register. (Photograph) When a high level is applied to the fft pole 10, the intact region 3 of the substrate forming the light receiving part and the n-type layer 2 forming the vertical shift register are separated by the folded region 4 of the substrate, and the photovoltaic Signal charges generated by conversion are accumulated in region 3, which remains in the substrate. Excess charges generated due to the incidence of strong light are absorbed by the overflow drain 6 through the potential barrier formed by the ultrap region 5, and so-called blooming is suppressed. On the other hand, signal charges in the vertical shift register are sequentially transferred by a vertical shift register clock. The above is the operating principle of a conventional CCD image pickup device using a MOS diode as a light receiving section.

However, the conventional structure described above has two major problems as shown below. First, in order to suppress blooming, it is necessary to arrange the p region 5 and the overflow drain 6 in a planar manner for forming the entire potential barrier, which reduces the effective area of the pixel. The second is dark current.

That is, a surface single image exists at the interface between the silicon substrate and the insulating film, and this causes dark current to occur. Photogate electrode 1
Polysilicon is usually used for 0, but since polysilicon is semitransparent, its short wavelength sensitivity is particularly low. In order to prevent this, it is necessary to use a transparent electrode such as indium oxide or tin oxide as the photogate electrode.
If these charges are used, the surface level will normally increase and the dark current will further increase.

<Object of the invention> The present invention has been made in view of the above two points, and has an effective aspect of 7 (-1
To provide a solid-state imaging device which enables a CCD imaging device having a blooming suppression function and having a MOS diode with a small dark current.

<Embodiment> FIG. 2 is a block diagram of a solid-state imaging device showing an embodiment to which the present invention is applied. Here, (a) is a plan view of a unit pixel, and (b) and (C) are a plan view of a unit pixel. l-1', ll-11 respectively
FIG.

That is, one layer 12 is formed on the second substrate 14, and an n-type layer 2 is further formed as a buried channel for a vertical shift register, and a layer 12 is formed at a predetermined distance from the n-type layer 2 to form a light receiving section. An n-type layer 13 is formed. The n
In this embodiment, the type layer 13 is formed to have an 11-type conductivity because the signal charge caused by imaging is an electron. A two-dimensional imaging device is constructed by forming a plurality of columns of vertical shift registers on the same semiconductor chip, and forming a plurality of n-type layers 13 for one vertical shift register. The n-type layer 2 and the n-type layer 13 are connected by a region 4 which remains a p-layer. A channel stop 7 made of a highly doped p-type layer is formed in a portion other than the n-type layer 2, the n-type layer 13, and the region 4 which remains the p-layer. On the other hand, the silicon substrate is covered with an insulating film 8, on which vertical shift register electrodes 9°15, 16, and 17 are formed of polysilicon. Electrodes 9 and 16 are formed as a first layer of polysilicon, electrodes 15 and 17 are formed as a second layer of polysilicon, and the polysilicon layers of different layers are separated by an insulating film. The electrodes 9, 15, 16 and 17 cover the upper part 'f' of the n-type layer 2 for the vertical shift register, and also cover the upper part of the region 4 which remains the p layer. n-type layer 13 forming a light receiving section
A photogate electrode 1o is provided on top of the insulating film 8 with an insulating film 8 interposed therebetween. The photogate electrode 10 may cover the upper portions of the vertical shift register electrodes 9, 15, 16, and 17 with an insulating film interposed therebetween. The photogate electrode 10 may be formed using polysilicon, but since polysilicon is semitransparent, it is desirable to use a transparent material such as tin oxide or indium oxide from the viewpoint of short wavelength sensitivity. The top portion of the silicon substrate, except for the light receiving portion, is covered with AtII for light shielding. A bias voltage in the opposite direction is applied between the channel stop 7 formed by the p-type layer and the n-substrate 14. A negative voltage is applied to the photogate electrode 10 with respect to the channel stop 7 formed by the p-type layer so that holes, that is, charges having conductivity opposite to the signal charge, accumulate at the interface between the n-type layer 13 and the insulating film 8. is applied.

At this time, the n-type layer 13, p-type/i'J12, n-type/i'J12,
The potential of 4 is as shown in Figure 3. In other words, holes accumulate on the surface of the n-type layer 13 and the channel stop 7
Since the potential is the same as that of , the potential is Ov.

In addition, the accumulation of holes fills the interface level, thereby suppressing the generation of dark current. As signal charges accumulate, the potential of the n-type layer 13 gradually becomes shallower, and excess signal charges flow toward the substrate 11, thereby suppressing blooming caused by the incidence of strong light. The clock pulse φ1. shown in FIG. 4 is applied to the electrodes 17°9.15.16.
φ2. φ3. φ4 is applied respectively. These clock pulses φl to φ4 are signals having three levels: u, VL, VI, and VH. When the clock pulses are VL or VI, the signal charge in the vertical shift register 2 is transferred from the bottom to the top in FIG. 2(a). be done. At this time, since the n-type layer 13 and the n-type layer 2 are separated by the region 4, signal charges generated by photoelectric conversion are accumulated in the n-type layer 13. When the clock pulse is VH, the signal charges accumulated in the n-type layer 13 are transferred through the region 4 to the n-type layer 2 forming the vertical shift register.

FIG. 5 is a configuration diagram of a solid-state imaging device showing another embodiment to which the present invention is applied. Here, (a) is a plan view, (b) (
c) is a sectional view in the I-1 and nn directions, respectively.

The difference between FIG. 5 and FIG. 2 is that, as is clear from FIG. 5(c), there is no channel stop between the n-type layers 13 forming the light receiving section;
b) VC is provided only between the n-type layer 13 and the vertical shift register n-type layer 2 as shown. This structure was specially applied for in 1982.
It is similar to -126552, and corresponds to the one in which the light receiving part is replaced with a MOS diode instead of a pn junction diode. In this structure, the electrodes 17, 9, 15, 16 have the sixth
φ1 shown in the figure. φ2′, φ3. φ4' or φ1 shown in FIG. φf.

φ3. φ? It is sufficient to apply the spider's rays, the clouds, and the clouds.This can be partially omitted, and variations in characteristics due to misalignment of the mask can be significantly reduced, and at the same time, the same effect as shown in FIG. 2 can be obtained.

<Effects> By applying the present invention as described above, it is possible to realize a solid-state imaging device that has a small dark current and a blooming suppression function while having a large effective surface area. each op
It is clear that there is an effect of reducing dark current even when it is formed on a substrate.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a solid-state imaging device using a conventional MOS diode as a light receiving section, and FIG. 2 is a diagram showing the configuration of a solid-state imaging device according to an embodiment of the present invention. b
)(c) is a sectional view, FIG. 3 is a potential diagram of the light receiving section to explain the operation of the same embodiment, FIG. 4 is a timing diagram of clock pulses to explain the operation of the same embodiment, and FIG. 5 is a diagram of the present invention. FIG. 6 is a diagram showing the configuration of a solid-state imaging device according to another embodiment, in which (a) is a plan view, (b) and (c) are cross-sectional views;
7 and 7 are 24477 diagrams of clock pulses used to explain the operation of the same embodiment. 2; N-type layer for vertical shift register, 4; Transfer gate section, 7; Channel stop, 8; Insulating film, 9, 15
, 16, 17; Vertical shift register electrode,', 10
; Photogate electrode, 11; At. "1 12; 1 layer, 13; Light receiving part (n-type layer), 14; n-substrate

Claims (1)

[Claims] 1) In a solid-state imaging device comprising a MOS diode as a light receiving part and a vertical shift register for transferring signal charges generated in the light receiving part, a semiconductor substrate is provided with a light receiving part in contact with the semiconductor surface. The feature is that a layer with the same conductivity as the signal charge is formed, and a bias voltage is applied to the electrode of the MOS diode so that the charge with the opposite conductivity to the signal charge accumulates at the interface between the insulating film and the semiconductor. A solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein a ternary clock pulse is applied to a vertical shift register electrode that controls the operation of the vertical shift register. 3) In the solid-state imaging device according to claim 1, the layer provided in contact with the semiconductor surface and having the same conductivity as the signal charges is formed on the substrate having the same conductivity as the signal charges. A solid-state imaging device characterized in that it is formed on a layer having conductivity opposite to that of signal charges. 4) In the solid-state imaging device according to claim 1 or 2, the layers having the same conductive layer as the signal charge formed in contact with the semiconductor surface are separated from each other by a vertical shift register electrode. A solid-state imaging device characterized by: