JPS6314468A - Change transfer type solid-state imaging device - Google Patents

Abstract

PURPOSE:To reduce the area occupied by an overflow transistor and to contrive increasing the signal storage capacity and the sensitivity of a photodiode by providing the overflow MOS transistor in the element separation region between an optoelectric transducer and an adjacent charge transfer device and by forming the gate with part of a conductive wiring. CONSTITUTION:A plurality of optoelectric transducers 1, charge transfer devices 7, 2 and 3 for reading the optical signal charge stored in the optoelectric transducers, and an overflow MOS transistor 8 for discarding the excessive optical signal charge are integrated on the same semiconductor substrate. In such a charge transfer type solid-state imaging device, the element separation region between the charge transfer device 2 and the adjacent optoelectric transducer 1 is allocated to the overflow MOS transistor B and a conductive wiring 10' runs across the element separation region. At least the gate electrode 8'of the overflow MOS transistor 8 is made of part of the above-mentioned conductive wiring 10'. This enables effectively providing the overflow MOS transistor without the reduction of an aperture rate and restraining blooming perfectly.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides a photoelectric conversion element on a semiconductor substrate and a charge transfer element ((::harge) for extracting optical information of each element.
(::upled 1)evHces) This relates to a t-integrated solid-state imaging device.

[Conventional technology]

A solid-state imaging device requires an imaging plate with the resolving power of the imaging electron tube used in current television broadcasting.
000 picture elements (photoelectric conversion elements) (ma) IJ Lux A scanning element corresponding to the IJ Lux is required. Therefore, the solid-state imaging device described above is manufactured using MO8 large-scale circuit technology that requires high integration, and generally uses COD as a component.
(CCD type image sensor) or MOS transistor C
MO8 type image sensor) etc. are used.

FIG. 9(a) shows the configuration of a CCD type image sensor characterized by low noise (for example, Horii et al. "Pluming improved type 2
/3-inch single-plate color CCD image pickup device", Television Society Technical Report, ED525° May 1980.) 1 is a photoelectric conversion element consisting of, for example, a photodiode, 2 and 3 are a group of photoelectric conversion elements. Vertical CCD shift V for taking out the accumulated optical signal to the output end 4
register and horizontal shift register. 5-1.5
-2°6-1 and 6-2 are terminals into which clock pulses for driving the vertical shift register and horizontal shift register are input, respectively. Although the case where two-phase clock pulses are input is illustrated here, either four-phase or three-phase clock format may be adopted. Further, numeral 7 indicates a transfer MOS transistor that sends the charges accumulated in the photodiode 1 to the vertical shift register 2. Here, the transfer MOS
Although we have shown a configuration in which the electrode 2-1 of the vertical COD shift register also serves as the gate of the transistor, a configuration in which an independent electrode is used for this gate (a configuration in which the COD electrode and the transfer gate electrode are separated and made independent) is shown. I don't mind. Further, 8 is an overflow MOS transistor that sweeps out excess charge generated when intense light is incident to the drain 10, and 9 is an overflow control gate that controls the sweeping potential of the overflow MOS transistor 8. 1
Reference numeral 2 indicates the charge transfer direction, and reference numeral 13 indicates the wiring area of the vertical CCD electrode. In its current form, this element becomes a monochrome image sensor, and when a color filter is laminated on top, each party diode is provided with color information, resulting in a 9-color image sensor.

Solid-state imaging devices have many advantages over electron tubes, such as being small, lightweight, maintenance-free, and low power consumption, and are expected to have a promising future as imaging devices. However, current CCD type image sensors have a problem of low light sensitivity for reasons explained below.

FIG. 9(b) is a diagram showing a planar configuration of a pixel (indicated by a dotted line 11 in FIG. 9(a)) which is a constituent unit of the image sensor shown in FIG. 9(a). 2-1 is an electrode (for example, the first
2-2 is a vertical CC
Another electrode constituting D2 (for example, formed from a second layer of polycrystalline silicon), 2-3 is a channel region of the vertical CCD 2 (channel means a path for electricity), 7
' indicates the gate region of the transfer MO8 transistor 7. 8' is the gate region of the overflow MoS transistor 8, 9' is the wiring for the control gate 9, and 10' is the wiring for the drain 10. When the incident light is intense, excess charge is generated that cannot be accumulated in photodiode 1.
This excess is swept out to the drain wiring lO' via the gate region 8'.

This sweeping can prevent the occurrence of pluming and significantly improve the image quality (pluming is a phenomenon in which excess charge overflows to the adjacent vertical C0D2 and generates white stripes in the vertical direction on the monitor).

[Problem that the invention seeks to solve]

However, the gate region 8', the control gate wiring 9',
Since the area consumed by the drain wiring 10' occupies a considerable portion of the pixel, the area of the photodiode and the additional area of light (generally referred to as the aperture ratio) are significantly reduced. The former reduction in diode area causes the problem of lowering the signal charge storage capacity and narrowing the dynamic range. This area becomes considerably small because in addition to the area of the regions 8', 9', and 10', an area for insulating and separating the regions s;, 9', and 10' is also required. On the other hand, the aperture ratio of the latter is 8'
, 9', and 10', only about 20% can be obtained (
In other words, only 115 of the incident light can be used for a signal), which leads to a decrease in photosensitivity and is a major problem for CCD type devices.

Furthermore, when trying to reduce the pixel size in order to achieve higher resolution in the future, these BZg/.

The area ratio of the 10' region will increase from the present, and the dynamic range and photosensitivity will decrease more and more. on the other hand,
In the MO8 type image sensor, which is another element similar to the CCD type element of a solid-state image sensor, an overflow MOS transistor similar to that described above is added to the photodiode to suppress pluming. Unlike a CCD type element, in the MO8 type element, signal transfer is performed using metal wiring, etc., so unlike a COD shift register, the surface fRt is not consumed, and even if an overflow drain is provided as shown in Figure 1, the area or aperture of the photodiode will be reduced. The reduction in rate is not as great as in the case of CCD type elements. Therefore, for CCD type devices, it will be an important task in the future to improve the overflow MOS transistor structure and reduce the area occupied by the transistor and wiring as much as possible.

Zeng An object of the present invention is to reduce the area occupied by an overflow transistor in a CCD type element and to increase the signal storage capacity and sensitivity of a photodiode.

[Means for solving problems]

The above purpose is to provide an overflow MOS transistor in an element isolation region between a photoelectric conversion element and an adjacent vertical charge transfer element, and to form the gate of the transistor with a part of a conductive wiring having an element isolation function. This is achieved by

[Effect]

Since the conductive wiring has an element isolation function and the gate electrode of the overflow MOS transistor can be controlled, a decrease in the aperture ratio and blooming can be suppressed. Furthermore, since the drain of the transistor is also provided in the isolation region,
There is no decrease in aperture ratio.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1 is a photoelectric conversion element consisting of, for example, a photodiode; 2 and 3;
are a vertical COD shift register and a horizontal shift register for taking out the optical signals accumulated in the photoelectric conversion element group to the output terminal 4.

5-1. 5-2. 6-1 and 6-2 are terminals for inputting clock pulses for driving the vertical shift register and the horizontal shift register, respectively. Although the case where two-phase clock pulses are input is illustrated here, either four-phase or three-phase clock format may be adopted. In addition, 7 transfers the charge accumulated in the photodiode 1 to the vertical shift register 2.
A transfer MOS transistor is shown. Here, we have shown a configuration in which the gate of the transfer MOS transistor is also used by the constituent electrode 2-1 of the vertical CCD shift t/transistor, but a configuration in which an independent electrode is used for this gate (the COD electrode and the transfer gate electrode are separated and made independent) is shown. configuration). Reference numeral 8 denotes an overflow MOS transistor which discharges excess charge generated when intense light is incident to the common drain wiring 10 via the drain 9. An overflow control gate 8 controls the discharge potential of the overflow MOS transistor 8. is connected to. 12 is the charge transfer direction, 13 is the vertical CCD
The wiring area of the electrode is shown. In its original form, this device becomes a monochrome image sensor, and when a color filter is laminated on top, each photodiode loses color information and becomes a color image sensor.

FIG. 1(Φ) is a diagram showing a planar configuration of a pixel (indicated by a dotted line 11 in FIG. 1(a)) which is a constituent unit of the image sensor shown in FIG. 1(a). 2-1 is an electrode that constitutes a vertical CCDk that also serves as a transfer MOS transistor (for example, formed from the second layer of polycrystalline silicon), 2-2 is a vertical CCD2i
2-3 is the channel region of the vertical CCD 2 (channel means one path); 7' is the channel region of the transfer MOS transistor 7; The gate area is shown. 8
' is the gate region of the overflow MOS transistor 8, 9' is the drain region of 8, and 10' is the common drain 9.
wiring (for example, formed from the first layer of polycrystalline silicon). 14 is a through hole connecting the drain 9 and the wiring 10'. When the incident light is intense, an excess charge that cannot be accumulated in the photodiode 1 is generated, but this excess charge is swept out to the drain wiring 10' via the gate region S/ and the through hole ILj-. . This sweeping can prevent the occurrence of pluming and significantly improve the image quality (blooming is a phenomenon in which excess charge overflows to the adjacent vertical C0D2 and causes white stripes in the vertical direction on the monitor).

As can be seen from the layout diagram shown above, a wiring 10' is provided in the separation area between the photoelectric conversion element 1 and the vertical shift register, and a part of the wiring 10' is used as the gate electrode and drain of the over-70-MOS transistor 8. By combining the two, it is possible to greatly reduce the reduction in aperture ratio due to the addition of an overflow MOS transistor and to suppress pluming.

FIG. 2 shows another embodiment, which corresponds to FIG. The vertical separation of each photoelectric conversion element 1 is determined by the electrode wiring (13-1 or 13-1) of the vertical shift register.
-2) Performed by setting i to a predetermined potential. 1 and the adjacent vertical shift register on the right side is overflow M
Wiring 1 that also serves as the drain and gate of the OS transistor
This is done at 0'. Further, in this embodiment, separation between 1 and the left vertical shift register for transferring signals is performed by a wiring 15 which also serves as a transfer gate 7'. There is an advantage that the usual thick oxide film for element isolation is unnecessary, the area of the element isolation region can be effectively reduced, and the opening can be made larger than in the embodiment of FIG. Furthermore, transfer gate 7't! It also has the advantage of being easier to drive because it can be controlled separately from the clock of the load transfer element.

Figures 3 and 4 are examples of ponds corresponding to Figures 2 and 1(b), respectively, in which the drain of an overflow MOS transistor is shared between two upper and lower photoelectric conversion elements. Therefore, the number of through holes 14 can be halved, which is advantageous in manufacturing the device (in terms of yield). 5 and 6 further show that in FIGS. 3 and 4, one overflow MOS transistor is provided per photoelectric conversion element, and two overflow MOS transistors are provided at the top and bottom for each photoelectric conversion element.
This is an example in which an S transistor is provided. Variations in overflow MOS transistors due to variations during device manufacturing can be effectively eliminated, and the ability to discharge excess charge can be increased.

In the above embodiment, a vertical shift register having two gate electrodes per photoelectric conversion element was described, but it is also possible to construct a vertical shift register with two or four gate electrodes per photoelectric conversion element and to carry two charges. Even when used as a vertical shift register, the effects of the present invention remain the same.

Here, the photodiode 1 may be a lightly doped N layer that is completely depleted during signal reading, or may be a highly doped N0 layer that is not depleted.

In addition, the photodiode is not a junction type as mentioned above, but
MIS type (Metel engineering n5ulator Sem1
Con-dHctor f may be used.

The above embodiments may be implemented, for example, on a P-type silicon substrate or in a P-type well on an N-type silicon substrate.

FIG. 7 shows an example implemented in a P-type well on an N-type silicon substrate. In (a), the drain 19 of the over-70-MOS transistor is not connected to the wiring 10 but to the substrate. (b) is a plan view, and sectional view t-(
It is shown in C). 31 is, for example, an N-type substrate, and 32 is a P-type well layer. The well layer in the through hole 24 portion is removed, and the side surface of the hole is also used as the gate region of the overflow MOS transistor, and the lower surface of the hole is in contact with the N-type substrate 31, so the charge overflowing from the photodiode 1 is transferred to the wiring 10'. The lower part of the P-type well layer can be drained into the N-type substrate 31 through the surface of the P-type well layer and the gate channel region on the side surface of the hole, which acts as a drain. Here, 33 is a thick oxide film for element isolation, and 34 is an N-swelled diffusion layer that extends to the channel of the vertical charge transfer element.

The embodiment shown in FIG. 8 is an example in which the method shown in FIG. 7 is applied to FIG. 2, and shows a cross section along lines 35-36. There is no thick oxide film for element isolation, and the isolation function is provided by the wiring 10'.

It is clear that the method shown in FIG. 7 can also be applied to the embodiments shown in FIGS. 3 to 6.

[Effects of the Invention] According to the present invention, overflow MO can be achieved without reducing the aperture ratio.
8) It is possible to effectively arrange the windshield and has the effect of completely suppressing pluming.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. 3, 4, 5 and 6 are plan layout diagrams showing other embodiments of the invention, FIG. 7 is a diagram showing still another embodiment of the invention, and FIG. 15 1 showing the case where the embodiment of FIG. 7 is applied to the embodiment of FIG. 2]
(Ku) Figure Z/D' Oats V-Foo-kL, > Funeral Wiring 3 Figure 4 ■ 5 Figure 6 Figure ■ 7 Figure (a-) Banquet 7 (b)

Claims (1)

[Scope of Claims] 1. A plurality of photoelectric conversion elements, a charge transfer element group for reading optical signal charges accumulated in the photoelectric conversion element group, and an overflow MOS transistor for sweeping out excess optical signal charges to the outside are mounted on the same semiconductor substrate. In the charge transfer type solid-state imaging device integrated above, an element isolation region between the charge transfer element and the adjacent photoelectric conversion element is allocated to the overflow MOS transistor, and a conductive wiring is run in the element isolation region. A charge transfer type solid-state image sensor, characterized in that at least the gate electrode of the overflow MOS transistor is formed of a part of the conductive wiring. 2. A charge transfer type solid-state imaging device according to claim 1, wherein the drain of the overflow MOS transistor is connected to the conductive wiring. 3. A charge transfer type solid-state image pickup device according to claim 1, wherein the conductive wiring has a device isolation function between the photoelectric conversion device and the adjacent charge transfer device.