JP2559465B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to an image pickup device, and more particularly to a solid-state image pickup device in which a plurality of light receiving elements and the like are integrated on a semiconductor substrate.

[Conventional technology]

The solid-state image pickup device is required to have a resolution as high as that of an image pickup element tube used in current television broadcasting. For this reason, the semiconductor substrate has a vertical (column) direction.
A picture element matrix in which 500 picture elements (800 to 1000 picture elements (photoelectric conversion elements) are arranged in the horizontal (row) direction) and a scanning element for scanning these picture elements are required. Therefore, such a solid-state image pickup device is manufactured by using a MOS large-scale circuit technology capable of high integration, and is generally used as a constituent element of the Charge device.
Coupled devices (CCD) or MOS transistors are used.

An example in which an SOI (Silicon On Insulator) structure is adopted for the switching transistor of the MOS type solid-state image pickup device will be described below. For this, iM
86, Technical digest page 369-372 (IEDM86, Techni
cal Digest, pp369-372). This conventional example will be described with reference to FIGS. 2 and 3.
FIG. 2 is a diagram showing a circuit configuration of a MOS type solid-state imaging device. Plural photodiodes 101, 20 in a p-type silicon substrate
1, 301 and 401 are arranged in a matrix, and MOS transistor switches 104, 204, 304 and 404 for selecting each of these hol diodes are connected to the corresponding photodiodes. The photodiode and the MOS transistor switch are combined to form one picture element. The signal lines 510 and 511 for outputting signal charges are connected to the output ends of the MOS transistor switches 104, 204, 304 and 404 in the vertical direction (column direction). MOS transistor switch 104,204,3
04 and 404 are sequentially scanned by the gate lines 512 and 513 output from the shift register 514. As a result, the photodiode 10
The signal charges generated by the light incident on the 1,201,301,401 are output through the MOS transistor switches 104,204,304,404 and the signal lines 510,511.

FIG. 3 is a view showing a sectional structure in the vicinity of one photodiode shown in FIG. An oxide film 12 is formed in the p-type silicon substrate 17.
And an n-type impurity region (n + layer) 15 which constitutes a photodiode and is separated by a p-type impurity region (p + diffusion layer) 11. The oxide film 12 and the p-type impurity region 11 are
This is an element isolation region, and in particular, it is called a pixel isolation region because it separates picture elements (pixels) from each other. This n-type impurity region (n +
Layer) 15 to M consisting of source 16, drain 6 and gate 7.
The OS transistor is provided so as to extend on the oxide film 12. The entire device is covered with a protective film 14, and a signal line 8 is connected to the drain 6. Here, the MOS transistor consisting of the source 16, the drain 6, and the gate 7 is
The n-type impurity region (n + layer) 15 is used as a seed region (Seeding re
It is formed within the recrystallized SOI structure as gion). Therefore, it is possible to reduce the parasitic capacitance between the drain 6 and the p-type silicon substrate 17, and thus the parasitic capacitance of the signal line 8 is also reduced, and the output noise level can be suppressed. This is because the square of the output noise current is proportional to the total capacitance of the signal line 8. In addition, this kind of MO
The S-type solid-state imaging device is also described in USP 4,551,742.

However, in the above-mentioned conventional technique, the leak current flowing between the source 16 and the drain 6 of the MOS transistor formed in the SOI flows between the source and the drain of the MOS transistor formed in the silicon substrate 17. The fact that it is much larger than the leakage current was found by experiments. Then, they found a new problem of generation of new noise component and loss of signal charge due to the leak current in the SOI. This problem is the SOI structure MOS
This is a major obstacle to the practical application of the solid-state imaging device.

[Problems to be Solved by the Invention]

An object of the present invention is to suppress the above leakage current while maintaining the SOI
It is an object of the present invention to provide a solid-state imaging device capable of suppressing parasitic capacitance due to its structure.

[Means for solving the problem]

The above object is to provide a first MOS transistor switching element in which each switch for scanning is formed in a semiconductor substrate,
A second MOS transistor switching element formed in a semiconductor provided on a semiconductor substrate via an insulator is connected in series, and the first switching element is arranged on the side of the light receiving portion, and the second switching element is provided. This is achieved by adopting a structure in which the element is arranged on the signal output end side.

[Action]

Since the MOS transistor arranged on the light receiving portion side is formed in the semiconductor substrate, almost no leak current is generated. Further, the MOS transistor arranged on the signal output end side is formed in the semiconductor provided on the insulator on the semiconductor substrate, so that the parasitic capacitance on the drain side, that is, the signal line can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of a MOS type solid-state imaging device which is an embodiment of the present invention. The same components as those in FIG. 2 are designated by the same reference numerals as those in FIG.

The photodiodes 101, 201, 301, 401 are formed in a matrix in a p-type silicon substrate (not shown). In the figure, for convenience, a case of 4 pixels of 2 × 2 is shown.
Two MOS transistor switches connected in series are connected to each photodiode. For example, the photodiode 101 is connected with a series connection of MOS transistor switches 105 and 106. In this embodiment,
One pixel is composed of one photodiode and two MOS transistor switches. The vertical signal lines 510 and 511 for outputting the signal charges are MOS in the vertical direction (column direction).
The transistor switches 106, 306, 206 and 406 are respectively connected to the output terminals thereof and transfer signal charges in the vertical direction. The two MOS transistor switches 105 and 106 forming the picture element are connected in parallel to the gate line 512 output from the vertical shift register 514 so that they are simultaneously scanned. The vertical shift register 514 sequentially scans pixels in the vertical direction via the gate lines 512 and 513. One ends of the vertical signal lines 510 and 511 are connected to the horizontal signal line 526 via the MOS transistor switches 515, 516, 517 and 518. Horizontal signal line, 526 is vertical signal line 51
The signal charge from 0,511 is transferred to the output end. The MOS transistor switches 515,516,517,518 are horizontal shift registers 519.
Thus, the scanning is sequentially performed in the horizontal direction. The MOS transistor switches 515, 516 and 517, 518 are respectively connected in series, like the MOS transistor switches 105, 106 for forming pixels.

The operation of this embodiment will be described below. Each photodiode 10
Light is incident on 1,201,301,401 via a camera lens. Then, in the photodiode 101, signal charges corresponding to incident light are accumulated. This signal charge is transferred to the vertical signal line 510 by the MOS transistor switches 105 and 106 scanned at a predetermined time. The signal charge transferred onto the vertical signal line 510 is also scanned by the MOS transistor 5 scanned at a predetermined time.
15,516, transferred to the horizontal signal line 526, transferred on the horizontal signal line 526, output from the output end to the outside,
It is processed as a video signal. The above operation is performed in other picture elements.

FIG. 4 shows one set of two of the read MOS transistor switches 515 to 518 connected in series in FIG.
It is a figure which shows the cross-section of S transistor switch 515,516. The cross-sectional views of the switches 517 and 518 are the same as this and will be omitted. A p-type well 10 is formed on the n-type silicon substrate 9. In the p-type well 10, there is provided an n-type MOS transistor 515 composed of a source 18, a drain 19 and a gate 20, which are separated by an insulating film 12 such as SiO ₂ and a p-type impurity region (p + diffusion layer) 11. is there. Here, the insulating film 12 and the p-type impurity region 11 form an element isolation region. Moreover The MOS transistor 515 upward, silicon or formed on the insulating film 13 such as SiO ₂ (hereinafter S OI (Silicon o n I nsulator ) and called) in the source 21, drain 22, and the gate 23 type MO
An S transistor 516 is provided. A wiring 24 made of a low resistance material such as aluminum is connected to the source 18 of the MOS transistor 515 or 517. This wiring 24 is the third
It corresponds to the vertical signal line 510 in the figure. Similarly, a wiring 25 connects the drain 19 of the MOS transistor 515 and the source 21 of the MOS transistor 516 in the SOI. A wiring 26 made of a low resistance material such as aluminum is connected to the drain 22 of the MOS transistor 516 in the SOI. This wiring 26 corresponds to the horizontal signal line 526 in FIG. This example is
The MOS transistor switch 515 or 517 of FIG. 3 is formed in the silicon substrate (p-type well 10), and the MOS transistor switch 516 or 518 is formed in the SOI formed on the semiconductor substrate via the insulating film. . That is, the signal charge is input from the wiring 24 connected to the vertical signal line 510 and output from the wiring 26 connected to the horizontal signal line 526 when the gates 20 and 23 are opened. Since the drain 22 of the MOS transistor 516 or 518 provided in the SOI is separated from the silicon substrate by the thick insulating film 13, the drain 19 of the MOS transistor 515 or 517 provided in a normal silicon substrate is provided. Its parasitic capacitance is much smaller. Therefore, according to the structure shown in FIG. 4, it is possible to reduce the parasitic capacitance on the horizontal signal line 526 and the wiring 26 when the gates 20 and 23 are both closed. In addition, M provided in SOI
The problem that the leak current flowing between the source 21 and the drain 22 of the OS transistor 516 or 518 is generally large is
The leakage current between the source 18 and the drain 19 of the MOS transistors 515 and 517 provided in the silicon substrate is reduced and can be ignored.

FIG. 5 is a diagram showing a cross-sectional structure of one picture element composed of two MOS transistor switches shown in FIG. In FIG. 5, an n-type impurity region (n-type diffusion layer) 1 forming the photodiode 101 is used as a source, an n-type impurity region provided adjacent to this is made a drain 2, and a gate 3 is provided between them. , A MOS transistor 105 is provided in the silicon substrate. It consists of source 5, drain 6 and gate 7.
A MOS transistor 106 is provided in SOI. Drain 6
The wiring 8 corresponding to the vertical signal line 510 is connected to. The drain 2 and the source 5 are connected by a wiring 4.
The other structure is the same as that of FIG. The signal charge accumulated in the n-type impurity region (n-type diffusion layer) 1 for the photodiode is transferred to the wiring 8 connected to the vertical signal line 510 when the gate 3 and the gate 7 are turned on. At this time, according to the embodiment of FIG. 5, the parasitic capacitance of the vertical signal line 510 and the wiring 8 when the gate 3 and the gate 7 are off can be reduced, and at the same time, the n-type diffusion layer for forming the photodiode is formed. The leakage current between the vertical signal line 510 and the vertical signal line 510 and the wiring 8 can be suppressed for the same reason as described in FIG.

In the embodiment shown in FIG. 1, it is explained about the case where the SOI structure is adopted for both the MOS transistor forming the pixel and the MOS transistor between the vertical signal line 510 and the horizontal signal line 526. It may be provided. However, providing both of them is more effective in suppressing the leak current and reducing the parasitic capacitance.

FIG. 6 is a sectional view showing a first modified example of FIG. In FIG. 6, the wiring 4 in FIG. 5 is omitted, and the drain 2 and the source 5 are directly connected. Others In this embodiment, the gate 3 of the MOS transistor 105, which is formed in the silicon substrate without the insulating film 13, is provided.
However, it also serves as the gate of the MOS transistor 106 in the SOI composed of the source 5 and the drain 6. Others are the same as those in FIG. In this modification, the same effects as those of the embodiment of FIG.
A part of the MOS transistor 106 is used as n for forming a photodiode.
Since it is provided on the mold diffusion layer 1, it is advantageous for increasing the resolution of the solid-state imaging device capable of reducing the area per pixel. Further, the drain 2 portion is used as a seed region.
Since the SOI part is recrystallized, the MOS transistor in SOI 1
It is possible to improve the characteristics such as mobility of 06.

FIG. 7 is a sectional view showing a second modification of FIG. In FIG. 7, the drain 6 of the MOS transistor in the SOI is provided on the gate 3. Others are the same as the sixth one. In this modification, the same effect as that of the modification of FIG. 6 can be obtained, and since the drain 6 does not cover the n-type diffusion layer 1 for forming the photodiode, the sensitivity of the solid-state imaging device can be deteriorated. Absent.

FIG. 8 is a sectional view showing a third modification example of FIG. FIG. 8 shows that the gate 3 in FIG. 6 is a MOS in SOI.
It is located above the source 5 and the drain 6 of the transistor 106, with the gate 3 of both MOS transistors 105,106.
It is commonly connected as the gate of. Others are the same as in FIG. In the embodiment of FIG. 8, the same effect as that of the embodiment of FIG. 5 can be obtained, and since the SOI portion can be recrystallized by using the drain 2 portion as a seed region, it is formed in the SOI. MOS transistor 106
It is possible to improve the characteristics such as the mobility of the.

FIG. 9 is a diagram showing a fourth modification of FIG. In FIG. 9, the wiring 4 and the insulating film 13 of FIG. 5 are omitted, and the drain 2 and the source 5 are directly connected. Others are the same as those in FIG. Also in this modification, the fifth
The same effect as the embodiment shown in the figure can be obtained, and since the SOI part is formed by the method of recrystallizing the drain 2 part as the seed region, the MOS in SOI formed of the source 5, the drain 6 and the gate 7 is formed. It is possible to improve characteristics such as mobility of the transistor.

FIG. 10 is a diagram showing a fifth modification of FIG. First
In FIG. 10, the MOS transistor in the SOI of FIG. 5 is located above the n-type diffusion layer 1 for forming the photodiode. Others are the same as those in FIG. According to this modification, the fifth
The same effect as that of the embodiment in the figure can be obtained, and the area per pixel can be reduced as in the case of FIG. 6 and the first modification, and the resolution of the solid-state imaging device can be increased. You can However, since the SOI structure interrupts part of the light incident from the n-type diffusion layer 1 for forming the photodiode, it is better to make the SOI structure as thin as possible and increase the amount of light transmission.

FIG. 11 is a diagram showing a sixth modified example of FIG. First
In FIG. 11, the drain 6 of the MOS transistor in the SOI of FIG. 5 is shared by a plurality of adjacent pixels. That is, the drains of the MOS transistor switches 106 and 306 commonly connected to the vertical signal line 510 in FIG. 3 are shared. Others are the same as those in FIG. According to this modification, the area per pixel can be reduced by reducing the number of contacts between the drain 6 and the wiring 8.
This is advantageous for increasing the resolution of the solid-state imaging device.

In the above embodiment, the number of pixels of the solid-state imaging device is 2
Although the description has been limited to x2, the present invention does not particularly limit the number of pixels. In addition, the p-type and n-type of the semiconductor may be reversed, and the semiconductor does not necessarily have to be silicon. Note that the present invention can be applied to any semiconductor structure formed on an insulator, whether it is single crystal, polycrystal, or amorphous.

FIG. 12 is a diagram showing a modification of the circuit configuration shown in the embodiment of FIG.

Differences between FIG. 12 and FIG. 1 will be described below. Among the MOS transistors provided for each of the photodiodes 101, 201, 301, 401, the MOS transistor switches 102, 202, 302, 402 on the photodiode side are selected by the vertical shift register 507 via the vertical gate lines 508, 509. In addition, the horizontal signal lines 527 and 528 are connected to the MOS transistor switches 103 and 20.
3,303,403 are selected by the horizontal shift register 506 via the horizontal gate lines 524,525. MOS transistor switch 501, which connects the horizontal signal lines 527, 528 and the vertical signal line 505,
502, 503, 504 are selected by the vertical shift register 507. Further, MOS transistor switches 520 and 521 for sweeping out noise charges on the horizontal signal lines 527 and 528, a gate line 522 for sweeping out, and a drain 523 for sweeping out are provided. This is because the signal charges generated by the light incident on the photodiodes 101 to 401 are transferred to the MOS transistor switches 102, 202, 202 by the vertical shift register 507 and the horizontal shift register 506.
By selecting 302, 402 and 103, 203, 303, 403, the signal is output from the end of the vertical signal line 505 via the horizontal signal lines 527, 528. Here, the horizontal signal lines 527 and 528 and the vertical signal lines 505
MOS transistor switch 501,502,503,504 to connect with
3 has the same structure as the MOS transistor switches 515 and 516 of FIG. 3, that is, the structure of FIG. in this case,
The wiring 24 in FIG. 4 is connected to the horizontal signal lines 527 and 528 in FIG. 12, and the wiring 26 is connected to the vertical signal line 505 in FIG. According to the present embodiment, it is possible to reduce the parasitic capacitance of the vertical signal line 505 in FIG. 12 and also suppress the leak current between the horizontal signal lines 517 and 528 and the vertical signal line 505. Any one of FIG. 5, FIG. 9, FIG. 10, and FIG. 11 is used for the cross-sectional structure of one picture element composed of the photodiodes 101, 201, 301, 104 and the MOS transistor switches 102, 202, 302, 403 in FIG. In this case, the wiring 8 in FIG. 5 is connected to the horizontal signal lines 527 and 528 in FIG. The gate 3 is connected to the horizontal gate lines 524 and 525 in FIG. 12, and the gate 7 is connected to the vertical gate lines 508 and 509 in FIG.
Such a connection relationship is also applied to those shown in FIGS. 9, 10 and 11. When the structure of FIG. 11 is applied to the circuit configuration of FIG. 12, the shared MOS transistors are the MOS transistors 103 and 203 commonly connected to the horizontal signal line 527.
Is. According to this embodiment, the horizontal signal line in FIG.
It is possible to reduce the parasitic capacitance of 527 and 528, and also to suppress the leak current between the photodiodes 101, 201, 301 and 401 and the horizontal signal lines 527 and 528.

As described above, the respective embodiments and modified examples shown in FIGS. 6 to 11 show the cross-sectional structure of the MOS transistors 105 and 106 constituting the pixel.
When used by connecting to the n-type diffusion layer 1 shown in FIG. 11, it can be applied to the MOS transistors 515, 516 or 517, 518.

〔The invention's effect〕

According to the present invention, by forming the MOS transistor switch in the semiconductor provided on the insulator on the semiconductor substrate, the parasitic capacitance of the signal line can be reduced, and at the same time, another MOS transistor switch can be connected in series with the parasitic capacitance. By forming in the semiconductor substrate, it is possible to suppress the generation of leak current to the signal line, it is possible to suppress the noise of the solid-state image pickup device, and thus the conventional leak current of the MOS transistor is large. Regarding SOI technology that was not practically practical, another MOS transistor switch was provided in the substrate to solve the problem of leak current all at once.
It is possible to improve the SOI technology to a practical technology.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a MOS type solid-state image pickup device according to an embodiment of the present invention, and FIG. 2 is a conventional MOS technique.
FIG. 3 is a diagram showing a circuit configuration of the solid-state image pickup device, FIG. 3 is a diagram showing a sectional structure in the vicinity of the photodiode of FIG. 1, and FIG.
FIG. 3 is a diagram showing a cross-sectional structure of read-out MOS transistor switches 515 and 516 connected in series in FIG. 3, and FIG. 5 is a diagram showing a cross-sectional structure of one pixel composed of the photodiode of FIG. 3 and two MOS transistor switches. FIG. 6 is a view showing a first modification of FIG. 5, FIG. 7 is a view showing a second modification of FIG. 5, and FIG. 8 is a view showing a third modification of FIG. , 9th
5 is a diagram showing a fourth embodiment of FIG. 5, FIG. 10 is a diagram showing a fifth modification of FIG. 5, and FIG. 11 is a diagram showing a sixth modification of FIG. FIG. 12 shows a modification of the embodiment shown in FIG. 1 ... Photodiode n-type diffusion layer, 2 ... MOS in substrate
Drain of transistor, 5 ... Source of MOS transistor in SOI, 6 ... Drain of MOS transistor in SOI.

Claims (7)

(57) [Claims] 1. A semiconductor device provided in a semiconductor substrate of a first conductivity type,
A plurality of photoelectric conversion elements for accumulating signal charges according to incident light, a first signal line for transmitting the signal charges of the photoelectric conversion elements in a predetermined direction row in the predetermined direction, and accumulated in the photoelectric conversion elements. First switch means for transferring the signal charge to the first signal line, output means for converting the signal charge transferred by the first signal line into an output signal, and the first switch means. And a scanning means for scanning the switch means in a predetermined order, the first switch means is a first MOS transistor having a part of the photoelectric conversion element as a first electrode. And a second MOS transistor having a first electrode connected to the second electrode of the first MOS transistor and a second electrode connected to the first signal line, The first MOS type transistor is the semiconductor substrate Formed with, said second
A solid-state imaging device, wherein the MOS transistor is formed on the semiconductor substrate via an insulating film. 2. The photoelectric conversion elements are arranged in a matrix, and the solid-state imaging device further transfers the signal charges transferred by the first signal line to the output means.
Signal line, a second switch means for transferring the signal charge of the first signal line to the second signal line, and a scan for scanning the second switch means in a predetermined order. The solid-state imaging device according to claim 1, further comprising: 3. The second switch means includes a third MOS transistor having a first electrode connected to the first signal line, and a first electrode on a second electrode of the third MOS transistor. And a fourth MOS transistor having a second electrode connected to the second signal line, the third MOS transistor being formed using the semiconductor substrate. The solid-state imaging device according to claim 2, wherein the fourth MOS transistor is formed on the semiconductor substrate via an insulating film. 4. The scanning means is commonly connected to the gate electrode of the first MOS type transistor via the first gate line of the second switch means, and scans them in a predetermined order. 1 scanning means and a second scanning means which is connected to the gate electrode of the second MOS type transistor through a second gate line and scans this in a predetermined order. The solid-state imaging device according to claim 2 or 3. 5. The second MOS transistor is arranged on a pixel isolation region between a pixel region composed of the photoelectric conversion element and the first MOS transistor. The solid-state imaging device according to any one of 1 to 4. 6. The second MOS type transistor is arranged on a pixel region formed of the photoelectric conversion element and the first MOS type transistor.
5. The solid-state imaging device according to any one of items 4 to 4. 7. The solid-state imaging device according to claim 1, wherein the second electrode of the second MOS transistor is shared by at least two adjacent pixels. apparatus.