JP3298259B2 - Charge transfer element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device used for charge transfer such as a solid-state image pickup device and a CCD delay line, and more particularly to a frame interline transfer (FIT) system and an interline transfer (IT) system. The present invention relates to a charge transfer element suitable for use as a vertical transfer register in a solid-state imaging device.

[0002]

2. Description of the Related Art Recently, for example, in a solid-state image pickup device for a 1-inch optical system for high definition television (HDTV),
In order to prevent a propagation delay of a transfer clock applied to a vertical transfer register, a CCD solid-state imaging device having a shunt wiring structure has been proposed.

Here, a conventional CCD solid-state imaging device having a shunt wiring structure will be described with reference to FIGS. 8 and 9. FIG.

[0004] The solid-state imaging device shown in FIG. 8 includes, for example, an N-type impurity diffusion region 103 for forming a light receiving portion on the surface of a first P-type well region 102 formed on an N-type silicon substrate 101. An N-type transfer channel region 104 and a P-type channel stopper region 105 constituting a vertical transfer register are formed.
A P-type positive charge storage region 106 and a second P-type well region 107 for reducing smear are formed directly below the N-type transfer channel region 104 on the surface of the substrate 03. The P-type region 108 between the N-type impurity diffusion region 103 and the transfer channel region 104 forms a read gate.

Here, a light receiving portion 109 (photoelectric conversion portion) is constituted by a photodiode formed by a PN junction J between the N-type impurity diffusion region 103 and the first P-type well region 102, and a large number of light receiving portions 109 are provided. The imaging areas are arranged in a matrix. In the case of color imaging, one pixel is formed by, for example, four light receiving units 109 adjacent to each other, depending on the color arrangement of color filters (three primary color filters and complementary color filters) formed corresponding to the light receiving unit 109. It is supposed to.

Also, an N-type transfer channel region 104, a channel stopper region 105, and a read gate unit 108
On the upper side, four transfer electrodes 111 (first to fourth transfer electrodes 111 a to 111 a) formed by a first polycrystalline silicon layer and a second polycrystalline silicon layer via a gate insulating film 110 made of, for example, SiO _2. 111d: see FIG. 9), and the transfer channel region 104, the gate insulating film 110, and the transfer electrode 111 constitute a vertical transfer register.

Each transfer electrode 111 is formed so as to extend in the horizontal direction (the direction perpendicular to the direction in which the transfer channel region 104 extends), and the light receiving sections 1 adjacent in the vertical direction are formed.
09 (the region for separating the light receiving portion 109 and the region for forming the wiring), in one region, the first transfer electrode of the first polycrystalline silicon layer is used. 111a and the fourth transfer electrode 111d of the second polycrystalline silicon layer are formed so as to overlap with each other. And the second transfer electrode 111b of the second polycrystalline silicon layer are formed so as to overlap with each other.

On each transfer electrode 111, a shunt wiring layer 1 made of an Al layer is interposed via a thick planarizing film 112.
13 is formed to extend in the vertical direction, and a light-shielding film 116 of an Al layer is formed on the shunt wiring layer 113 via an interlayer insulating film 115 so as to also extend in the vertical direction.

Each of the shunt wiring layers 113 includes first to fourth transfer electrodes 111a to 111 corresponding to each column.
d is selectively electrically connected via the contact portion 114. And, in each shunt wiring layer 113,
For example, four-phase transfer clocks φV1 to φV4 are selectively applied, and the first
The first to fourth transfer clocks φV1 to φV4 are individually applied to the to fourth transfer electrodes 111a to 111d, respectively. By the application of the four-phase transfer clocks φV1 to φV4, signal charges read from the light receiving unit 109 during the readout period are transferred to the horizontal transfer register (not shown) in row units along the vertical transfer register.

In the conventional solid-state imaging device shown in FIG. 8, a protective film, a flattening film, a color filter, a micro condenser lens, and the like on the shunt wiring layer 113 are omitted for simplicity.

[0011]

By the way, the charge transfer devices used in the conventional solid-state imaging device are the first to the first.
The shunt wiring layer 113 of the Al layer is directly connected to the fourth transfer electrodes 111a to 111d through the contact portion 114. In this case, in the contact portion 114, Al as a material for forming the shunt wiring layer 113 and the first to fourth transfer electrodes 111a to 111
d reacts with polycrystalline silicon which is a material for forming the transfer channel region 1 under the contact portion 114.
Since the potential of No. 04 is different from the potential other than the contact portion 114, there has been a problem that transfer deterioration such as transfer remaining of signal charge is caused at the time of charge transfer. The potential fluctuation caused by the contact between Al and polycrystalline silicon is generally called a potential shift.

In order to prevent the potential shift, conventionally, as shown in FIG. 8, between the transfer electrode 111 and the shunt wiring layer 113, a buffer layer made of a third polycrystalline silicon layer is used. Electrode 117 is formed. Specifically, after the buffer electrode 117 is formed on the transfer electrode 111 via the thermal oxide film 118,
A flattening film 112 made of, for example, PSG for the purpose of insulation and flattening is formed on the buffer electrode 117, and then a shunt wiring layer 113 of a first Al layer is formed on the flattening film 112. Is formed, and this shunt wiring layer 1 is formed.
A light-shielding film 116 of a second Al layer is formed on the substrate 13 with an interlayer insulating film 115 interposed therebetween to constitute a solid-state imaging device.

However, in the conventional solid-state imaging device shown in FIG. 8, the potential shift in the transfer channel region 104 can be prevented by forming the buffering electrode 117. 1
Along with the formation of the electrode 17, a flattening film 112 is required between the electrode 117 and the shunt wiring layer 113, and a contact for making a contact between the buffer electrode 117 and the shunt wiring layer 113. Since a hole is required, the buffer electrode 117 cannot be made thin. Accordingly, the ratio of the opening width of the light receiving unit 109 to the height of the vertical transfer register, that is, the aspect ratio increases,
Peripheral edge (shoulder) of light-receiving portion opening in light-shielding film 116
There is a problem that the frequency of the reflection of the incident light to the outside, that is, the so-called "blur" increases, and the light receiving sensitivity is reduced.

In addition, with the increase in the aspect ratio, the formation of the light-shielding film 116 using the second Al layer, particularly the patterning process becomes difficult, and the line width of the shunt wiring layer 113 using the Al layer. However, the diameter of the contact hole between the shunt wiring layer 113 and the lower buffer electrode 117 is determined by the minimum rule, and the diameter cannot be further reduced. Therefore, the shunt wiring layer 113 and the upper layer Since the processing margin of the interlayer insulating film 115 between the light-shielding film 116 and the light-shielding film 116 is reduced and the processing becomes difficult, there is a problem that the number of steps is increased and the manufacturing cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to reduce the height of a transfer electrode forming portion, to prevent disconnection of a shunt wiring layer, and to achieve the above-described transfer. An object of the present invention is to provide a charge transfer element which is advantageous in manufacturing, such as facilitating formation of a film constituting a portion where an electrode is formed.

Another object of the present invention is to reduce the frequency of "shaking" of incident light by a light-shielding film formed on a transfer register when applied to a transfer register adjacent to a light receiving section of a solid-state image sensor. It is an object of the present invention to provide a charge transfer element which can reduce the charge and improve the light receiving sensitivity.

Another object of the present invention is to make it easy to form a light-shielding film surrounding a light-receiving section when applied to a transfer register adjacent to the light-receiving section of a solid-state imaging device. Another object of the present invention is to provide a charge transfer element capable of reliably performing light shielding between light receiving sections and effectively reducing smear.

[0018]

A charge transfer device according to the present invention comprises a set of a transfer channel region for charge transfer formed on a semiconductor substrate and a plurality of transfer electrodes, and is arranged in one direction along the transfer channel region. And a shunt wiring layer for shunting the corresponding transfer electrode with respect to the transfer electrode group. The shunt wiring layer is directly contacted with the lower transfer electrode via a contact hole. The upper conductive film is formed of a lower conductive film and an upper conductive film laminated on the lower conductive film, and the width of the upper conductive film is smaller than the width of the lower conductive film.

In this case, the lower conductive film can be formed of a polycrystalline silicon layer, and the upper conductive film can be formed of an Al layer.

Further, the charge transfer element according to the present invention is a set of a transfer channel region for charge transfer formed on a semiconductor substrate and a plurality of transfer electrodes, and is arranged in one direction along the transfer channel region. A transfer electrode group, a shunt wiring layer for shunting the corresponding transfer electrode for the transfer electrode group, a buffer electrode formed between the transfer electrode and the shunt wiring layer to prevent a potential shift in the transfer channel region, and a buffer electrode. And an insulating film formed on the buffer electrode between the shunt wiring layers. The insulating film is formed by thinning a part of the flattening film laminated on the buffer electrode.

Further, the charge transfer device according to the present invention is a transfer channel region for charge transfer formed on a semiconductor substrate and a plurality of transfer electrodes, and is arranged in one direction along the transfer channel region. A transfer electrode group, a shunt wiring layer for shunting the corresponding transfer electrode for the transfer electrode group, a buffer electrode formed between the transfer electrode and the shunt wiring layer to prevent a potential shift in the transfer channel region, and a buffer electrode. And an insulating film formed on the buffer electrode between the shunt wiring layers. The portion of the shunt wiring layer formed on the buffer electrode is provided on the insulating film located in a region where the flattening film laminated on the buffer electrode is partially removed.

The first contact hole formed between the transfer electrode and the buffer electrode and the second contact hole formed between the buffer electrode and the shunt wiring layer may be formed at different positions. Good.

[0023]

In the charge transfer device according to the present invention, the shunt wiring layer is a thin film lower conductive film directly contacted with the lower transfer electrode via a contact hole, and the upper conductive film laminated on the lower conductive film. Since the lower conductive film functions as a buffer electrode for preventing potential shift, the lower conductive film serves as a buffer electrode formed below the shunt wiring layer via an insulating film. The formation of the electrodes can be omitted.

As a result, it is possible to reduce the height of the laminated film formed on the transfer electrode, to prevent disconnection of the shunt wiring layer and to facilitate the formation of the laminated film formed on the transfer electrode. This is advantageous in manufacturing.

In particular, when the charge transfer device according to the present invention is applied to a transfer register adjacent to a light receiving section of a solid-state image pickup device, the height of the transfer register can be reduced as described above. It is possible to prevent an increase in the aspect ratio with respect to the light receiving unit opening. As a result,
The frequency of “shaking” of incident light by the light-shielding film formed on the transfer register can be reduced, and the light receiving sensitivity can be improved.

In addition, it is easy to form a light-shielding film in a shape surrounding the light-receiving portion, and accordingly, light-shielding between the light-receiving portions can be reliably performed, thereby effectively reducing smear. be able to.

In the charge transfer device according to the present invention, a buffer electrode for preventing a potential shift in the transfer channel region is formed between the transfer electrode and the shunt wiring layer. In between, the insulating film is formed by partially thinning the flattening film stacked on the buffer electrode, and the buffer electrode located in a region where the flattening film stacked on the buffer electrode is partially removed. Since the insulating film is provided on the insulating film and the shunt wiring layer is provided on the insulating film, it is not necessary to form a thick interlayer insulating film between the buffer electrode and the shunt wiring layer. It is possible to reduce the height of the laminated film. In particular, by partially reducing the thickness of the planarizing film formed on the buffer electrode, the insulating film between the light-shielding film and the shunt wiring layer can be easily formed.

Further, the first contact hole formed between the transfer electrode and the buffer electrode and the second contact hole formed between the buffer electrode and the shunt wiring layer are located at different positions. By forming, potential fluctuation due to contact between Al and polycrystalline silicon can be further reduced.

As a result, it is possible to prevent disconnection of the shunt wiring layer and to facilitate formation of a laminated film formed on the shunt wiring layer, which is advantageous in manufacturing. In particular, when the charge transfer device according to the present invention is applied to a transfer register adjacent to a light receiving unit of a solid-state imaging device, as described above,
Since the height of the transfer register can be suppressed, it is possible to prevent an increase in the aspect ratio between the transfer register and the light-receiving unit opening, and to reduce the “shaking” of incident light due to the light shielding film formed on the transfer register. Frequency can be reduced. This leads to an improvement in light receiving sensitivity.

In addition to the above, in addition to the above, it is easy to form a light-shielding film in a shape surrounding the light-receiving portion, so that light-shielding between the light-receiving portions can be reliably performed and smear can be reduced. Can be effectively achieved.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Several embodiments in which the charge transfer device according to the present invention is applied to a vertical transfer register in a frame interline transfer (FIT) type solid-state imaging device will be described below with reference to FIGS. I do.

First, frame interline transfer (FIT) to which the vertical transfer register according to the first embodiment is applied.
As shown in FIG. 1, the solid-state imaging device of the system includes a large number of light receiving units 1 that photoelectrically convert electric charges into an amount corresponding to the amount of incident light in a matrix. An image section 3 in which a number of vertical transfer registers 2 which are common to the arranged light receiving sections 1 are arranged in the row direction.
And the image portion 3
There is no light receiving section 1 formed in the
And a storage section 5 in which only a large number of vertical transfer registers 4 are respectively formed continuously from the large number of vertical transfer registers 2.

Further, two horizontal transfer registers adjacent to the storage section 5 and made common to the many vertical transfer registers 15 are provided in parallel. here,
Of the two horizontal transfer registers, the horizontal transfer register located on the storage unit 5 side is the first horizontal transfer register H
1. The other horizontal transfer register is set to the second horizontal transfer register H
Write 2.

Then, between the storage section 5 and the first horizontal transfer register H1, a signal charge transferred to the last stage of the vertical transfer register 4 in the storage section 5 is transferred to the first horizontal transfer register H1. Two vertical-horizontal transfer registers (not shown) are formed in common for a number of vertical transfer registers 4 and in parallel with each other. These vertical-horizontal transfer registers are supplied with vertical-horizontal transfer pulses φVH1 and φVH2, respectively, and by the supply of these transfer pulses φVH1 and φVH2, the signal charge from the vertical transfer register 4 is changed to the first signal.
Is transferred to the horizontal transfer register H1.

The first and second horizontal transfer registers H
1 and H2, the signal charge transferred to the first horizontal transfer register H1 is selectively transferred to the second horizontal transfer register H2.
A horizontal-horizontal transfer register HH for transferring to the side is extended in the horizontal direction along each horizontal transfer register H1 and H2. The horizontal-horizontal transfer register HH includes:
A horizontal-horizontal transfer pulse φHHG is supplied, and the supply of the transfer pulse φHHG causes the first
Signal charges in the horizontal transfer register H1
Is transferred to the horizontal transfer register H2.

The final stages of the first and second horizontal transfer registers H1 and H2 have first and second horizontal transfer registers, respectively.
Output units 6a and 6b are connected. These first and second output units 6a and 6b are connected to each horizontal transfer register H
A charge-electric signal conversion unit 7 composed of, for example, a floating diffusion or a floating gate for converting the signal charges transferred from the final stages 1 and H2 into an electric signal (for example, a voltage signal), and
A reset gate R for sweeping signal charges after conversion of an electric signal in the electric signal conversion section 7 to a drain region D
G, and an amplifier 8 for amplifying the electric signal from the charge-electric signal conversion unit 7.

On the vertical transfer register 2 in the image section 3 and on the vertical transfer register 4 in the storage section 5, for example, four layers of polycrystalline silicon are used.
Each of the vertical transfer electrodes is formed via an insulating film. That is, a set of four vertical transfer electrodes is formed, and a large number of the sets are sequentially arranged in the vertical direction.
The four vertical transfer electrodes φIM1 having different phases from each other are applied to the four vertical transfer electrodes in the image unit 3.
.About..phi.IM4, respectively, and four vertical transfer pulses .phi.ST1 to .phi.ST4 having mutually different phases are supplied to the four vertical transfer electrodes in the storage section 5, respectively.

By supplying these vertical transfer pulses φIM1 to φIM4 in the image unit 3 and four vertical transfer pulses φST1 to φST4 in the storage unit 5,
The potential distribution under each vertical transfer electrode in the image unit 3 and the storage unit 5 sequentially changes, whereby
The signal charges are respectively transferred to the vertical transfer register 2 in the image unit 3 and the vertical transfer register 4 in the storage unit 5.
Along the vertical direction (the first horizontal register H1 side).

In particular, in the image section 3, the light receiving section 1
The signal charges stored in the vertical transfer register 2 are firstly read out to the vertical transfer register 2 during the vertical flyback period, and then the signal charges transferred to the vertical transfer register 2 are quickly read into the storage unit 5 during the vertical flyback period. To the vertical transfer register 4.

The storage unit 5 transfers the signal charges transferred to the vertical transfer register 4 during the vertical blanking period to the first horizontal transfer register H1 side by row during the subsequent horizontal blanking period. As a result, the signal charge at the last stage of the vertical transfer register 4 is first transferred to the first horizontal transfer register H1 via the two vertical-horizontal transfer registers. The data is transferred to the second horizontal transfer register H2 via the horizontal-horizontal transfer register HH.

Then, in the next horizontal scanning period, the first
The signal charges are sequentially changed by applying two-phase horizontal transfer pulses φH1 and φH2 having different phases to the horizontal transfer electrodes formed of, for example, two polycrystalline silicon layers formed on the second horizontal transfer registers H1 and H2. It is transferred to the corresponding charge-electric signal conversion unit 7 on the output unit 6a and 6b side,
Each charge-electric signal conversion unit 7 converts the electric signal into an electric signal, and extracts the electric signal from the corresponding output terminal 9 via an amplifier 8.

Here, when a cross section around the light receiving section 1 of the solid-state imaging device is viewed, as shown in FIG. 3, for example, the surface of a first P-type well region 12 formed on an N-type silicon substrate 11 is formed. An N-type impurity diffusion region 13 for forming the light-receiving portion 1, an N-type transfer channel region 14 and a P-type channel stopper region 15 constituting the vertical transfer register 2 are formed. A P-type positive charge accumulation region 16 is formed on the surface of the region 13, and a second P-type well region 17 for reducing smear is formed directly below the N-type transfer channel region 14. The P-type region 18 between the N-type impurity diffusion region 13 and the transfer channel region 14 forms a read gate.

The N type impurity diffusion region 13 and the first P
A light receiving section 1 (photoelectric conversion section) is constituted by a photodiode formed by a PN junction J with the well region 12, and a large number of the light receiving sections 1 are arranged in a matrix to form an imaging area. In the case of color imaging, one pixel is formed by, for example, four light receiving units 1 adjacent to each other, depending on the color arrangement of color filters (three primary color filters and complementary color filters) formed corresponding to the light receiving unit 1. It is supposed to.

In the first embodiment, the first polycrystalline silicon layer is formed on the transfer channel region 14, the channel stopper region 15, and the read gate portion 18 via a gate insulating film 19 made of, for example, SiO2. And four transfer electrodes 20 (first and second polycrystalline silicon layers).
To the fourth transfer electrodes 20a to 20d: see FIG. 2), and the transfer channel region 14, the gate insulating film 19 and the transfer electrode 20 constitute the vertical transfer register 2. Note that, since the cross-sectional view of FIG. 3 shows a cross section taken along line AA of FIG.
Is shown only the transfer electrode 20a.

As shown in FIG. 2, each of the transfer electrodes 20a to 20d is formed so as to extend in the horizontal direction (in a direction perpendicular to the direction in which the transfer channel region 14 extends). In a region between the portions 1 (a region for separating the light receiving portion 1 and a region for forming wiring), in one region, the first transfer by the first polycrystalline silicon layer The electrode 20a and the second transfer electrode 20b of the second polycrystalline silicon layer are formed so as to overlap with each other. In the other region between the light receiving sections 1, the second transfer electrode 20b is formed of the first polycrystalline silicon layer. 3 transfer electrodes 20c and 2
The fourth transfer electrode 20d of the polycrystalline silicon layer is formed so as to overlap.

As shown in FIG. 3, a shunt wiring layer 22 is formed on each of the transfer electrodes 20a to 20d via an oxide film (SiO 2 film) 21, and an insulating layer is further formed on the shunt wiring layer 22. And PSG for planarization
A light-shielding film 24 of an Al layer is formed via an interlayer insulating film 23 made of (phosphosilicate glass) or the like. Note that, in the cross-sectional view of FIG.
The upper protective film, flattening film, color filter, micro condenser lens, and the like are omitted.

In plan view, as shown in FIG. 2, the shunt wiring layer 22 is formed so as to extend in the vertical direction, and the first to fourth transfer electrodes 20a respectively corresponding to the column unit. Contact portion 25a selectively with respect to .about.20d
To 25d electrically. Then, for example, a four-phase vertical transfer clock φ is applied to each shunt wiring layer 22.
IM1 to φIM4 are selectively applied, and the first to fourth transfer electrodes 20a to 20a to
The first to fourth vertical transfer clocks φIM1 to φIM4 are individually applied to 20d. By the application of the four-phase vertical transfer clocks φIM1 to φIM4, the signal charges read from the light receiving unit 1 during the readout period are transferred along the vertical transfer register 2 in the first horizontal transfer register shown in FIG. Transferred to H1 side.

As shown in FIG. 3, the shunt wiring layer 22 in the first embodiment passes through a contact portion 25 (contact hole) formed at a required portion of the oxide film 21 to form a lower transfer electrode 20 ( In the illustrated example, a third polycrystalline silicon layer 22a of a thin film electrically connected to the first transfer electrode 20a) and a first Al layer laminated on the thin polycrystalline silicon layer 22a 22b. In this embodiment, the thickness of the thin-film polycrystalline silicon layer 22a is on the order of 100 nm.

The thin polycrystalline silicon layer 22a
Can function as a buffer electrode for preventing the occurrence of potential shift in the transfer channel region 14 because the reaction between the lower transfer electrode 20 (polycrystalline silicon layer) and the upper Al layer 22b can be prevented. Will be.
Therefore, the shunt wiring layer 22 and the transfer electrode 20
In between, there is no need to form a thick buffer electrode, and the height above the transfer electrode 20 can be suppressed. In addition, since the width of the shunt wiring layer 22 can be made smaller than the width of the transfer electrode 20, a laminated film that is narrower upward overall can be formed on the transfer electrode 20.

The light-shielding film 24 formed on the shunt wiring layer 22 with the interlayer insulating film 23 interposed therebetween is, as shown in FIG. (In FIG. 2, the light-shielding film 24 is indicated by oblique lines.) That is, the light-shielding film 24 has a rectangular opening 24 a at a position corresponding to each light receiving unit 1,
Each light receiving unit 1 is formed so as to surround it from all sides. The light-shielding film 24 is set at a position where the peripheral edge of the opening protrudes toward the light receiving unit 1 beyond the opening width regulated by the transfer electrode 20.

Here, when the light receiving portion 1 is surrounded on all sides by the light shielding film 24, if the height above the transfer electrode 20 is large, the aspect ratio increases in relation to the opening width of the light receiving portion 1, and Reflection of incident light to the outside at the opening peripheral edge (shoulder portion) of the film 24, that is, the frequency of so-called "blur" increases,
This will cause a decrease in light receiving sensitivity.

However, in the first embodiment, as described above, a thick buffer electrode for preventing a potential shift can be omitted.
The height above the transfer electrode 20 can be kept low, and the increase in the aspect ratio can be avoided. Therefore, even if the light receiving section 1 is surrounded on all sides by the light-shielding film 24, the occurrence of the above-mentioned "blur" is reduced, and the light receiving sensitivity is not deteriorated. Furthermore, since the generation of smear due to surrounding the light receiving unit 1 from all sides can be efficiently reduced,
The image quality of the reproduced image can be improved.

As described above, according to the vertical transfer register 2 according to the first embodiment, the shunt wiring layer 22 is directly in contact with the lower transfer electrode 20 via the contact hole 25. And an upper Al layer 22 laminated on the thin-film polycrystalline silicon layer 22a.
b, the thin-film polycrystalline silicon layer 22a functions as a buffer electrode for preventing potential shift, and is formed below the shunt wiring layer 22 via an insulating film. The formation of the buffering electrode can be omitted.

As a result, the height of the stacked film formed on the transfer electrode 20 can be reduced, and the formation of the stacked film formed on the transfer electrode 20 can be facilitated. This is advantageous. Further, since the upper Al layer 22b is flattened by the lower thin-film polycrystalline silicon layer 22a, disconnection of the shunt wiring layer 22 can be prevented.

Therefore, when the present invention is applied to the vertical transfer register 2 adjacent to the light receiving section 1 of the solid-state image sensor as in the first embodiment, the height above the transfer electrode 20 can be suppressed as described above. In addition, since the cross-sectional structure of the laminated film formed on the transfer electrode 20 can be narrowed upward, the vertical transfer register 2 and the light receiving unit 1
It is possible to prevent an increase in the aspect ratio with the opening,
It is possible to reduce the frequency of “shaking” of the incident light by the light shielding film 24 formed on the vertical transfer register 2.

The fact that the height of the vertical transfer register 2 can be suppressed means that the formation of the light shielding film 24, particularly the patterning process, becomes very easy, and the light shielding film 24 can be easily patterned to surround the light receiving section 1. become. Accordingly, the light shielding between the light receiving sections 1 can be reliably performed, smear can be effectively reduced, and the frequency of occurrence of “blur” can be reduced. Improvement can be achieved. Further, the simplification of the patterning process of the light-shielding film 24 leads to an improvement in the opening shape of the light receiving portion 1, whereby the characteristics as an element can be improved and the unevenness of the photoelectric conversion characteristics of each light receiving portion 1 can be improved. Can be done.

Further, the fact that the cross-sectional structure of the laminated film formed on the transfer electrode 20 can be made narrower in the upward direction is that the interlayer insulating film between the shunt wiring layer 22 and the light shielding film 24 is formed. This leads to an improvement in the step coverage of the device, thereby improving the breakdown voltage and the yield of the device.

Further, of the thin-film polycrystalline silicon layer 22a and the Al layer 22b constituting the shunt wiring layer 22, the upper Al layer 22b is replaced with the lower thin-film polycrystalline silicon layer 22a regardless of the diameter of the contact hole 25. Can be formed to be narrower than the formation width, and as a result, the cross-sectional structure of the laminated film formed on the transfer electrode 20 can be made narrower upward and the interlayer insulation can be further reduced. Membrane 2
3 can improve the step coverage.

In the first embodiment, the shunt wiring layer is constituted by the thin-film polycrystalline silicon layer and the Al layer. However, the lower thin-film polycrystalline silicon layer prevents potential shift. Any film may be used. For example, a thin TiON film or another thin metal film may be used.

Next, frame interline transfer (FIT) to which the vertical transfer register according to the second embodiment is applied.
A solid-state imaging device of the system will be described with reference to FIGS. Note that components corresponding to those in FIG. 1 are denoted by the same reference numerals.

This solid-state imaging device is the first solid-state imaging device shown in FIG.
Although it has almost the same configuration as the solid-state imaging device to which the vertical transfer register according to the embodiment is applied, as shown in FIG. 5, the configuration of the laminated film formed on the transfer electrode 20 is different in the following points.

That is, in the second embodiment, as shown in FIG. 5, for example, the S channel is formed on the transfer channel region 14, the channel stopper region 15 and the read gate portion 18.
iO ₂ a gate insulating film 19 through the first layer polycrystalline silicon layer and four transfer electrodes 20 by second layer polycrystalline silicon layer (first to fourth transfer electrodes 20a~20
d: see FIG. 4), and these transfer channel regions 1
4. A vertical transfer register is constituted by the gate insulating film 19 and the transfer electrode 20. Note that, since the cross-sectional view of FIG. 5 shows a cross section taken along line BB of FIG. 4, only the first transfer electrode 20 a is shown as the transfer electrode 20.

Each transfer electrode 20 is formed to extend in the horizontal direction (direction perpendicular to the direction in which the transfer channel region 14 extends), similarly to the first embodiment, and the light receiving electrodes adjacent in the vertical direction are formed. In one of the regions between the parts 1, the first transfer electrodes 20a and 2a of the first polycrystalline silicon layer are formed.
A fourth transfer electrode 20d of a polycrystalline silicon layer of the layer is formed so as to overlap with the fourth transfer electrode 20d.
In other regions, the third transfer electrode 20c of the first polycrystalline silicon layer and the second transfer electrode 20c of the second polycrystalline silicon layer
And the transfer electrode 20b.

As shown in FIG. 5, a buffer electrode 31 of a third polycrystalline silicon layer is formed on each transfer electrode 20 via a thin oxide film (SiO 2 film) 21 as shown in FIG.
On this buffer electrode 31, a thin oxide film (SiO 2 film) 32
A shunt wiring layer 33 of a first Al layer is formed through the first wiring. Then, a light-shielding film 2 of a second Al layer is formed on the shunt wiring layer 33 via an interlayer insulating film 23 made of, for example, PSG for insulation and planarization.
4 are formed.

Normally, a thick flattening film 34 is interposed between the buffer electrode 31 and the shunt wiring layer 33 thereabove. However, the thickness of the flattening film 34 is hardly necessary in the portion between the buffer electrode 31 and the shunt wiring layer 33. If the buffer electrode 31 and the shunt wiring layer 33 are not physically in contact with each other, There is no problem with the oxide film 32 of the electrode 31.

Therefore, in the second embodiment, after a thick flattening film 34 is formed on the buffer electrode 31, the portion where the shunt wiring layer 33 is to be formed is thinned. The shunt wiring layer 33 is formed in the portion. In this example, the portion of the flattening film 34 where the shunt wiring layer 33 is formed is removed to expose the underlying oxide film 32, and the shunt wiring layer 33 is formed on the oxide film 32. I have to.

Also in this solid-state imaging device, the light-shielding film 24 formed on the shunt wiring layer 33 via the interlayer insulating film 23 is a solid-state imaging device to which the vertical transfer register according to the first embodiment is applied. Like the element, it is formed over the entire surface except for the position corresponding to each light receiving unit 1. That is, the light-shielding film 24 has a rectangular opening 24 a at a position corresponding to each light-receiving unit 1, and is formed so as to surround each light-receiving unit 1 from all sides. And this light shielding film 24
Is set at a position where the peripheral edge of the opening protrudes toward the light receiving section 1 beyond the opening width regulated by the transfer electrode 20.

Further, the light shielding film 24 in the second embodiment
Is set at a position where the peripheral edge of the opening protrudes toward the light receiving section 1 beyond the opening width regulated by the transfer electrode 20, and the lower interlayer insulating film 23 is formed on the end face on the light receiving section 1 side. The position is set closer to the transfer electrode 20 than the position of the peripheral edge of the opening of the light shielding film 24. That is, the upper light shielding film 24
As a result, only the gate insulating film 19 and the flattening film 34 are formed between the silicon surface on the light receiving portion 1 and the overhanging portion of the light-shielding film 24. And the thickness is thin. Therefore, the degree of obliquely incident light entering between the overhanging portion of the light-shielding film 24 and the silicon surface is reduced, which contributes to the reduction of smear.

Next, a method of manufacturing a solid-state imaging device to which the vertical transfer register according to the second embodiment is applied will be described with reference to FIG.
And a process chart of FIG. In addition,
Components corresponding to those in FIG. 5 are denoted by the same reference numerals.

First, as shown in FIG. 6A, a transfer electrode 20 is formed from the first and second polycrystalline silicon layers, and then thermally oxidized to form SiO2 on the surface of the transfer electrode 20.
A thin oxide film 21 made of is formed. Then, the oxide film 2
First, a first contact hole reaching the transfer electrode 20 is formed at a required location.

As shown in FIG. 4, the first contact hole is formed, for example, in the column where the shunt wiring layer 33 to which the transfer pulse φIM1 is applied is formed, for example, the first layer of polycrystalline silicon. An electrode portion of the first transfer electrode 20a formed of a silicon layer (a portion that contributes to actual signal charge transfer and is sandwiched between the left and right light receiving portions 1 on a plane) and has a transfer pulse φIM2 Is applied to the column where the shunt wiring layer 33 is formed, for example, the electrode portion of the second transfer electrode 20b formed of the second polycrystalline silicon layer, and the transfer pulse φIM3 is applied. In the column where the shunt wiring layer 33 is formed, for example, it is the electrode portion of the third transfer electrode 20c formed of the first polycrystalline silicon layer, and the transfer pulse φI
In the column where the shunt wiring layer 33 to which M4 is applied is formed, for example, it is the electrode portion of the fourth transfer electrode 20d formed of the second-layer polycrystalline silicon layer.

Thereafter, as shown in FIG. 6A, a third polycrystalline silicon layer is formed on the entire surface and then patterned to form a buffer on the transfer electrode 20 by the third polycrystalline silicon layer. An electrode 31 is formed. Thereafter, thermal oxidation is performed to form a thin oxide film 32 made of SiO _{2 on} the surface of the buffer electrode 31. Thereafter, a thick planarizing film 3 is formed on the entire surface.
4 is deposited. The manufacturing method up to this point is exactly the same as the conventionally used method.

Next, as shown in FIG. 6B, after forming a photoresist film (not shown) on the entire surface, exposure and development are performed to form an opening in a region corresponding to the buffer electrode 31. Then, the planarizing film 34 exposed from the opening of the photoresist film is removed by, for example, RIE (reactive ion etching) to expose the underlying oxide film 32. At this time, if the etching selectivity between the flattening film 34 and the oxide film 32 cannot be obtained, the oxide film 32 is also removed at the same time.
The lower buffer electrode 31 may be exposed and then thermally oxidized again to form an oxide film 32 on the buffer electrode 31, or a thin oxide film 32 may be deposited by high temperature CVD (HTO) or the like. You may make it.

After that, a second contact hole reaching the buffer electrode 31 is formed at a required portion of the oxide film 32. As shown in FIG. 4, the formation position of the second contact hole is, for example, the second contact hole in the column where the shunt wiring layer 33 to which the transfer pulse φIM1 is applied is formed.
In the column where the shunt wiring layer 33 to which the transfer pulse φIM2 is applied is formed, for example, the fourth transfer electrode 20d
In the column where the shunt wiring layer 33 to which the transfer pulse φIM3 is applied is formed, for example, the electrode portion of the fourth transfer electrode 20d, the transfer pulse φ
In the column where the shunt wiring layer 33 to which IM4 is applied is formed, for example, it is the electrode portion of the second transfer electrode 20b.

That is, the formation position of the first contact hole and the formation position of the second contact hole are different from each other.

Next, as shown in FIG.
After forming an Al layer as a layer by, for example, a sputtering method, a photoresist film (not shown) is formed thereon, and then, exposure and development processing is performed to make the photoresist film correspond to the buffer electrode 31. Leave on part. After that, A
The l layer is removed by etching to form a shunt wiring layer 33 of the first Al layer on the oxide film 32 in which the second contact hole is formed.

Next, as shown in FIG. 7A, an interlayer insulating film 23 made of, for example, PSG is deposited on the entire surface including the shunt wiring layer 33 by, for example, a CVD method.

Next, as shown in FIG. 7B, after a photoresist film (not shown) is formed on the interlayer insulating film 23, an exposure and development process is performed, and a portion corresponding to the transfer electrode 20 is formed. Leave on. Thereafter, the exposed interlayer insulating film 23 is removed by etching, and the end face of the interlayer insulating film 23 on the light receiving section 1 side is substantially the same as the end face of the transfer electrode 20 on the light receiving section 1 side, or somewhat inside or outside thereof. Position.

Thereafter, a second Al layer is formed on the entire surface by, for example, a sputtering method, and then a photoresist film (not shown) is formed on the Al layer. An opening is formed at a position corresponding to the light receiving unit 1. Thereafter, the Al layer exposed through the opening is removed by etching to form a light-shielding film 24 having a light-receiving portion opening 24a.
At this time, the peripheral edge of the opening of the light-shielding film 24 is set at a position protruding toward the light-receiving unit 1 beyond the opening width regulated by the transfer electrode 20. The upper surface and the side surfaces of the insulating film 23 are wrapped.

In the following steps, although not shown, a protective film is formed on the entire surface including the light shielding film 24, a flattening film is formed on the protective film, and a color filter is formed on the flattening film. After that, a micro condenser lens corresponding to each light receiving section is formed, and the solid-state imaging device according to this embodiment is manufactured.

According to the vertical transfer register according to the second embodiment, the flattening film 34 formed on the transfer electrode 20 is
A thin film is formed on the transfer electrode 20, and a shunt wiring layer 33 is formed on the thinned portion to form a flattening film 34.
Since the shunt wiring layer 33 is buried in the shape, the step due to the formation of the shunt wiring layer 33 is reduced, and the height of the stacked film formed on the transfer electrode 20 can be reduced accordingly. Become.

The first contact hole formed between the transfer electrode 20 and the buffer electrode 31 and the second contact hole formed between the buffer electrode 31 and the shunt wiring layer 33 are located at different positions. By forming, Al
Potential variation due to contact between the silicon and polycrystalline silicon can be further reduced.

As a result, it is possible to prevent disconnection of the shunt wiring layer 33 and to facilitate formation of a laminated film formed on the shunt wiring layer 33, which is advantageous in manufacturing.
In particular, when the present invention is applied to a vertical transfer register adjacent to the light receiving section 1 of the solid-state imaging device as in the second embodiment, the height of the vertical transfer register can be reduced as described above. The step coverage of the light-shielding film 24 can be improved by preventing an increase in the aspect ratio between the light-receiving portion and the aperture of the light-receiving portion. Can be reduced. This leads to an improvement in light receiving sensitivity.

The fact that the height of the vertical transfer register can be suppressed means that the formation of the light-shielding film 24, particularly the patterning process, becomes very easy, and the light-shielding film 2 surrounds the light receiving section 1.
4 can be easily patterned. Along with this,
The light shielding between the light receiving sections 1 can be reliably performed, the smear can be effectively reduced, and the image quality of the reproduced image can be improved in combination with the reduction in the frequency of occurrence of the above-mentioned “blur”. Can be. Further, facilitation of the patterning process of the light shielding film 24 leads to improvement of the opening shape of the light receiving unit 1. Thereby, the characteristics as an element can be improved, and the unevenness of the photoelectric conversion characteristics of each light receiving unit 1 can be improved.

In the second embodiment, the transfer electrode 20
The buffer electrode 31 is formed directly on the upper surface of the oxide film 21 including the first contact hole, and the wiring layer 33 for shunt is directly formed on the upper surface of the oxide film 32 on the buffer electrode 31 including the second contact hole. After the high melting point metal film such as tungsten is selectively buried in the first and second contact holes, the oxide film 21 including the first contact holes is formed. Alternatively, the buffer electrode 31 may be formed, and the shunt wiring layer 33 may be formed on the oxide film 32 including the second contact hole. In this case, the buffer electrode 31 and the shunt wiring layer 33 formed on the oxide films 21 and 32 can be planarized.

In the first and second embodiments,
An antireflection film may be formed between the light-shielding film 24 and the interlayer insulating film 23 thereunder. In this case, since the peripheral end face facing the light receiving section 1 is a laminated end face of the light shielding film 24 and the antireflection film, the transfer channel region 1 for obliquely incident light is provided.
4 can be more effectively reduced, and the occurrence of smear can be further reduced.

In the first and second embodiments, an example is shown in which the present invention is applied to the vertical transfer register of a solid-state image sensor of the frame interline transfer (FIT) system. The present invention can also be applied to a vertical transfer register of a solid-state imaging device of a system and a charge transfer register of a CCD delay line.

[0088]

As described above, according to the charge transfer device of the present invention, the shunt wiring layer is made of a thin conductive film directly contacted with the lower transfer electrode via a contact hole, and Since the upper conductive film is formed to be narrower than the lower conductive film, the height of the transfer electrode formation portion can be suppressed. This is advantageous in manufacturing, for example, preventing disconnection of the shunt wiring layer and facilitating formation of a film constituting a portion where the transfer electrode is formed.

When this charge transfer device is applied to a transfer register adjacent to the light receiving portion of the solid-state image pickup device, the frequency of "shaking" of incident light by the light shielding film formed on the transfer register is reduced. And the light receiving sensitivity can be improved. Further, it becomes easy to form a light-shielding film in a shape surrounding the light-receiving portion, and accordingly, light-shielding between the light-receiving portions can be reliably performed, and smear can be effectively reduced. Further, the cross-sectional structure of the laminated film formed on the transfer electrode can be made narrower upward, and the step coverage of the interlayer insulating film can be further improved.

According to the charge transfer device of the present invention, a buffer electrode for preventing a potential shift in the transfer channel region is formed between the transfer electrode and the shunt wiring layer, and the buffer electrode and the shunt are formed. Between the wiring layers for use, the flattening film laminated on the buffer electrode is partially thinned to form an insulating film, and a buffer located in a region where the planarizing film laminated on the buffer electrode is partially removed. Since the insulating film is provided on the electrode and the shunt wiring layer is provided on the insulating film, the height of the transfer electrode forming portion can be suppressed, the disconnection of the shunt wiring layer can be prevented, and the transfer electrode forming portion can be prevented. This is advantageous in manufacturing, such as facilitating the formation of a film constituting.

When this charge transfer device is applied to a transfer register adjacent to the light receiving portion of the solid-state image pickup device, the frequency of "shaking" of incident light by the light shielding film formed on the transfer register is reduced. And the light receiving sensitivity can be improved. Further, it becomes easy to form a light-shielding film in a shape surrounding the light-receiving portion, and accordingly, light-shielding between the light-receiving portions can be reliably performed, and smear can be effectively reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a frame interline transfer (FIT) type solid-state imaging device to which a charge transfer device according to the present invention is applied.

FIG. 2 is a plan view schematically showing an image portion of the solid-state imaging device in the first embodiment in which the charge transfer device according to the present invention is applied to a vertical transfer register in a solid-state imaging device of the FIT system.

FIG. 3 is a sectional view taken along line AA in FIG. 2;

FIG. 4 is a plan view schematically showing an image portion of a solid-state imaging device in a second embodiment in which the charge transfer device according to the present invention is applied to a vertical transfer register in a solid-state imaging device of the FIT system.

FIG. 5 is a sectional view taken along line BB in FIG. 4;

FIG. 6 is a process chart showing a method for manufacturing a solid-state imaging device to which the vertical transfer register according to the second embodiment is applied, and FIG. 6A shows a state in which a buffer electrode and a flattening film are formed on a transfer electrode; FIG. 2B shows a state in which the flattening film is partially thinned, and FIG. 2C shows a state in which a shunt wiring layer is formed on the thinned flattening film.

FIG. 7 is a process chart showing a method for manufacturing a solid-state imaging device to which the vertical transfer register according to the second embodiment is applied, and FIG. 7A shows a state in which an interlayer insulating film is formed on a shunt wiring layer. FIG. 2B shows a state in which a light-shielding film is formed after patterning the interlayer insulating film.

FIG. 8 is a cross-sectional view showing a schematic configuration around a light receiving section of a solid-state imaging device to which a vertical transfer register according to a conventional example is applied.

FIG. 9 is a plan view showing a schematic configuration around a light receiving section of a solid-state imaging device to which a vertical transfer register according to a conventional example is applied.

[Explanation of symbols]

Reference Signs List 1 light receiving unit, 2 and 4 vertical transfer register, 3 image unit, 5 storage unit, 6a and 6b first and second output unit, 7 charge-electric signal conversion unit, 8 amplifier, H1 and H2 first and second Horizontal transfer register, 11 silicon substrate, 12 first P-type well region, 13 N-type impurity diffusion region, Jpn junction (light receiving portion), 14 transfer channel region, 15 channel stopper region, 16 positive charge accumulation region , 17 second P-type well region, 18 read gate portion, 19 gate insulating film, 20 transfer electrode, 21 oxide film, 22 shunt wiring layer, 22a thin-film polycrystalline silicon layer, 22b Al layer, 23 interlayer insulating film, 24 light shielding film, 31 buffer electrode, 32 oxide film, 33 shunt wiring layer, 34 flattening film

Continuation of front page (56) References JP-A-5-145855 (JP, A) JP-A-5-206437 (JP, A) JP-A-4-239771 (JP, A) JP-A-6-268192 (JP) JP-A-63-120463 (JP, A) JP-A-3-161197 (JP, A) JP-A-4-279060 (JP, A) JP-A-7-226496 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/339 H01L 27/148 H01L 29/762 H04N 5/335

Claims (5)

(57) [Claims] 1. A transfer channel region for charge transfer formed on a semiconductor substrate, a group of transfer electrodes arranged in one direction along the transfer channel region as a set of a plurality of transfer electrodes, and the transfer electrode A shunt wiring layer for shunting the corresponding transfer electrode for each group, wherein the shunt wiring layer is a lower conductive film directly in contact with the lower transfer electrode via a contact hole; and the lower conductive film. A charge transfer element formed from an upper conductive film laminated thereon, wherein the width of the upper conductive film is smaller than the width of the lower conductive film. 2. The charge transfer device according to claim 1, wherein said lower conductive film is formed of a polycrystalline silicon layer, and said upper conductive film is formed of an Al layer. 3. A transfer channel region for charge transfer formed in a semiconductor substrate, a group of transfer electrodes arranged in one direction along the transfer channel region as a set of a plurality of transfer electrodes, A shunt wiring layer for shunting the corresponding transfer electrode for each group; a buffer electrode formed between the transfer electrode and the shunt wiring layer to prevent a potential shift in the transfer channel region; a buffer electrode and the shunt And an insulating film formed on the buffer electrode between the wiring layers for use, wherein the insulating film is formed by partially reducing a flattening film laminated on the buffer electrode. Transfer element. 4. A transfer channel region for charge transfer formed on a semiconductor substrate, a group of transfer electrodes arranged in one direction along the transfer channel region as a set of a plurality of transfer electrodes, and the transfer electrode A shunt wiring layer for shunting the corresponding transfer electrode for each group; a buffer electrode formed between the transfer electrode and the shunt wiring layer for preventing a potential shift in the transfer channel region; a buffer electrode and the shunt An insulating film formed on the buffer electrode between the wiring layers for use, and a portion of the shunt wiring layer formed on the buffer electrode partially includes a planarization film laminated on the buffer electrode. A charge transfer element provided on the insulating film located in the removed region. 5. A first contact hole formed between the transfer electrode and the buffer electrode, and a second contact hole formed between the buffer electrode and the shunt wiring layer at different positions. The charge transfer device according to claim 3, wherein the charge transfer is performed.