JP2006086232A - Mos type solid-state image pickup device, and camera - Google Patents
Mos type solid-state image pickup device, and camera Download PDFInfo
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本発明は、固体撮像装置に係わり、特に増幅型ＭＯＳ（Metal Oxide Semiconductor)センサを用いた固体撮像装置であって、撮像面積の大きな受光部を持つ固体撮像装置の画質安定化を図るための技術に属する。 The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device using an amplification MOS (Metal Oxide Semiconductor) sensor, and a technique for stabilizing the image quality of a solid-state imaging device having a light-receiving portion with a large imaging area. Belonging to.
ＭＯＳ型固体撮像装置の従来の画素構造について図６を用いて説明する。半導体基板６１上に、第１の第１導電型ウェル６２、第２の第１導電型ウェル６３、第３の第１導電型ウェル６４、第４の第１導電型ウェル６５を有し、このウェル領域内に第２導電型フォトダイオード６６とその上部に第１導電型表面層７を有する。第１の第１導電型ウェルはフォトダイオード６６の領域には注入しないよう選択的に形成している。 A conventional pixel structure of the MOS type solid-state imaging device will be described with reference to FIG. On the semiconductor substrate 61, a first first conductivity type well 62, a second first conductivity type well 63, a third first conductivity type well 64, and a fourth first conductivity type well 65 are provided. A second conductivity type photodiode 66 is provided in the well region, and a first conductivity type surface layer 7 is provided thereon. The first first conductivity type well is selectively formed so as not to be implanted into the region of the photodiode 66.
また、フォトダイオード６６に蓄積した光蓄積信号を転送し、電圧変換ためのドレイン領域９とフォトダイオード６６からドレイン領域９へ光蓄積信号を転送する読み出しゲート８を有する。 Further, it has a drain region 9 for transferring a light accumulation signal accumulated in the photodiode 66 and a voltage conversion, and a readout gate 8 for transferring the light accumulation signal from the photodiode 66 to the drain region 9.
読み出しゲート８を介してドレイン領域９へ転送された光蓄積信号は電圧変換され、ドライブトランジスタ１１および負荷トランジスタ１３とで構成されるソースフォロア回路によりインピーダンス変換されて電圧出力される。 The light accumulation signal transferred to the drain region 9 via the read gate 8 is voltage-converted, impedance-converted by a source follower circuit composed of a drive transistor 11 and a load transistor 13, and output as a voltage.
従来の構造による、第１の第１導電型ウェル６２、第２の第１導電型ウェル６３、第３の第１導電型ウェル６４、第４の第１導電型ウェル６５の不純物濃度の関係は、第１の第１導電型ウェル＞第２の第１導電型ウェル≧第３の第１導電型ウェル≧第４の第１導電型ウェルという関係が一般的である。 The relationship between the impurity concentrations of the first first conductivity type well 62, the second first conductivity type well 63, the third first conductivity type well 64, and the fourth first conductivity type well 65 according to the conventional structure is as follows. In general, the relationship is: first first conductivity type well> second first conductivity type well ≧ third first conductivity type well ≧ fourth first conductivity type well.
この意味するところは、第１の第１導電型ウェル６２は搭載するトランジスタの閾値電圧を設計する上で重要であり、おおよそ半導体プロセスが決定された段階で濃度設定が完了しているべきものである。 This means that the first first conductivity type well 62 is important in designing the threshold voltage of the transistor to be mounted, and the concentration setting should be completed when the semiconductor process is determined. is there.
しかし、第１の第１導電型ウェル６２、第２の第１導電型ウェル６３、第３の第１導電型ウェル６４、第４の第１導電型ウェル６５は、フォトダイオードの空乏層をどの深さまで必要とするかにより決定される。通常、カメラで使用される光電変換分光特性を意識して、フォトダイオードの空乏層を１〜１．５μｍ程度まで伸ばすことができるような濃度設定にしている。 However, the first first conductivity type well 62, the second first conductivity type well 63, the third first conductivity type well 64, and the fourth first conductivity type well 65 are used to determine the depletion layer of the photodiode. It depends on what you need to the depth. Usually, the concentration is set so that the depletion layer of the photodiode can be extended to about 1 to 1.5 μm in consideration of the photoelectric conversion spectral characteristics used in the camera.
しかしながら、通常の固体撮像装置において、次のような問題があった。１つ目としては、第１の第１導電型ウェル６２でほぼ支配されるウェル抵抗値は、受光部の面積拡大に伴い無視できないものとなり、ウェル電位を安定化させるためには抵抗値の低減が必要である。２つ目としては、例えば特許文献１に開示されているように、受光部内ウェル電位の安定化には、各画素内のウェルコンタクトおよび配線が有効であるが、画素内にコンタクトを形成することは、無効領域の増加につながり、基本特性の確保に悪影響を与える。 However, the conventional solid-state imaging device has the following problems. First, the well resistance value that is almost dominated by the first first conductivity type well 62 becomes non-negligible with the increase in the area of the light receiving portion, and the resistance value is reduced in order to stabilize the well potential. is required. Secondly, as disclosed in Patent Document 1, for example, well contacts and wirings in each pixel are effective for stabilizing the well potential in the light receiving unit, but a contact is formed in the pixel. Leads to an increase in the invalid area and adversely affects the securing of basic characteristics.
次に図７を参照しながら、従来技術におけるウェル電位を印加するレイアウトについて説明する。通常、論理演算を主体とするロジック系集積回路においては、図に示すようにチップ外周に備えた周辺回路用グランド配線７２を用いてチップ全体のウェル電位を設定している。基本的にＭＯＳ型固体撮像装置においてもこの方法は共通である。 Next, a layout for applying a well potential in the prior art will be described with reference to FIG. Normally, in a logic integrated circuit mainly for logical operations, the well potential of the entire chip is set using a peripheral circuit ground wiring 72 provided on the outer periphery of the chip as shown in the figure. Basically, this method is common to MOS solid-state imaging devices.
チップの面積が小さい場合、例えば２５ｍｍ2程度のチップサイズであれば、受光部にウェル抵抗の影響が出るものではない。しかし、チップサイズが１００ｍｍ2を越えるとウェル抵抗の影響が出始めるため、受光部周辺にウェル電位安定化配線を配置する、画素内にウェルコンタクトを配置するなどの工夫が施されてきた。
このように、受光部の拡大を前提とする高級ＤＳＣ（Digital Still Camera)向けＭＯＳ型固体撮像装置において、従来構造では、ウェル電位の安定化と性能確保の両立に限界があった。また、ウェル電位設定用配線を用いても、チップサイズ、受光部面積の拡大に伴う影響を防止できない。 As described above, in the MOS type solid-state imaging device for high-grade DSC (Digital Still Camera) that presupposes the enlargement of the light receiving portion, the conventional structure has a limit in achieving both well potential stabilization and performance securing. Further, even if the well potential setting wiring is used, it is impossible to prevent the influence due to the expansion of the chip size and the light receiving area.
本発明は、チップサイズ、受光部面積の拡大によるウェル電位の変動を最小化するとともに、画素部性能を最大化することに適した固体撮像装置およびカメラを提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device and a camera that are suitable for minimizing well potential fluctuations due to an increase in chip size and light receiving area, and maximizing pixel section performance.
上記課題を解決するため本発明のＭＯＳ型固体撮像装置は、ＤＳＣ等に備えられ、２次元配列されたフォトダイオードを含む受光部を有するＭＯＳ型固体撮像装置であって、半導体基板上に形成された第１導電型のウェル領域と、前記第１導電型のウェル領域中に形成された第２導電型の領域からなるフォトダイオード部とを有し、前記ウェル領域は深さ方向に２層以上に分割して形成され、前記ウェル領域における最も浅い第１層の不純物濃度は他の層に比べて低いことを特徴とする。 In order to solve the above problems, a MOS type solid-state image pickup device of the present invention is a MOS type solid-state image pickup device provided in a DSC or the like and having a light receiving portion including two-dimensionally arranged photodiodes, which is formed on a semiconductor substrate. A well region of the first conductivity type, and a photodiode portion comprising a second conductivity type region formed in the well region of the first conductivity type, and the well region has two or more layers in the depth direction. The impurity concentration of the shallowest first layer in the well region is lower than that of other layers.
この構成によれば、トランジスタ特性、画素特性を劣化させることなくウェル抵抗を低減することができる。これによって、ウェル電位の安定化を図り受光部の面積を大きくとることができる。 According to this configuration, the well resistance can be reduced without deteriorating transistor characteristics and pixel characteristics. As a result, the well potential can be stabilized and the area of the light receiving portion can be increased.
より具体的には、本発明の第１のＭＯＳ型固体撮像装置は、半導体基板上に形成された第１導電型のウェル領域とウェル領域上に形成された第２導電型領域とからなるフォトダイオード部と、フォトダイオード部の上部に形成された第１導電型の表面層と、第１導電型のウェル領域におけるフォトダイオード部の第２導電型領域近傍に形成された第２導電型のドレイン領域と、当該ドレイン領域とフォトダイオード部の第２導電型領域との間におけるウェル領域上部に設けられた読み出しトランジスタのゲート部とを有した画素として構成され画素を２次元に配列した受光部と、受光部で発生した光蓄積信号を順次Ｘ−Ｙアドレス方式で読み出すための水平および垂直走査回路、出力アンプなどを含めた周辺回路を有したＭＯＳ型固体撮像装置であって、第１導電型ウェル領域が深さ方向に２〜４種類に分割して形成され、最も浅い第１導電型ウェルを第１の第１導電型ウェル、深くなるに従い順次、第２の第１導電型ウェル、第３の第１導電型ウェル、第４の第１導電型ウェルとして形成し、かつ第１の第１導電型ウェルをフォトダイオード部以外を選択的に形成し、第２の第１導電型ウェル、第３の第１導電型ウェル、第４の第１導電型ウェルを受光部および周辺回路部を一括して形成し、かつ第２の第１導電型ウェルの不純物濃度が第１の第１導電型ウェルの不純物濃度より高いことを特徴としている。 More specifically, the first MOS type solid-state imaging device of the present invention is a photo comprising a first conductivity type well region formed on a semiconductor substrate and a second conductivity type region formed on the well region. A diode portion; a surface layer of a first conductivity type formed above the photodiode portion; and a drain of a second conductivity type formed in the vicinity of the second conductivity type region of the photodiode portion in the first conductivity type well region. A light receiving portion configured as a pixel having a region and a gate portion of a read transistor provided above the well region between the drain region and the second conductivity type region of the photodiode portion; MOS type solid-state imaging device having peripheral circuits including horizontal and vertical scanning circuits, output amplifiers and the like for sequentially reading out optical storage signals generated in the light receiving section by the XY address method The first conductivity type well region is formed by dividing the first conductivity type well region into 2 to 4 types in the depth direction, and the shallowest first conductivity type well is formed as the first first conductivity type well, and the second conductivity is sequentially increased. Forming the first conductivity type well, the third first conductivity type well, and the fourth first conductivity type well, and selectively forming the first first conductivity type well other than the photodiode portion; 2 first conductivity type wells, 3rd first conductivity type wells, and 4th first conductivity type wells are formed as a light receiving portion and a peripheral circuit portion at a time, and impurities of the second first conductivity type well are formed. The concentration is higher than the impurity concentration of the first first conductivity type well.
上記の構成によれば、第２の第１導電型ウェルの不純物濃度を増加させ、第１の第１導電型ウェルの濃度より高くすることによって、搭載しているトランジスタの閾値を変化させることなく受光部内ウェル抵抗を低抵抗化できる。受光部面積拡大に起因するウェル抵抗の影響は、特に光蓄積信号を電圧変換するドレイン領域のウェル電位が変動した場合に現れる。第２の第１導電型ウェルの抵抗値を下げることによって、受光部に印加されるパルスによるウェル電位変動を速やかに吸収することができるため、画質劣化を抑制することができる。 According to the above configuration, by increasing the impurity concentration of the second first conductivity type well and making it higher than the concentration of the first first conductivity type well, the threshold value of the mounted transistor is not changed. The well resistance in the light receiving section can be reduced. The influence of the well resistance resulting from the increase in the area of the light receiving portion appears particularly when the well potential of the drain region for converting the voltage of the light accumulation signal changes. By lowering the resistance value of the second first conductivity type well, it is possible to quickly absorb well potential fluctuations due to pulses applied to the light receiving portion, so that deterioration in image quality can be suppressed.
また、本発明のＭＯＳ型固体撮像装置は、半導体基板上に形成された第１導電型のウェル領域と、このウェル領域上に形成された第２導電型領域とからなるフォトダイオード部とフォトダイオード部の第２導電型領域上部に形成された第１導電型の表面層と、第１導電型のウェル領域におけるフォトダイオード部の第２導電型領域近傍に形成された第２導電型のドレイン領域と、当該ドレイン領域とフォトダイオード部の第２導電型領域との間におけるウェル領域上部に設けられた読み出しトランジスタのゲート部とを有した画素として構成され、画素を２次元に配列した受光部と、受光部で発生した光蓄積信号を順次Ｘ−Ｙアドレス方式で読み出すための水平および垂直走査回路、出力アンプなどを含めた周辺回路を有したＭＯＳ型固体撮像装置であって、第１導電型ウェル領域が深さ方向に２〜４種類に分割して形成され、最も浅い第１導電型ウェルを第１の第１導電型ウェル、深くなるに従い順次、第２の第１導電型ウェル、第３の第１導電型ウェル、第４の第１導電型ウェルとして形成し、かつ第１の第１導電型ウェル、第２の第１導電型ウェルをフォトダイオード部以外を選択的に形成し、第３の第１導電型ウェル、第４の第１導電型ウェルを受光部および周辺回路部を一括して形成し、かつ第３の第１導電型ウェルの不純物濃度が第１の第１導電型ウェル、第２の第１導電型ウェルの不純物濃度より高いことを特徴としている。 In addition, the MOS type solid-state imaging device of the present invention includes a photodiode section and a photodiode including a first conductivity type well region formed on a semiconductor substrate and a second conductivity type region formed on the well region. A surface layer of the first conductivity type formed on the second conductivity type region of the portion, and a drain region of the second conductivity type formed in the vicinity of the second conductivity type region of the photodiode portion in the first conductivity type well region And a light-receiving unit that is arranged in a two-dimensional manner, and includes a gate portion of a read transistor provided above the well region between the drain region and the second conductivity type region of the photodiode unit. MOS type solid-state imaging device having a peripheral circuit including a horizontal and vertical scanning circuit, an output amplifier and the like for sequentially reading out an optical storage signal generated in the light receiving unit by an XY address method In the device, the first conductivity type well region is formed by dividing the first conductivity type well region into 2 to 4 types in the depth direction. The second first conductivity type well, the third first conductivity type well, and the fourth first conductivity type well are formed, and the first first conductivity type well and the second first conductivity type well are formed as photodiodes. The first and second wells are selectively formed, the third first conductivity type well and the fourth first conductivity type well are collectively formed as the light receiving unit and the peripheral circuit unit, and the third first conductivity type well is formed. The impurity concentration is higher than the impurity concentration of the first first conductivity type well and the second first conductivity type well.
上記の構成によれば、第２の第１導電型ウェル、第３の第１導電型ウェルの不純物濃度を増加させ、第１の第１導電型ウェルの濃度より高くし、さらに第２の第１導電型ウェルをフォトダイオード部に形成しないよう選択的に形成する。これによって、搭載しているトランジスタの閾値を変化させることなく受光部内ウェル抵抗を低抵抗化でき、光蓄積信号を電圧変換するドレイン領域のウェル電位が変動した場合に現れる画質劣化を抑圧できるとともに、フォトダイオードの長波長側光電変換特性を改善することが可能である。 According to the above configuration, the impurity concentration of the second first conductivity type well and the third first conductivity type well is increased to be higher than the concentration of the first first conductivity type well, and the second second conductivity type well is further increased. One conductivity type well is selectively formed so as not to be formed in the photodiode portion. As a result, it is possible to reduce the well resistance in the light receiving unit without changing the threshold value of the mounted transistor, and it is possible to suppress deterioration in image quality that appears when the well potential of the drain region that converts the voltage of the light accumulation signal fluctuates. It is possible to improve the long wavelength photoelectric conversion characteristics of the photodiode.
ここで、前記ＭＯＳ型固体撮像装置は、受光部の外周部で接地またはその他の電位に固定するための受光部ウェル安定化配線及び基板−配線間ビアを具備し、基板−配線間ビアと第２の第１導電型ウェルと低抵抗で接続するため第１の第１導電型ウェルと同じ深さで第１の第１導電型ウェルより不純物濃度が高い第１導電型コンタクト注入を追加した構成としてもよい。 Here, the MOS type solid-state imaging device includes a light receiving unit well stabilizing wiring and a substrate-to-wiring via for fixing to the ground or other potential at the outer periphery of the light receiving unit, In order to connect to the first conductivity type well with a low resistance, the first conductivity type contact implantation having the same depth as the first first conductivity type well and having a higher impurity concentration than the first first conductivity type well is added. It is good.
上記の構成によれば、第２の第１導電型ウェルと受光部外周のウェル安定化配線間の抵抗を下げることができるため、低抵抗化した第２の第１導電型ウェルとの接続の低抵抗化が実現できる。 According to the above configuration, since the resistance between the second first conductivity type well and the well stabilization wiring on the outer periphery of the light receiving section can be lowered, the connection with the second resistance type second well with reduced resistance can be achieved. Low resistance can be realized.
ここで、前記ＭＯＳ型固体撮像装置は、受光部の外周部で接地またはその他の電位に固定するための受光部ウェル安定化配線及び基板−配線間ビアを具備し、基板−配線間ビアと第３の第１導電型ウェルと低抵抗で接続するため第１の第１導電型ウェル、第２の第１導電型ウェルと同じ深さで第１の第１導電型ウェル、第２の第１導電型ウェルより不純物濃度が高い第１導電型コンタクト注入を追加した構成としてもよい。 Here, the MOS type solid-state imaging device includes a light receiving unit well stabilizing wiring and a substrate-to-wiring via for fixing to the ground or other potential at the outer periphery of the light receiving unit, The first first conductivity type well and the second first conductivity type well have the same depth as the first first conductivity type well and the second first conductivity type well. A configuration in which a first conductivity type contact implantation having an impurity concentration higher than that of the conductivity type well is added may be employed.
上記の構成によれば、第３の第１導電型ウェルと受光部外周のウェル安定化配線間の抵抗を下げることができるため、低抵抗化した第２の第１導電型ウェルとの接続の低抵抗化が実現できる。 According to the above configuration, since the resistance between the third first conductivity type well and the well stabilization wiring on the outer periphery of the light receiving portion can be lowered, the connection with the second resistance type second well reduced in resistance can be achieved. Low resistance can be realized.
ここで、前記ＭＯＳ型固体撮像装置は、受光部ウェル安定化配線をアルミ配線などの低抵抗物質かつ２本以上の配線で直接入出力端子へ接続し、受光部のウェル電位の変動を最小化したことを特徴としている。 Here, in the MOS type solid-state imaging device, the light receiving unit well stabilization wiring is directly connected to the input / output terminal by a low resistance material such as aluminum wiring and two or more wirings, thereby minimizing fluctuation of the well potential of the light receiving unit. It is characterized by that.
上記の構成によれば、受光部内でウェル電位を均一にすることが可能であり、特に受光部面積が大きい場合（例えば４００ｍｍ2以上の場合）に有効である。 According to the above configuration, it is possible to make the well potential uniform in the light receiving portion, which is particularly effective when the area of the light receiving portion is large (for example, 400 mm 2 or more).
上記の構成により、本発明のＭＯＳ型固体撮像装置は、トランジスタ特性、画素特性を劣化させることなくウェル抵抗を低減することができる。これによって、ウェル電位の安定化を図り受光部の大面積化が可能である。また、本発明の配線レイアウトによって、さらに均一な撮像特性を実現することができる。 With the above configuration, the MOS type solid-state imaging device of the present invention can reduce well resistance without deteriorating transistor characteristics and pixel characteristics. As a result, the well potential can be stabilized and the area of the light receiving portion can be increased. Further, more uniform imaging characteristics can be realized by the wiring layout of the present invention.
（第１の実施の形態）
図１は、本発明の第１の実施形態によるＭＯＳ型固体撮像装置における画素部断面概略図である。図１に示すように、基板１中に形成した第１の第１導電型ウェル２と第２の第１導電型ウェル３と第３の第１導電型ウェル４と第４の第１導電型ウェル５の４つの深さの層に分割して形成したウェルと、ウェル中に形成され光電変換を行うフォトダイオード６と、フォトダイオード６上に形成された第１導電型表面層７と、フォトダイオード６に蓄積された光蓄積信号電荷を電圧に変換する浮遊拡散容量を有するドレイン領域９を形成する。
(First embodiment)
FIG. 1 is a schematic cross-sectional view of a pixel portion in a MOS type solid-state imaging device according to the first embodiment of the present invention. As shown in FIG. 1, a first first conductivity type well 2, a second first conductivity type well 3, a third first conductivity type well 4, and a fourth first conductivity type formed in a substrate 1. A well formed by dividing the well 5 into four depth layers, a photodiode 6 formed in the well for photoelectric conversion, a first conductivity type surface layer 7 formed on the photodiode 6, and a photo A drain region 9 having a floating diffusion capacitance for converting the photo-accumulated signal charge accumulated in the diode 6 into a voltage is formed.
その上部にはフォトダイオード６からドレイン領域９に光蓄積信号電荷を転送するための読み出しゲート８、ドライブトランジスタ１１および負荷トランジスタ１３で構成されドレイン領域９で変換した電圧を受けてインピーダンス変換するソースフォロア回路、ソースフォロア回路の電源である画素部電源１２、ドレイン領域９と画素電源部１２との間を導通させることでドレイン領域９の不要信号電荷をリセットするためのリセットトランジスタ１０を有している。以上から単位画素が構成される。光蓄積信号によって発生した電圧は、負荷トランジスタ１３を合わせて構成されるソースフォロアの出力として電圧振幅として出力される。 A source follower which is composed of a read gate 8, a drive transistor 11 and a load transistor 13 for transferring the photo-accumulated signal charge from the photodiode 6 to the drain region 9 and receives the voltage converted in the drain region 9 and converts the impedance. A pixel unit power source 12 which is a power source of the circuit and the source follower circuit, and a reset transistor 10 for resetting unnecessary signal charges in the drain region 9 by conducting between the drain region 9 and the pixel power source unit 12. . The unit pixel is configured from the above. The voltage generated by the optical accumulation signal is output as a voltage amplitude as an output of a source follower configured by combining the load transistor 13.
また、ＭＯＳ型固体撮像装置は、画素を２次元に配列した受光部と、受光部で発生した光蓄積信号を順次Ｘ−Ｙアドレス方式で読み出すための水平および垂直走査回路、出力アンプなどを含めた周辺回路を有している。 Further, the MOS type solid-state imaging device includes a light receiving unit in which pixels are two-dimensionally arranged, a horizontal and vertical scanning circuit for sequentially reading out light accumulation signals generated in the light receiving unit by an XY address method, an output amplifier, and the like. It has a peripheral circuit.
さらに、この構成の特徴は第１導電型ウェルを２層以上に分けて形成し、第２の第１導電型ウェル３の不純物濃度を第１の第１導電型ウェル２より高く設定することにある。本実施例では、第１導電型ウェルは４層構造で説明する。 Further, the feature of this configuration is that the first conductivity type well is formed in two or more layers, and the impurity concentration of the second first conductivity type well 3 is set higher than that of the first first conductivity type well 2. is there. In this embodiment, the first conductivity type well is described as a four-layer structure.
各ウェルの不純物分布最大値の位置は、例えば以下のような関係にある。第１の第１導電型ウェル：０．１μｍ以上０．８μｍ以下、第２の第１導電型ウェル：０．８μｍ以上１．６μｍ以下、第３の第１導電型ウェル：１．６μｍ以上２．２μｍ以下、第４の第１導電型ウェル：２．２μｍ以上２．７μｍ以下程度である。 The position of the maximum impurity distribution value in each well has, for example, the following relationship. First first conductivity type well: 0.1 μm to 0.8 μm, second first conductivity type well: 0.8 μm to 1.6 μm, third first conductivity type well: 1.6 μm to 2 .2 μm or less, fourth first conductivity type well: about 2.2 μm or more and 2.7 μm or less.
この形成方法としては、第１の第１導電型ウェル２はフォトダイオード６の領域には形成されないように選択的に形成し、第２の第１導電型ウェル３、第３の第１導電型ウェル４、第４の第１導電型ウェル５は一括して形成する。 As the formation method, the first first conductivity type well 2 is selectively formed so as not to be formed in the region of the photodiode 6, and the second first conductivity type well 3 and the third first conductivity type are formed. The well 4 and the fourth first conductivity type well 5 are formed together.
通常、第１の第１導電型ウェル２は搭載するトランジスタの閾値を決定する。よって、ウェル抵抗を下げることを目的に不純物の高濃度化を実施すると、閾値の変動やドレイン領域もしくは第２導電型チャネル間で耐圧劣化を伴う。 Usually, the first first conductivity type well 2 determines a threshold value of a transistor to be mounted. Therefore, if the impurity concentration is increased for the purpose of reducing the well resistance, the threshold value varies and the breakdown voltage deteriorates between the drain region or the second conductivity type channel.
第１導電型ウェルを分割して形成すると、第２の第１導電型ウェル３のみを高濃度化することができる。第２の第１導電型ウェルは、トランジスタの閾値に影響しない。よって、この高濃度化によって、大幅にウェル抵抗を押さえることができる。例えば、通常の濃度の１０倍程度にすると抵抗値を１／５程度に抑えることができる。 If the first conductivity type well is divided and formed, only the second first conductivity type well 3 can be highly concentrated. The second first conductivity type well does not affect the threshold value of the transistor. Therefore, the well resistance can be significantly suppressed by this high concentration. For example, when the concentration is about 10 times the normal concentration, the resistance value can be suppressed to about 1/5.
なお、第１導電型ウェルの分割数は２以上であれば可能であり上限は設けない。また、濃度設定についても上記に限るものではない。 Note that the number of divisions of the first conductivity type well is possible if it is two or more, and there is no upper limit. Further, the density setting is not limited to the above.
なお、上記のＭＯＳ型固体撮像装置は、デジタルスチルカメラ（ＤＳＣ）などに備えられる。
（第２の実施の形態）
図２は、本発明の第２の実施形態によるＭＯＳ型固体撮像装置における画素部断面概略図である。画素を構成する要素は第１の実施の形態とほぼ同等であるため、重複する説明は省略する。
The MOS solid-state imaging device is provided in a digital still camera (DSC) or the like.
(Second Embodiment)
FIG. 2 is a schematic cross-sectional view of a pixel portion in a MOS type solid-state imaging device according to the second embodiment of the present invention. Since the elements constituting the pixel are substantially the same as those in the first embodiment, a duplicate description is omitted.
図２の構成の特徴は、第３の第１導電型ウェル４が、第１の第１導電型ウェル２および第２の第１導電型ウェル３の不純物濃度より高く、また第１の第１導電型ウェル２、第２の第１導電型ウェル３ともにフォトダイオード６に形成されないよう選択的に形成する。例えば、通常の濃度の１０倍程度にすると抵抗値を１／３程度に抑えることができる。 2 is characterized in that the third first conductivity type well 4 is higher in impurity concentration than the first first conductivity type well 2 and the second first conductivity type well 3, and the first first Both the conductive well 2 and the second first conductive well 3 are selectively formed so as not to be formed in the photodiode 6. For example, when the concentration is about 10 times the normal concentration, the resistance value can be suppressed to about 1/3.
なお、第１導電型ウェルの分割数は３以上あれば可能であり上限は設けない。また、濃度設定についても上記に限るものではない。
（第３の実施の形態）
図３は、本発明の第３の実施形態によるＭＯＳ型固体撮像装置におけるレイアウト図と図中Ａ−Ａ'間の断面概略図である。
Note that the number of divisions of the first conductivity type well can be three or more, and there is no upper limit. Further, the density setting is not limited to the above.
(Third embodiment)
FIG. 3 is a layout diagram of the MOS type solid-state imaging device according to the third embodiment of the present invention and a schematic cross-sectional view taken along line AA ′ in the drawing.
本構成の特徴は、受光部周辺に配置する受光部ウェル安定化配線３１と受光部ウェル安定化配線３１と第２の第１導電型ウェル３を接続するビア１４を設け、この直下に第１の第１導電型ウェル２より不純物濃度が高いコンタクト注入３０を実施することにある。 The feature of this configuration is that a light receiving portion well stabilizing wiring 31 disposed in the periphery of the light receiving portion, a via 14 connecting the light receiving portion well stabilizing wiring 31 and the second first conductivity type well 3 are provided, and the first is provided immediately below this. The contact implantation 30 having an impurity concentration higher than that of the first conductivity type well 2 is performed.
第１の実施形態の説明で記述したが、第２の第１導電型ウェル３の濃度を１０倍に増加しても、ウェル抵抗が１／５程度であるのは、このコンタクト注入がないからである。したがって、本実施例は実施例１の構成をさらに効果的にするものである。 As described in the description of the first embodiment, even if the concentration of the second first conductivity type well 3 is increased 10 times, the well resistance is about 1/5 because there is no contact implantation. It is. Therefore, the present embodiment further improves the configuration of the first embodiment.
本実施例のようにコンタクト注入を実施することによって、第２の第１導電型ウェル３の濃度を１０倍にした場合、ウェル抵抗は１／８程度に低抵抗化できる。 By performing contact implantation as in this embodiment, when the concentration of the second first conductivity type well 3 is increased 10 times, the well resistance can be reduced to about 1/8.
本実施例では、受光部ウェル安定化配線は受光部外周を一周している場合を示したが、特に一周している必要はなく、上辺のみ、下辺のみ、左右のみなど様々な場合があり得る。また、同一材質で接続されている必要はなく、レイアウトによっては、別材質でジャンプ接続している場合もあり得る。 In the present embodiment, the case where the light receiving unit well stabilization wiring goes around the outer periphery of the light receiving unit is shown, but it is not necessary to make one round, and there are various cases such as only the upper side, only the lower side, and only the left and right. . Moreover, it is not necessary to connect with the same material, and depending on the layout, there may be a jump connection with a different material.
また、受光部からの距離は特に規定するものではなく、受光部ウェルの安定化を目的とし、またその効果がある距離であれば同等の内容である。
（第４の実施の形態）
図４は、本発明の第４の実施形態によるＭＯＳ型固体撮像装置におけるレイアウト図と図中Ａ−Ａ'間の断面概略図である。
Further, the distance from the light receiving portion is not particularly specified, and is the same as long as the distance is effective for the purpose of stabilizing the light receiving portion well.
(Fourth embodiment)
FIG. 4 is a layout diagram in the MOS type solid-state imaging device according to the fourth embodiment of the present invention and a schematic cross-sectional view between AA ′ in the drawing.
本構成の特徴は、受光部周辺に配置する受光部ウェル安定化配線と受光部ウェル安定化配線と第３の第１導電型ウェル４を接続するビアを設け、この直下に第１の第１導電型ウェル２、第２の第１導電型ウェル３より不純物濃度が高いコンタクト注入３０を実施することにある。 The feature of this configuration is that a light receiving portion well stabilization wiring, a light receiving portion well stabilization wiring, and a via that connect the third first conductivity type well 4 disposed in the periphery of the light receiving portion are provided, and the first first is directly below this. The purpose is to perform contact implantation 30 having an impurity concentration higher than that of the conductive type well 2 and the second first conductive type well 3.
実施例２の説明で記述したが、第２の第１導電型ウェル３の濃度を１０倍に増加しても、ウェル抵抗が１／３程度であるのは、このコンタクト注入がないからである。したがって、本実施例の内容は実施例２の構成をさらに効果的にするものである。 As described in the explanation of the second embodiment, even if the concentration of the second first conductivity type well 3 is increased 10 times, the well resistance is about 1/3 because there is no contact implantation. . Therefore, the contents of the present embodiment make the configuration of the second embodiment more effective.
本実施例のようにコンタクト注入を実施することによって、第２の第１導電型ウェルの濃度を１０倍にした場合、ウェル抵抗は１／７程度に低抵抗化できる。 By performing contact implantation as in this embodiment, when the concentration of the second first conductivity type well is increased 10 times, the well resistance can be reduced to about 1/7.
本実施例では、受光部ウェル安定化配線は受光部外周を一周している場合を示したが、特に一周している必要はなく、上辺のみ、下辺のみ、左右のみなど様々な場合があり得る。また、同一材質で接続されている必要はなく、レイアウトによっては、別材質でジャンプ接続している場合もあり得る。 In the present embodiment, the case where the light receiving unit well stabilization wiring goes around the outer periphery of the light receiving unit is shown, but it is not necessary to make one round, and there are various cases such as only the upper side, only the lower side, and only the left and right. . Moreover, it is not necessary to connect with the same material, and depending on the layout, there may be a jump connection with a different material.
また、受光部からの距離は特に規定するものではなく、受光部ウェルの安定化を目的とし、またその効果がある距離であれば同等の内容である。
（第５の実施の形態）
図５は、本発明の第５の実施形態によるＭＯＳ型固体撮像装置におけるレイアウト図と図中Ａ−Ａ'間の断面概略図である。
Further, the distance from the light receiving portion is not particularly specified, and is the same as long as the distance is effective for the purpose of stabilizing the light receiving portion well.
(Fifth embodiment)
FIG. 5 is a layout diagram in the MOS type solid-state imaging device according to the fifth embodiment of the present invention and a schematic cross-sectional view between AA ′ in the drawing.
本構成の特徴は、受光部ウェル安定化配線から例えばアルミ、銅などの金属材料から成る低抵抗物質で２本以上の複数配線によって直接、半導体チップの入出力端子５１に接続し、ＧＮＤ等の所定電位に固定している。本実施例では、受光部の４隅から４本の配線で接続している。特に、受光部の面積が４００ｍｍ2を超えると、受光部ウェル安定化配線３１の抵抗値も無視できなくなる。 The feature of this configuration is that the light receiving unit well stabilization wiring is directly connected to the input / output terminal 51 of the semiconductor chip by two or more wirings with a low resistance material made of a metal material such as aluminum, copper, etc. It is fixed at a predetermined potential. In this embodiment, the connection is made with four wires from the four corners of the light receiving portion. In particular, when the area of the light receiving part exceeds 400 mm 2 , the resistance value of the light receiving part well stabilization wiring 31 cannot be ignored.
この抵抗成分により電位の浮きが発生する。例えば、受光部ウェル安定化配線３１の一方から外部へ接続すると対角あるいは対面に配線したウェル電位変動を抑えられず、不均一な電位状態となる。本発明の形態によれば、対面方向のウェル電位を一致させることが可能である。 This resistance component causes a potential float. For example, if one of the light receiving unit well stabilization wirings 31 is connected to the outside, fluctuations in well potentials that are diagonally or faced to each other cannot be suppressed, resulting in a nonuniform potential state. According to the embodiment of the present invention, the well potentials in the facing direction can be matched.
本実施例では、受光部の４隅から４本の配線としたが、２本以上あれば十分な効果が得られる。 In this embodiment, four wirings are provided from the four corners of the light receiving unit, but a sufficient effect can be obtained with two or more wirings.
本発明のレンズ交換型高級ディジタルスチルカメラのような結像サイズが大きい分野に利用される固体撮像装置の製造に有用であり、その他、結像サイズが大きい分野、歯科用Ｘ線入力固体撮像装置、顔輪郭イメージ入力デバイスなどに適している。 The present invention is useful for manufacturing a solid-state imaging device used in a field having a large imaging size, such as a high-definition digital still camera of the present invention, and a field having a large imaging size. Dental X-ray input solid-state imaging device Suitable for face contour image input device.
また、本発明は結像サイズの拡大に対する効果のみならず、高速に信号を取り扱えるようになるという効果もあり、高速化を特徴とする固体撮像装置に適している。 The present invention is suitable not only for increasing the imaging size but also for enabling signals to be handled at high speed, and is suitable for solid-state imaging devices characterized by high speed.
１、６１ 基板
２、６２ 第１の第１導電型ウェル
３、６３ 第２の第１導電型ウェル
４、６４ 第３の第１導電型ウェル
５、６５ 第４の第１導電型ウェル
６、６６ フォトダイオード
７、６７ 第１導電型表面層
８ 読み出しゲート
９ ドレイン領域
１０ リセットトランジスタ
１１ ソースフォロア ドライブトランジスタ
１２ 画素部電源
１３ 負荷トランジスタ
１４ ビア
３０ コンタクト注入
３１ 受光部ウェル安定化配線
３２、７２ 周辺回路用グランド配線
３３、７３ 基板電圧印加配線
４０ コンタクト注入２
５１ 入出力端子
1, 61 Substrate 2, 62 First first conductivity type well 3, 63 Second first conductivity type well 4, 64 Third first conductivity type well 5, 65 Fourth first conductivity type well 6, 66 Photodiode 7, 67 First conductivity type surface layer 8 Read gate 9 Drain region 10 Reset transistor 11 Source follower Drive transistor 12 Pixel part power supply 13 Load transistor 14 Via 30 Contact injection 31 Light receiving part well stabilization wiring 32, 72 Peripheral circuit Ground wiring 33, 73 Substrate voltage application wiring 40 Contact injection 2
51 I / O terminal
Claims (8)
半導体基板上に形成された第１導電型のウェル領域と、
前記第１導電型のウェル領域中に形成された第２導電型の領域からなるフォトダイオード部とを有し、
前記ウェル領域は深さ方向に２層以上に分割して形成され、
前記ウェル領域における最も浅い第１層の不純物濃度は他の層に比べて低い
ことを特徴とするＭＯＳ型固体撮像装置。 A MOS type solid-state imaging device having a light receiving portion including two-dimensionally arranged photodiodes,
A first conductivity type well region formed on a semiconductor substrate;
A photodiode portion formed of a second conductivity type region formed in the first conductivity type well region;
The well region is formed by dividing into two or more layers in the depth direction,
The MOS type solid-state imaging device, wherein the impurity concentration of the shallowest first layer in the well region is lower than that of the other layers.
前記ウェル領域における基板表面から２番目の第２層の不純物濃度は前記第１層に比べて高い
ことを特徴とする請求項１記載のＭＯＳ型固体撮像装置。 The photodiode portion is formed in the first layer,
The MOS type solid-state imaging device according to claim 1, wherein an impurity concentration of the second layer second from the substrate surface in the well region is higher than that of the first layer.
前記フォトダイオード部は第１の層および第２の層内に形成され、
前記第１層および第２層の不純物濃度は第３層目の層に比べて低い
ことを特徴とする請求項１記載のＭＯＳ型固体撮像装置。 The well region is formed by dividing the well region into three or more layers including the first layer to the third layer in the depth direction;
The photodiode portion is formed in the first layer and the second layer,
The MOS type solid-state imaging device according to claim 1, wherein the impurity concentration of the first layer and the second layer is lower than that of the third layer.
前記受光部の外周部の一部あるいは周囲に受光部のウェル電位を安定化させるためのウェル安定化配線を有し、
前記ウェル安定化配線の下に位置する領域でかつ第１層内の領域は、第１層内の他の領域よりも不純物濃度が高い
ことを特徴とする請求項２記載のＭＯＳ型固体撮像装置。 The MOS-type solid-state imaging device further includes a well stabilization wiring for stabilizing the well potential of the light receiving unit at a part of or around the outer periphery of the light receiving unit,
3. The MOS type solid-state imaging device according to claim 2, wherein a region located under the well stabilizing wiring and a region in the first layer has a higher impurity concentration than other regions in the first layer. .
前記受光部の外周部の一部あるいは周囲に受光部のウェル電位を安定化させるためのウェル安定化配線を有し、
前記ウェル安定化配線の下に位置する領域でかつ第１層内および第２層内の領域は、第１層内および第２層内の他の領域よりも不純物濃度が高い
ことを特徴とする請求項３記載のＭＯＳ型固体撮像装置。 The MOS-type solid-state imaging device further includes a well stabilization wiring for stabilizing the well potential of the light receiving unit at a part of or around the outer periphery of the light receiving unit,
A region located under the well stabilization wiring and in the first layer and the second layer has a higher impurity concentration than other regions in the first layer and the second layer. The MOS type solid-state imaging device according to claim 3.
ことを特徴とする請求項４または５記載のＭＯＳ型固体撮像装置。 The MOS type solid-state imaging device according to claim 4 or 5, wherein the well stabilization wiring is formed of a metal material.
ことを特徴とする請求項４または５記載のＭＯＳ型固体撮像装置。 The MOS type solid-state imaging device according to claim 4 or 5, wherein the well stabilizing wiring is directly connected to an input / output terminal of a semiconductor chip.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010073906A (en) * | 2008-09-18 | 2010-04-02 | Sharp Corp | Solid-state imaging element, and electronic information apparatus |
| US8860099B2 (en) | 2009-09-25 | 2014-10-14 | Sony Corporation | Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device |
| JP2017055099A (en) * | 2015-09-10 | 2017-03-16 | キヤノン株式会社 | Solid state image sensor, manufacturing method of solid state image sensor and imaging system |
| JP7535747B2 (en) | 2019-09-05 | 2024-08-19 | パナソニックＩｐマネジメント株式会社 | Imaging device |
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2004
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| JP2010073906A (en) * | 2008-09-18 | 2010-04-02 | Sharp Corp | Solid-state imaging element, and electronic information apparatus |
| US8860099B2 (en) | 2009-09-25 | 2014-10-14 | Sony Corporation | Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device |
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| US9559131B2 (en) | 2009-09-25 | 2017-01-31 | Sony Corporation | Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device |
| US10090343B2 (en) | 2009-09-25 | 2018-10-02 | Sony Corporation | Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device |
| US11088187B2 (en) | 2009-09-25 | 2021-08-10 | Sony Corporation | Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device |
| JP2017055099A (en) * | 2015-09-10 | 2017-03-16 | キヤノン株式会社 | Solid state image sensor, manufacturing method of solid state image sensor and imaging system |
| JP7535747B2 (en) | 2019-09-05 | 2024-08-19 | パナソニックＩｐマネジメント株式会社 | Imaging device |
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