JP2017055099A - Solid state image sensor, manufacturing method of solid state image sensor and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce magnetic noise generating on the ground wiring in a solid state image sensor.SOLUTION: A solid state image sensor includes pixel ground wiring arranged on a pixel well region, peripheral ground wiring arranged on a peripheral well region, multiple pixels placed in the pixel well region, a read circuit placed in the peripheral well region, and having a first input terminal receiving pixel signals from the multiple pixels, and a second input terminal receiving a reference signal, and a reference signal circuit placed in the peripheral well region, having a first electrode to which the ground voltage is supplied, and outputting the reference signal to the second input terminal of the read circuit. The resistance value R1 of an electric path from one of multiple pixel well contacts to the first electrode, and the resistance value R2 of an electric path from one of multiple peripheral well contacts placed closest to the first electrode to the first electrode satisfy the relationship of R1<R2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technique for reducing magnetic noise generated in ground wiring in a solid-state imaging device.

  In recent years, there has been a demand for higher image quality in solid-state imaging devices, and noise suppression is indispensable for achieving high image quality. As such a noise suppression method, for example, Patent Document 1 discloses a technique for suppressing noise caused by a power source that drives a solid-state imaging device. In Patent Document 1, noise is suppressed by holding a reference signal of a readout circuit in a hold capacitor.

JP 2008-85994 A

  In the prior art disclosed in Patent Document 1, although noise generated in the signal line of the readout circuit can be suppressed, noise generated in the ground wiring is not considered. However, when a magnetic field is generated, the influence of the magnetic noise on the ground wiring cannot be ignored. This is because when the ground wiring forms a loop shape including the substrate inside or outside the solid-state imaging device, the induced electromotive force indicated by Faraday's law is generated in the ground wiring, and this is reflected as magnetic noise in the sensor output image. It is because it ends. For this reason, in Patent Document 1, there is a problem that magnetic noise generated in the ground wiring cannot be reduced. Therefore, an object of the present invention is to obtain a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an imaging system that can reduce magnetic noise generated in the ground wiring.

  A solid-state imaging device according to the present invention includes a semiconductor substrate including a pixel well region and a peripheral well region, a pixel ground wiring disposed on the pixel well region, a peripheral ground wiring disposed on the peripheral well region, A plurality of pixel well contacts that connect the pixel ground wiring and the pixel well region, a plurality of peripheral well contacts that connect the peripheral ground wiring and the peripheral well region, and a plurality of columns in the pixel well region, A readout circuit having a plurality of pixels each outputting a pixel signal, a first input terminal for receiving a pixel signal from the plurality of pixels, and a second input terminal for receiving a reference signal, disposed in the peripheral well region; The first electrode is disposed in the well region and supplied with a ground voltage, and outputs a reference signal to the second input terminal of the readout circuit. A reference signal circuit, and a wiring that connects the first electrode of the reference signal circuit and the pixel ground wiring, the resistance value R1 of the electrical path from one of the plurality of pixel well contacts to the first electrode, The resistance value R2 of the electrical path from one of the peripheral well contacts disposed closest to the first electrode to the first electrode satisfies a relationship of R1 <R2.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method and imaging system of a solid-state image sensor which can reduce the magnetic noise which arises in ground wiring can be obtained.

It is a figure which shows typically the structure of the solid-state image sensor which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the planar structure of the hold capacity | capacitance which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the cross-section of the hold capacity | capacitance which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the planar structure of the ground connection part which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the cross-sectional structure of the package containing the solid-state image sensor which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the equivalent circuit and ground potential distribution of the ground loop in the solid-state image sensor which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the planar structure of the ground connection part which concerns on the 2nd Embodiment of this invention. It is a figure which shows typically the planar structure of the ground connection part which concerns on the 3rd Embodiment of this invention. It is a figure which shows typically the planar structure of the ground connection part which concerns on the 4th Embodiment of this invention. It is a figure which shows typically the structure of the solid-state image sensor which concerns on the 5th Embodiment of this invention. It is a figure which shows typically the equivalent circuit and ground potential distribution of the ground loop in the solid-state image sensor which concerns on the 5th Embodiment of this invention. It is a figure which shows typically the magnetic noise contained in the input to the AD converter which concerns on the 5th Embodiment of this invention. It is a figure which shows typically the structure of the solid-state image sensor which concerns on the 6th Embodiment of this invention. It is a figure which shows typically the cross-section of the solid-state image sensor which concerns on the 6th Embodiment of this invention. It is a figure which shows typically the equivalent circuit and ground potential distribution of the ground loop in the solid-state image sensor which concerns on the 6th Embodiment of this invention. It is a figure which shows the structure of the imaging system which concerns on the 7th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited to the following embodiment, In the range which does not deviate from the summary, it can change suitably. In the drawings described below, components having the same function are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

[First Embodiment]
A solid-state imaging device according to the present embodiment will be described with reference to FIGS. FIG. 1 is a diagram schematically showing a configuration of a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state imaging device 1 shown in FIG. 1 includes a pixel well region 101, a peripheral well region 100, a vertical scanning circuit 70, and a peripheral circuit control unit 71. Each of the pixel well region 101 and the peripheral well region 100 is a semiconductor region formed on a semiconductor substrate. The pixel ground wiring 51 is disposed so as to overlap the pixel well region 101 in a plan view with respect to the semiconductor substrate. The peripheral ground wiring 50 is arranged so as to overlap the peripheral well region 100 in plan view with respect to the semiconductor substrate. The pixel array is arranged in the pixel well region 101 in which the pixel ground wiring 51 is arranged, and a plurality of pixels 10 are two-dimensionally arranged in the row direction and the column direction. Each pixel 10 includes a photoelectric conversion unit and an amplification unit that outputs a signal based on the charge generated by the photoelectric conversion unit. Each pixel 10 outputs a signal corresponding to light. The vertical scanning circuit 70 is configured by a shift register, for example, and performs drive control of the pixels 10 in units of rows. This drive control includes a reset operation, an accumulation operation, a signal readout operation from the pixel 10, and the like.

  The differential amplifier circuit 30 is disposed in the peripheral well region 100 in which the peripheral ground wiring 50 is disposed. A plurality of differential amplifier circuits 30 are provided corresponding to the plurality of columns formed by the plurality of pixels 10. The differential amplifier circuit 30 reads signals from the plurality of pixels 10 included in the corresponding column with reference to the reference signal. More specifically, the differential amplifier circuit 30 amplifies the difference between the signal input to the non-inverting input terminal (+) and the signal input to the inverting input terminal (−), and the solid-state imaging device 1 external To the video signal processing unit (see FIG. 13 described later). Here, pixel signals from a plurality of pixels 10 in the same column are input to the inverting input terminal (−) via a plurality of vertical signal lines 20 provided for each column. On the other hand, a control electrode of the hold capacitor 200 is connected to the non-inverting input terminal (+), and a reference signal is input via the switch transistor 300. The ground electrode of the hold capacitor 200 is connected to the pixel ground wiring 51. The hold capacitor 200 and the switch transistor 300 constitute a reference signal circuit that outputs a reference signal to the non-inverting input terminal (+). A reference signal source that supplies a reference signal may be provided inside the solid-state imaging device 1. Alternatively, the reference signal may be supplied from the outside of the solid-state imaging device 1. Note that the differential amplifier circuit 30 shown in FIG.

  By turning off the switch transistor 300, the hold capacitor 200 holds the reference signal Vref supplied from the reference signal source. The switch transistor 300 is connected to the control electrode of the hold capacitor 200, and charges and discharges the charge according to the reference signal Vref held by the hold capacitor 200 according to the control pulse P1 output from the peripheral circuit control unit 71 (for example, , See Patent Document 1). More specifically, when the switch transistor 300 is turned on before the signal reading operation from the pixel 10, the reference signal Vref is output to the non-inverting input terminal (+) of the differential amplifier circuit 30. At the same time, the hold capacitor 200 is charged with a charge corresponding to the reference signal Vref. When the charge according to the reference signal Vref is charged in the hold capacitor 200, the reference signal Vref for signal reading operation from the pixel 10 is output from the hold capacitor 200 even when the switch transistor 300 is turned off. . Therefore, by turning off the switch transistor 300, noise caused by the reference signal source can be reduced.

  A plurality of peripheral well contacts 43 that connect the peripheral well region 100 and the peripheral ground wiring 50 are disposed on the peripheral well region 100. The peripheral ground wiring 50 is electrically connected to an external ground potential outside the solid-state imaging device 1 via the external ground terminal 60. On the other hand, a plurality of pixel well contacts 42 connecting the pixel well region 101 and the pixel ground wiring are disposed on the pixel well region 101. Further, the pixel ground wiring 51 is electrically connected to the peripheral ground wiring 50 via the ground connection portion 52. The ground terminals (hereinafter simply referred to as “the ground terminal of the pixel 10”) of the photoelectric conversion unit and the amplification unit that constitute each pixel 10 are electrically connected to the pixel ground wiring 51 through the pixel well contact 42. The pixel well region 101 constitutes the ground terminal of the pixel 10. Note that the pixel well contacts 42 and the peripheral well contacts 43 are not necessarily arranged regularly as shown in the drawing.

  FIG. 2 is a diagram schematically showing a planar structure of the hold capacitor 200 according to the first embodiment of the present invention. FIG. 3 is a diagram schematically showing a cross-sectional structure of the hold capacitor 200 according to the first embodiment of the present invention. FIG. 3 shows a cross-sectional structure taken along the one-dot broken line L-L ′ in FIG. 2. The hold capacitor 200 includes a control electrode 54 and a ground electrode 53 as shown in FIG. A reference signal Vref is supplied to the control electrode 54 from a reference signal source. The ground electrode 53 is connected to the pixel ground wiring 51 through the first contact 48. Further, the control electrode 54 is connected to the switch transistor 300 via the second contact 47 and the wiring 58.

  The ground electrode 53 and the control electrode 54 are formed of a conductive material. Further, the first contact 48 only needs to be capable of electrically connecting the ground electrode 53 of the hold capacitor 200 to the pixel ground wiring 51. The first contact 48 and the pixel ground wiring 51 may be connected via another wiring. In the present embodiment, the ground electrode 53 and the first contact 48 are formed of different materials. The end of the ground electrode 53 can be defined by an interface of different materials. In general, the ground electrode 53 and the first contact 48 are formed by different processes. For example, the ground electrode 53 is formed by patterning a metal layer. On the other hand, the first contact 48 is formed by embedding a metal in a through hole formed in the insulating layer. As a modification, the ground electrode 53 and the first contact 48 may be formed of the same material. For example, when the wiring is formed by the dual damascene method, the ground electrode 53 and the first contact 48 can be formed of the same material. In this case, a conductive material different from them, for example, a barrier metal may be disposed between them. In the present specification, a plurality of processes for forming grooves having different widths in the dual damascene method used when forming wirings are treated as different processes. Alternatively, the ground electrode 53 and the pixel ground wiring 51 may be integrated in the same wiring layer. Thereby, the first contact 48 can be omitted. In this case, it is formed simultaneously with the ground electrode 53 and the pixel ground wiring 51. The end of the ground electrode 53 is defined by projecting the end of the opposing control electrode 54 in a direction perpendicular to the surface of the semiconductor substrate. Further, the end of the pixel ground wiring 51 is defined by projecting the pixel well region 101 in a direction perpendicular to the surface of the semiconductor substrate. In addition, by arranging the hold capacitor 200 in a well region separated from the peripheral well region 100, the separated well region can be used as the ground electrode 53. That is, the ground electrode 53 may be formed of a semiconductor region having a predetermined impurity concentration.

  The second contact 47 only needs to be able to electrically connect the control electrode 54 of the hold capacitor 200 to the wiring 58 to which the reference signal Vref is supplied. Here, the second contact 47 can be omitted by being integrated with the wiring 58 to which the reference signal Vref is supplied and the control electrode 54.

  FIG. 4 is a diagram schematically showing a planar structure of the ground connection portion 52 according to the first embodiment of the present invention. As shown in FIG. 4, the ground connection portion 52 of the present embodiment is characterized by having an intermediate wiring 63 having a layout meandering in the column direction and the row direction. The column direction is a direction along a column formed by a plurality of pixels 10. The row direction is a direction that intersects a column formed by a plurality of pixels 10. Usually, such a wiring layout is not performed because the layout area is increased. However, in the present embodiment, by laying out the intermediate wiring 63 in this way, as described later, the peripheral ground wiring 50 and the pixel ground wiring 51 are connected with high resistance, and magnetic noise generated in the ground wiring is reduced. So that it can be reduced. Hereinafter, the effects obtained by this embodiment will be described. Note that when the solid-state imaging device 1 is applied to an imaging system such as a camera, examples of the magnetic noise source affecting the ground wiring include a magnetic field generated by a motor for driving a camera lens.

  FIG. 5 is a diagram schematically showing a cross-sectional structure of a package including the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 5 shows a configuration in which the solid-state imaging device 1 shown in FIG. 1 is supported by a package 80. In FIG. 5, the peripheral ground wiring 50, the pixel ground wiring 51, and the ground connection portion 52 shown in FIG. 1 are shown as a single ground wiring 55. The ground wiring 55 is electrically connected to an external ground wiring 90 that is an inner layer wiring of the package via an external ground terminal 60, a wire bonding 61, and a through via 62 of the package. Here, the wire bonding 61 connects the external ground terminal 60 and the through via 62. In such a package configuration, the ground wiring 55 and the external ground wiring 90 form a loop (hereinafter referred to as “ground loop”).

  FIG. 6 is a diagram schematically showing a ground loop equivalent circuit and a ground potential distribution in the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 6 shows an equivalent circuit for one column of the ground loop shown in FIG. In the presence of a magnetic field, when the magnetic flux B passes through the ground loop, an induced electromotive force V corresponding to the time change of the magnetic flux B is generated in the ground loop. This follows Faraday's law, and the relationship between the induced electromotive force V and the change ΔB of the magnetic flux B in the minute time Δt is expressed as V = −ΔB / Δt.

  In addition, when the magnetic flux B faces 180 ° in the reverse direction, the directions of the electromotive force and the current are reversed. Further, even when the magnetic flux B is inclined in an oblique direction with respect to the loop plane of the ground wiring, an electromotive force is generated due to a component of the magnetic flux B in a direction perpendicular to the loop surface. Due to this electromotive force, a voltage distribution is generated in the ground loop, which is originally at the same potential, and the signal of the pixel 10 is swung by the distribution of the ground potential. In the output image of the solid-state imaging device 1, it appears as pattern noise in the image (magnetic noise). The external ground wiring 90 does not necessarily have to be inside the package. Even when the solid-state imaging device 1 is connected to the PCB substrate, an electromotive force is generated when the ground loop is formed as described above. Further, the ground loop does not necessarily have to be an electrically closed loop. For example, even when the external ground wiring 90 is partially disconnected, the ground wiring 55 of the solid-state imaging device 1 is used. An induced electromotive force V may be generated between both ends of the.

  The correspondence between the configuration of the solid-state imaging device 1 shown in FIG. 1 and the equivalent circuit of the ground loop shown in FIG. 6 will be described below. First, the points A to C, O to Q, S, and S ′ on the ground loop shown in FIG. 1 will be described. The first contact 48 shown in FIG. 3 connects the ground electrode 53 of the hold capacitor 200 to the pixel ground wiring 51 in the pixel well region 101 as described above. A contact point between the first contact 48 and the ground electrode 53 is a point A. Note that the point A shown in FIG. 1 is not strictly on the ground loop, but is located on the first contact 48 that connects the ground electrode 53 of the hold capacitor 200 to the ground loop. However, in the present embodiment, since the pixel ground wiring 51 to the hold capacitor 200 are connected by a low resistance wiring, it can be considered to be almost equipotential. Therefore, in FIG. 6, point A is shown on the ground loop.

  Next, in the pixel well region 101, among the plurality of pixel well contacts 42 connected to the pixel ground wiring 51, the pixel well contact 42 having the smallest electrical resistance value up to the point A is defined as a point B. Similarly, in the peripheral well region 100, the peripheral well contact 43 disposed closest to the ground electrode 53 among the plurality of peripheral well contacts 43 connected to the peripheral ground wiring 50 is defined as a point C. In this embodiment, when the electrical resistance values from each of the plurality of peripheral well contacts 43 to the ground electrode 53 are compared, the electrical resistance value from the peripheral well contact 43 disposed at the point C to the ground electrode 53 is the smallest. It is. FIG. 1 shows points A, B, and C.

  Next, among the peripheral well contacts 43 connected to the ground terminal of the differential amplifier circuit 30, the peripheral well contact 43 having the smallest electrical resistance value up to the point A is set as a point Q. The ground terminal of the differential amplifier circuit 30 is, for example, a source region of a MOS transistor included in the differential amplifier circuit 30. The ground terminal of the differential amplifier circuit 30 is connected to the peripheral ground wiring. A pixel well contact 42 connected to the ground terminal of the pixel 10 in the same column as the differential amplifier circuit 30 and farthest from the differential amplifier circuit 30 is defined as a point S. Similarly, a pixel well contact 42 connected to the ground terminal of the pixel 10 in the same column as the differential amplifier circuit 30 and closest to the differential amplifier circuit 30 is defined as a point S ′. When there are a plurality of points S or S ′, the peripheral well contact 43 having the minimum electric resistance value from the ground terminal of the pixel 10 is represented as a point S or a point S ′. FIG. 1 shows points Q, S, and S ′.

  Next, of the external ground terminals 60 that connect the peripheral ground wiring 50 to the reference potential outside the solid-state imaging device 1, the one connected to the ground terminal of the differential amplifier circuit 30 without passing through the pixel ground wiring 51. The external ground terminal 60 is designated as point P. The external ground terminal 60 connected to the ground terminal of the differential amplifier circuit 30 via the pixel ground wiring 51 is defined as a point O. FIG. 1 shows points P and O.

  Next, the electrical resistance value between points in the equivalent circuit of the ground loop shown in FIG. 6 will be described with reference to FIGS. In FIG. 1 and FIG. 6, the same symbol represents the same thing. First, the electrical resistance between points AP will be described. The electric resistance value between points A and C is R2. In the present embodiment, since the electrical resistance value of the intermediate wiring 63 is large, it can be considered that R2 is substantially equal to the electrical resistance value of the intermediate wiring 63. In addition, the electric resistance values between the points CP and CQ are sufficiently smaller than the electric resistance value R2 and can be ignored on the equivalent circuit. Therefore, the electric resistance value between the points A and P is approximated to R2. Similarly, the electrical resistance value from the point A to the peripheral ground wiring 50 is approximated to R2. Furthermore, the electric resistance value from the point A to any peripheral well contact 43 connected to the peripheral ground wiring 50 is approximated to R2.

  Next, the electrical resistance between points A and S will be described. The electric resistance value between the points A and B is R1, and the electric resistance value between the points S 'and S is R11. At this time, since the point B and the point S ′ are arranged in the vicinity of each other, the electrical resistance value between the points BS ′ and S ′ is sufficiently smaller than the electrical resistance value R11 between the points S ′ and S, and thus an equivalent circuit. The above is negligible. Therefore, the electric resistance value between the points A and S is approximated to R11 + R1.

  Next, the electrical resistance between the points S-O will be described. Since the point S-O is equivalent in circuit to the point S′-P, the point S-O has a point A-S ′ (electric resistance value R1) and a point A-P ( It can be regarded as equivalent to a series connection of electrical resistance values R2). Therefore, the electrical resistance value between the points S-O is approximated as R1 + R2.

  Since the pixel ground wiring 51 has a uniform electrical resistance in the plane, the electrical resistance value of the ground wiring is generally proportional to the length of the wiring. Therefore, in general, R11> R1. R1 actually includes the electrical resistance value of the wiring from the ground electrode 53 of the hold capacitor 200 to the pixel ground wiring 51, but is sufficiently small as compared to R11 and R1, and can be ignored on the equivalent circuit. .

  In consideration of the above approximation, the electric resistance values R1, R11 + R1, and R2 are, on the equivalent circuit, the electric resistance value between the points A and S ′, the electric resistance value between the points A and S, and between the points A and Q, respectively. It can be regarded as an electrical resistance value. That is, the electric resistance values R1 and R11 + R1 are the minimum values of the electric resistance values from the pixel well contact 42 to the first contact 48 connected to the ground terminals of the plurality of pixels 10 in the same column as the differential amplifier circuit 30, respectively. It is approximated as the maximum value. The electric resistance values R1 and R11 + R1 are resistance values of electric paths on the pixel ground wiring 51. The electrical resistance value R2 is approximated as the minimum electrical resistance value from the peripheral well contact 43 to the first contact 48 connected to the peripheral ground wiring 50, that is, the electrical resistance value of the ground connection portion 52.

In the present embodiment, the relationship of R1 <R2 is satisfied. This effect will be described. The relationship between the electrical resistance value between each point and the induced electromotive force in the equivalent circuit of the ground loop shown in FIG. 6 will be described. As described above, when the magnetic flux B passes through the ground loop, an induced electromotive force V corresponding to the time change of the magnetic flux B is generated in the ground loop. FIG. 6 shows the induced voltage difference V1 between points A, S, the induced voltage difference V2 between points AP, and the induced voltage difference V3 between points S-O among the induced electromotive forces V generated in the ground loop. Each is shown. These induced voltage differences V1 to V3 are expressed by the following equations (1) to (3) because the induced electromotive force V is divided by the electric resistance value in each section.
V1 = V × (R11 + R1) / (R11 + 2 × R1 + 2 × R2) (1)
V2 = V × R2 / (R11 + 2 × R1 + 2 × R2) (2)
V3 = V × (R2 + R1) / (R11 + 2 × R1 + 2 × R2) (3)

Here, the signal from the pixel 10 input to the inverting input terminal (−) of the differential amplifier circuit 30 includes the induced voltage difference V1 + V2 at the point S where the ground terminal of the pixel 10 is connected as magnetic noise. . On the other hand, the reference signal input to the non-inverting input terminal (+) of the differential amplifier circuit 30 includes the induced voltage difference V2 at the point A to which the ground electrode 53 of the hold capacitor 200 is connected as magnetic noise. Accordingly, the magnetic noise output Vout of the differential amplifier circuit 30 includes an induced voltage difference V1 between points A and S as shown in the following equation (4).
Vout = (V1 + V2) − (V2)
= V1 (4)

Therefore, the above equation (1) is
V1 = k × V (1 ′)
However, k = (R11 + R1) / (R11 + 2 × R1 + 2 × R2) <1
In other words, it can be seen that the magnetic noise output Vout = k × V can be reduced by adjusting the electric resistance values R1, R11, and R2 to reduce the proportionality constant k. Therefore, in the present embodiment, as shown in FIG. 4, by laying out the intermediate wiring 63 in the column direction and the row direction, the electrical resistance value R2 of the ground connection portion 52 is satisfied so that the following expression (5) is satisfied. Has increased.
R11 + R1 <R2 (5)

  Thereby, for example, when R11 + R1 <R2, V1 <V2 and V1 <V3 are obtained from the above equations (1) to (3), so that the magnetic noise output Vout (= V1) can be reduced. .

In the equivalent circuit shown in FIG. 6, as the pixel 10 connected to the inverting input terminal (−) of the differential amplifier circuit 30, the pixel 10 (electrical resistance value) at the farthest position in the same column as the differential amplifier circuit 30 R11 + R1) is represented, but another pixel 10 may be represented. For example, as the pixel 10 connected to the inverting input terminal (−), the pixel 10 (electric resistance value R <b> 1) located at the closest position in the same column as the differential amplifier circuit 30 may be represented. In this case, the following equation (6) is applied instead of the above equation (5).
R1 <R2 (6)

  Even in this case, for example, when R1 <R2, V1 <V2 and V1 <V3 are similarly obtained, so that the magnetic noise output Vout (= V1) can be reduced.

  As described above, the present embodiment is characterized in that the ground electrode 53 of the hold capacitor 200 is connected to the pixel ground wiring 51 via the first contact 48. The second feature is that the electrical resistance value R2 of the ground connection portion 52 that connects the pixel ground wiring 51 and the peripheral ground wiring 50 is set to be large so as to satisfy the above equation (6). Thereby, magnetic noise generated in the ground wiring can be reduced.

Here, let us consider a case where the first feature of the present invention described above is not satisfied. For example, this is a case where the ground electrode 53 of the hold capacitor 200 is connected to the peripheral ground wiring 50 (point Q) instead of the pixel ground wiring 51 (point A). At this time, the magnetic noise output Vout of the differential amplifier circuit 30 includes an induced voltage difference V1 + V2 between points SQ in the equivalent circuit of FIG. 6, as shown in the following equation (7).
Vout = (V1 + V2) (7)
= V × (R11 + R1 + R2) / (R11 + 2 × R1 + 2 × R2)

  In this case, since the electric resistance values R1, R11, and R2 are included in both the numerator and denominator of the above equation (7), the magnetic noise output Vout is reduced regardless of how the electric resistance values R1, R11, and R2 are adjusted. I can't do it.

  Next, consider a case where the above-described second feature of the present invention is not satisfied. That is, this is a case where the electrical resistance value R2 of the ground connection portion 52 does not satisfy the above formula (5) or (6) and is, for example, R11 + R1 >> R2. At this time, from (1) to (3), V1> V3 >> V2-0. Therefore, even in this case, the magnetic noise output Vout cannot be reduced.

  As described above, the present embodiment includes a readout circuit (differential amplifier circuit) that is arranged in the peripheral well region in which the peripheral ground wiring is arranged and reads signals from pixels in the same column with reference to the reference signal. ing. In addition, a first electrode (ground electrode) to which a ground voltage is supplied from the pixel ground wiring and a second electrode (control electrode) disposed to face the first electrode are provided, and a reference signal is output to the readout circuit. A reference signal circuit (hold capacitor) is provided. Further, the minimum value R2 of the electrical resistance value from the pixel ground wiring to the peripheral ground wiring is increased so as to satisfy the above formula (6). Thereby, it is possible to obtain a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an imaging system capable of reducing magnetic noise generated in the ground wiring without newly adding a circuit for noise reduction.

  In FIG. 4, the ground connection portion 52 is configured by one intermediate wiring 63, but may be configured by a plurality of wirings. Further, the ground connection portion 52 only needs to be electrically connected to the peripheral ground wiring 50 and the pixel ground wiring 51. In addition, although the example in which the peripheral ground wiring 50 and the pixel ground wiring 51 are each disposed in one layer is shown, they may be disposed in a plurality of layers. Also, the peripheral ground wiring 50 and the pixel ground wiring 51 may have any shape.

  FIG. 1 shows a layout in which the peripheral well region 100 includes a first peripheral well region provided on one side of the pixel well region 101 and a second peripheral well region provided on the other side. It was. However, it is not necessarily limited to such a configuration. For example, even when the first peripheral well region and the second peripheral well region are connected to each other by bypassing the pixel well region 101, or when the peripheral well region 100 is composed only of the first peripheral well region, Similar effects can be obtained.

[Second Embodiment]
A solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 7 is a diagram schematically showing a planar structure of the ground connection portion 52b according to the second embodiment of the present invention. This embodiment is different from the first embodiment in that the ground connection portion 52b is electrically connected to an external ground potential outside the solid-state imaging device 1 via the external ground terminal 60. . Others are the same as those in the first embodiment, and thus the description thereof is omitted.

  In the ground connection part 52b shown in FIG. 7, the intermediate wiring 63 described in the first embodiment shown in FIG. 4 is electrically connected to an external ground potential outside the solid-state imaging device 1 via the external ground terminal 60. Is. Even in this case, as in the first embodiment, the peripheral ground wiring 50 and the pixel ground wiring 51 are connected by a high resistance electric resistance value R2 corresponding to the distance of the intermediate wiring 63. Therefore, also in this embodiment, since the above equation (6) is satisfied, magnetic noise generated in the ground wiring can be reduced.

  The intermediate wiring 63 may be a plurality of wirings. Further, as shown in FIG. 7, the intermediate wiring 63 may be connected to a connection line that connects the peripheral ground wiring 50 and the external ground terminal 60, or may be directly connected to the external ground terminal 60. . This embodiment can also be combined with the first embodiment.

[Third Embodiment]
A solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 8 is a diagram schematically showing a planar structure of the ground connection portion 52c according to the third embodiment of the present invention. This embodiment is different from the first embodiment in that the intermediate wiring 64 passes through a well region 102 that is different from both the pixel well region 101 and the peripheral well region 100. Others are the same as those in the first embodiment, and thus the description thereof is omitted.

  The ground connection portion 52c shown in FIG. 8 has a configuration in which the intermediate wiring 64 passes through a well region 102 different from the pixel well region 101 and the peripheral well region 100 shown in FIG. The well region 102 is not connected to the pixel well region 101 and the peripheral well region 100 via the well. The well region 102 is connected to the peripheral ground wiring 50 and the pixel ground wiring 51 by a well contact 44, respectively. Note that the well region 102 and the peripheral ground wiring 50 and the well region 102 and the pixel ground wiring 51 are not necessarily connected by a single well contact 44 as shown in FIG. . For example, a plurality of well contacts 44 may be connected.

  With the above configuration, the peripheral well region 100 and the pixel well region 101 are connected via the high-resistance well region 102. Thereby, also in this embodiment, since the above equation (6) is satisfied as in the first embodiment, magnetic noise generated in the ground wiring can be reduced. A plurality of well regions 102 may be provided as long as the above conditions are satisfied. This embodiment can also be combined with the first and second embodiments.

[Fourth Embodiment]
The solid-state imaging device according to the present embodiment will be described with reference to FIG. FIG. 9 is a diagram schematically showing a planar structure of the ground connection portion 52d according to the fourth embodiment of the present invention. This embodiment is different from the first embodiment in that the intermediate wiring 64 electrically connects different wiring layers via the well contact 45. Others are the same as those in the first embodiment, and thus the description thereof is omitted.

  The intermediate wiring 64 shown in FIG. 9 passes through a well contact 45 arranged between the peripheral ground wiring 50 and the pixel ground wiring 51 as shown in FIG. At this time, the peripheral ground wiring 50 and the pixel ground wiring 51 are arranged in different layers. Thereby, the peripheral ground wiring 50 and the pixel ground wiring 51 are connected via the high-resistance well contact 45. With the above configuration, in the present embodiment as well, the above equation (6) is satisfied as in the first embodiment, so that magnetic noise generated in the ground wiring can be reduced. This embodiment can also be combined with the first to third embodiments.

[Fifth Embodiment]
A solid-state imaging device according to this embodiment will be described with reference to FIGS. FIG. 10 is a diagram schematically showing a configuration of a solid-state imaging device 1b according to the fifth embodiment of the present invention. In the first embodiment, the case where the readout circuit includes the differential amplifier circuit 30 that amplifies the signal from the pixel 10 with reference to the reference signal has been described. On the other hand, in this embodiment, the case where the readout circuit includes an AD converter (analog / digital converter) 31 that performs A / D conversion (analog / digital conversion) on the signal from the pixel 10 with reference to the reference signal will be described. To do.

  The solid-state imaging device 1b according to the present embodiment illustrated in FIG. 10 has a configuration in which the differential amplifier circuit 30 according to the first embodiment illustrated in FIG. The AD converter 31 is arranged in the peripheral well region 100 and reads out signals from the pixels 10 in the same column with reference to the reference signal. More specifically, the AD converter 31 compares the signal from the pixel 10 with the RAMP signal output from the ramp signal generation circuit 201, thereby converting the signal from the pixel 10 that is an analog signal into a digital signal. D-convert. Note that the AD converter 31 illustrated in FIG. 10 is conceptually illustrated with the peripheral circuits omitted.

  The ramp signal generation circuit 201 is disposed in the third well region 103 in which the ground wiring 56 is disposed. Here, the ground wiring 56 in the third well region 103 is connected to the pixel ground wiring 51 with a low resistance. In other words, the third well region 103 can be regarded as sharing the pixel ground wiring 51 with the pixel well region 101. The ground terminal of the ramp signal generation circuit 201 is connected to the ground wiring 56 connected to the pixel ground wiring 51 through the well contact 46. Therefore, the RAMP signal output from the ramp signal generation circuit 201 is generated using the pixel ground wiring 51 as a reference potential. The AD converter 31 and the ramp signal generation circuit 201 are controlled by the peripheral circuit control unit 71.

  Here, when the solid-state imaging device 1 of the first embodiment shown in FIG. 1 and the solid-state imaging device 1b of the present embodiment shown in FIG. 10 are compared, the well contact 46 of FIG. Thus, it can be seen that the method in the first embodiment can be applied as it is. Therefore, in the following description of the present embodiment, the well contact 46 is referred to as a first contact 46, and a contact between the first contact 46 and the pixel ground wiring 51 is a point A. Note that there may be a plurality of first contacts 46. In this case, point A is representative of any of the plurality of first contacts 46.

  FIG. 11 is a diagram schematically showing an equivalent circuit of the ground loop and the ground potential distribution in the solid-state imaging device 1b according to the fifth embodiment of the present invention. The equivalent circuit of the ground loop according to the present embodiment shown in FIG. 11 is the first circuit shown in FIG. 6 except that the differential amplifier circuit 30 is an AD converter 31 and the hold capacitor 200 is a ramp signal generation circuit 201. This is the same as the equivalent circuit of the ground loop according to the embodiment. Therefore, the induced voltage differences V1 to V3 between the points on the ground loop are expressed by the above formulas (1) to (3) as in the first embodiment.

  As described above, this embodiment also has a first feature in that the ground terminal of the ramp signal generation circuit 201 is connected to the pixel ground wiring 51 through the first contact 46. The second feature is that the electrical resistance value R2 of the ground connection portion 52 that connects the pixel ground wiring 51 and the peripheral ground wiring 50 is set to be large so as to satisfy the above equation (6). Thereby, magnetic noise generated in the ground wiring can be reduced.

  FIG. 12 is a diagram schematically showing magnetic noise included in the input to the AD converter 31 according to the fifth embodiment of the present invention. The AD converter 31 of this embodiment compares the signal from the pixel 10 with a reference signal and performs A / D conversion. Here, the signal from the pixel 10 includes the induced voltage difference V1 + V2 at the point S connected to the ground terminal of the pixel 10 as magnetic noise. On the other hand, the reference signal includes the induced voltage difference V2 at the point A connected to the ground terminal of the ramp signal generation circuit 201 as magnetic noise. Therefore, the output of the AD converter 31 includes the induced voltage difference V1 between points A and S shown in the above equation (4), which is the difference between them, as the magnetic noise output Vout. In the following description, it is assumed that the magnetic flux B changes sinusoidally with time.

  FIG. 12A shows an ideal signal from the pixel 10 and a time-varying waveform of the RAMP signal when both the signal from the pixel 10 and the reference signal do not include magnetic noise. The AD converter 31 digitally converts the signal from the pixel 10 at time t1 when the signal from the pixel 10 matches the RAMP signal and outputs the signal as a pixel signal.

  FIG. 12B shows a time-varying waveform of the signal from the pixel 10 and the RAMP signal when magnetic noise is included only in the signal from the pixel 10. This corresponds to a case where the above first feature of the present invention is not satisfied. Specifically, this is a case where the ground terminal of the ramp signal generation circuit 201 shown in FIG. 11 is connected to the peripheral ground wiring 50 (point Q) instead of the pixel ground wiring 51 (point A). In this case, an induced voltage difference V1 + V2 is generated at the point S connected to the ground terminal of the pixel 10. On the other hand, an induced voltage is hardly generated at the point Q connected to the ground terminal of the ramp signal generation circuit 201. The AD converter 31 converts the signal from the pixel 10 at time t2 when the signal from the pixel 10 and the RAMP signal coincide with each other into a digital signal and outputs it as a pixel signal. As a result, an error corresponding to time t1-t2 occurs with respect to the original output signal.

  FIG. 12C shows time-varying waveforms of the signal from the pixel 10 and the RAMP signal when both the signal from the pixel 10 and the reference signal contain magnetic noise. This corresponds to the case where the first feature of the present invention described above is satisfied. That is, this is a case where the ground terminal of the ramp signal generation circuit 201 shown in FIG. 11 is connected to the pixel ground wiring 51 (point A). In FIG. 12C, an induced voltage difference V1 + V2 is generated at the point S connected to the ground terminal of the pixel 10. On the other hand, an induced voltage difference V2 is generated at a point A connected to the ground terminal of the ramp signal generation circuit 201. The AD converter 31 converts the signal from the pixel 10 at time t3 when the signal from the pixel 10 matches the RAMP signal into a digital signal and outputs it as a pixel signal. As a result, although an error corresponding to the time t1-t3 occurs with respect to the original output signal, since t1-t3 <t1-t2, magnetic noise generated in the ground wiring can be reduced.

  As a factor that causes such an error of t1 to t3, there is an induced voltage difference V1 generated by the electric resistance value R11 + R1. Here, when the induced voltage difference V1 is sufficiently negligible, that is, when the above-described second feature of the present invention is further satisfied, substantially the same sine wave is included in both the signal from the pixel 10 and the RAMP signal. . Under this condition, the error corresponding to the time t1-t3 of the signal from the pixel 10 and the RAMP signal is substantially the same as the ideal signal shown in FIG. The signal is a signal substantially corresponding to time t1.

  As described above, the present embodiment includes a readout circuit (AD converter) that is arranged in the peripheral well region where the peripheral ground wiring is arranged and reads signals from pixels in the same column with reference to the reference signal. . The ground terminal is electrically connected to the pixel ground wiring through the first contact, and includes a reference signal circuit (ramp signal generation circuit) that outputs a reference signal to the readout circuit. Further, the minimum value R2 of the electrical resistance value from the pixel ground wiring to the peripheral ground wiring is increased so as to satisfy the above formula (6). Thereby, it is possible to obtain a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an imaging system capable of reducing magnetic noise generated in the ground wiring without newly adding a circuit for noise reduction. Note that this embodiment can be combined with the second to fourth embodiments.

  Note that the ramp signal generation circuit 201 of this embodiment is configured in the third well region 103, but the third well region 103 is configured in the pixel well region 101 and the peripheral well region 100. May be. However, in this case, it is necessary that the third well region 103 and the peripheral well region 100 configured by the ramp signal generation circuit 201 are not connected by a common well, that is, be an independent well region. At this time, the third well region 103 serving as the external ground of the ramp signal generation circuit 201 is connected by extending a low-resistance wiring from the pixel ground wiring 51.

[Sixth Embodiment]
A solid-state imaging device according to this embodiment will be described with reference to FIGS. FIG. 13 is a diagram schematically showing a configuration of a solid-state imaging device 1c according to the sixth embodiment of the present invention. In the present embodiment, a case where the pixel well region 101 and the peripheral well region 100 are arranged on different semiconductor substrates will be described.

  A solid-state imaging device 1c of this embodiment shown in FIG. 13 is an example of a stacked solid-state imaging device including a semiconductor substrate 1000 and a semiconductor substrate 2000. The semiconductor substrate 1000 and the semiconductor substrate 2000 are connected by at least the connection electrode 501. In the present embodiment, the semiconductor substrate 1000 and the semiconductor substrate 2000 are further connected by the connection electrodes 500 and 502. The semiconductor substrate 1000 includes components related to the pixel 10 such as the pixel well region 101, the vertical scanning circuit 70, and the pixel ground wiring 51. On the other hand, components related to the peripheral circuit such as the peripheral well region 100, the peripheral circuit control unit 71, the differential amplifier circuit 30, the peripheral ground wiring 50, and the hold capacitor 200 are included in the semiconductor substrate 2000.

  The connection electrode 500 connects the pixel ground wiring 51 and the peripheral ground wiring 50. The connection electrode 501 connects the hold capacitor 200 and the pixel ground wiring 51. The connection electrode 502 connects the vertical signal line 20 and the inverting input terminal (−) of the differential amplifier circuit 30. The connection electrode 500 corresponds to the ground connection portion 52 in the first embodiment in terms of an equivalent circuit, and the connection electrode 501 corresponds to the first contact 48 in the first embodiment in terms of an equivalent circuit. Note that the pixel ground wiring 51 and the peripheral ground wiring 50 are configured to be connected by a plurality of connection electrodes 500 in order to reduce the wiring impedance of the power supply, and in this embodiment, are connected at two locations. The peripheral ground wiring 50 is electrically connected to an external ground potential outside the solid-state imaging device 1 c via the external ground terminal 60. Others are the same as those in the first embodiment, and thus the description thereof is omitted.

  FIG. 14 is a diagram schematically showing a cross-sectional structure of a solid-state imaging device 1c according to the sixth embodiment of the present invention. The semiconductor substrate 1000 and the semiconductor substrate 2000 are connected by connection electrodes 500, 501, and 502 with the insulator 600 interposed therebetween. In FIG. 14, the connection electrodes 500, 501, and 502 are illustrated together, but actually, the connection electrodes 500 are provided at two locations, and the connection electrodes 501 and 502 are provided corresponding to the pixels to be arranged. Note that the insulator 600 may be a magnetic shield (a material having a high magnetic permeability) other than the periphery of the connection electrodes 500, 501, and 502.

FIG. 15 is a diagram schematically showing an equivalent circuit of a ground loop and a ground potential distribution in the solid-state imaging device 1c according to the sixth embodiment of the present invention. Compared to FIG. 6, an example in which a ground loop is formed in the semiconductor substrate 1000 and the semiconductor substrate 2000 via a point U and a point T is shown. Similarly to the first embodiment, the induced voltage differences V1 to V3 are expressed by the following expressions (8) to (10).
V1 = V × (R11 + R1) / (R11 + 2 × R1 + 2 × R2) (8)
V2 = V × R2 / (R11 + 2 × R1 + 2 × R2) (9)
V3 = V × (R2 + R1) / (R11 + 2 × R1 + 2 × R2) (10)

  Even in the case of the present embodiment, the values of the electric resistance values R1, R11, and R2 are set so as to satisfy the expressions (5) and (6) described above. The resistance value R1 of the electrical path from one of the plurality of pixel well contacts 42 to the ground electrode 53 and the electrical path from the peripheral well contact 43 (point C) disposed closest to the ground electrode 53 to the ground electrode 53 The resistance value R2 satisfies the relationship R1 <R2. According to such a configuration, an effect similar to that of the first embodiment can be obtained. In other words, since the ground electrode 53 of the hold capacitor 200 is connected to the pixel ground wiring 51, magnetic noise generated in the ground wiring can be reduced.

  As described above, in the present embodiment, since the area related to the peripheral circuit can be reduced by using the stacked solid-state imaging device by the connection electrodes, the chip size of the solid-state imaging device can be reduced as compared with the first embodiment. Can be suppressed.

  In addition, the electrical resistance value can be adjusted depending on the arrangement position of the connection electrodes 500 to 502 of the semiconductor substrates 1000 and 2000, and the electrical resistance values R1 and R2 can be adjusted depending on the material of the connection electrode, so that the electrical resistance value can be easily designed. it can. Therefore, the degree of freedom in designing to reduce the proportionality constant k in the above formula (1 ′) is improved, and the same effect as in the first embodiment can be obtained more effectively. Note that the configuration of this embodiment can also be applied to the fifth embodiment.

[Seventh Embodiment]
Hereinafter, the imaging system according to the present embodiment will be described with reference to FIG. FIG. 16 is a diagram illustrating a configuration of an imaging system according to the seventh embodiment of the present invention. In this embodiment, an example of an imaging system to which the configuration shown in the first to sixth embodiments is applied will be described.

  An imaging system 800 illustrated in FIG. 16 includes, for example, an optical unit 810, an imaging device 820, a recording / communication unit 840, a timing control unit 850, a system control unit 860, and a playback / display unit 870. Here, the imaging device 820 includes the solid-state imaging device 1 (or 1b, 1c, the same applies hereinafter) and a video signal processing unit 830. The solid-state imaging device 1 includes the photoelectric devices described in the first to sixth embodiments. A conversion device is used.

  An optical unit 810 that is an optical system such as a lens forms an image of a subject by forming light from the subject on a pixel array in which a plurality of pixels of the solid-state imaging device 1 are two-dimensionally arranged. The solid-state imaging device 1 outputs a signal corresponding to the light imaged on the pixel array at a timing based on the signal from the timing control unit 850. The signal output from the solid-state imaging device 1 is input to the video signal processing unit 830, and the video signal processing unit 830 performs signal processing according to a method determined by a program or the like. The signal obtained by the processing in the video signal processing unit 830 is sent to the recording / communication unit 840 as image data. The recording / communication unit 840 sends a signal for forming an image to the reproduction / display unit 870 and causes the reproduction / display unit 870 to reproduce / display a moving image or a still image. The recording / communication unit 840 receives a signal from the video signal processing unit 830 and communicates with the system control unit 860, and also records an operation for recording a signal for forming an image on a recording medium (not shown). Do.

  The system control unit 860 comprehensively controls the operation of the imaging system, and controls driving of the optical unit 810, the timing control unit 850, the recording / communication unit 840, and the reproduction / display unit 870. The optical unit 810 is driven by a motor (not shown), for example, and performs camera shake correction and focus position adjustment. In the first to sixth embodiments, examples of the magnetic noise source that affects the ground wiring include a magnetic field generated by the motor.

  Further, the system control unit 860 includes a storage device (not shown) that is a recording medium, for example, and a program necessary for controlling the operation of the imaging system is recorded therein. Further, the system control unit 860 supplies a signal for switching the drive mode in accordance with, for example, a user operation in the imaging system. Specific examples include a change in a line to be read out and a line to be reset, a change in an angle of view associated with electronic zoom, and a shift in angle of view associated with electronic image stabilization. The timing control unit 850 controls the drive timing of the solid-state imaging device 1 and the video signal processing unit 830 based on control by the system control unit 860.

DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor 10 ... Pixel 20 ... Vertical signal line 30 ... Differential amplifier circuit (readout circuit)
31 ... AD converter (readout circuit)
42 ... Pixel well contact 43 ... Peripheral well contact 50 ... Peripheral ground wiring 51 ... Pixel ground wiring 52 ... Ground connection 60 ... External ground terminal 70 ... Vertical scanning circuit 71 ... peripheral circuit control unit 100 ... peripheral well region 101 ... pixel well region 200 ... hold capacitor (reference signal circuit)
201 ... Ramp signal generation circuit (reference signal circuit)
300 ... Switch transistors 500, 501, 502 ... Connecting electrode 600 ... Insulator, magnetic shield 1000, 2000 ... Semiconductor substrate

Claims (18)

A semiconductor substrate including a pixel well region and a peripheral well region;
A pixel ground wiring disposed on the pixel well region;
A peripheral ground wiring disposed on the peripheral well region;
A plurality of pixel well contacts connecting the pixel ground wiring and the pixel well region;
A plurality of peripheral well contacts connecting the peripheral ground wiring and the peripheral well region;
A plurality of pixels arranged in a plurality of columns in the pixel well region, each of which outputs a pixel signal;
A readout circuit disposed in the peripheral well region and having a first input terminal for receiving the pixel signal from the plurality of pixels and a second input terminal for receiving a reference signal;
A reference signal circuit disposed in the peripheral well region, having a first electrode supplied with a ground voltage, and outputting the reference signal to the second input terminal of the readout circuit;
A wiring for connecting the first electrode of the reference signal circuit and the pixel ground wiring,
A resistance value R1 of an electrical path from one of the plurality of pixel well contacts to the first electrode, and one of the plurality of peripheral well contacts arranged closest to the first electrode to the first electrode And the resistance value R2 of the electrical path to satisfy the relationship of R1 <R2.
A solid-state imaging device. Satisfying the relationship of R1 <R2 for each of the plurality of pixel well contacts;
The solid-state imaging device according to claim 1. The readout circuit includes a differential amplifier circuit that amplifies a signal from the pixel with reference to the reference signal,
The reference signal circuit includes a capacitor configured by the first electrode and a second electrode that is disposed to face the first electrode and is connected to the second input terminal of the readout circuit.
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. The reference signal circuit includes a switch transistor connected to the second electrode of the capacitor;
Holding the reference signal in the capacitor by controlling the switch transistor;
The solid-state imaging device according to claim 3. The readout circuit includes an analog-to-digital converter that performs analog-to-digital conversion on a signal from the pixel with reference to the reference signal,
The reference signal circuit includes a ramp signal generation circuit that generates a ramp signal that changes according to time as the reference signal.
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. 6. The solid-state imaging device according to claim 1, wherein the pixel ground wiring and the peripheral ground wiring are electrically connected to each other via a ground connection portion. The ground connection portion meanders in a direction along and intersecting the plurality of rows,
The solid-state imaging device according to claim 6. The ground connection portion is electrically connected to an external ground potential via an external ground terminal.
The solid-state imaging device according to claim 6 or 7, 9. The solid-state imaging device according to claim 6, wherein the ground connection portion connects different wiring layers via well contacts. 10. The ground connection portion includes a semiconductor region disposed on the semiconductor substrate.
The solid-state imaging device according to claim 6, wherein the solid-state imaging device is provided. The peripheral ground wiring and the pixel ground wiring form a loop.
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. The peripheral well region includes a first peripheral well region and a second peripheral well region,
The pixel well region is disposed between the first peripheral well region and the second peripheral well region,
The peripheral ground wiring includes a first peripheral ground wiring disposed on the first peripheral well region and a second peripheral ground wiring disposed on the second peripheral well region.
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. The readout circuit is connected to the peripheral ground wiring;
The solid-state imaging device according to claim 1, wherein The semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate,
The pixel well region is disposed on the first semiconductor substrate,
The peripheral well region is disposed on the second semiconductor substrate;
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. A semiconductor substrate including a pixel well region and a peripheral well region;
A pixel ground wiring disposed on the pixel well region;
A peripheral ground wiring disposed on the peripheral well region;
A plurality of pixel well contacts connecting the pixel ground wiring and the pixel well region;
A plurality of pixels arranged in a plurality of columns in the pixel well region, each of which outputs a pixel signal;
A readout circuit disposed in the peripheral well region and having a first input terminal for receiving the pixel signal from the plurality of pixels and a second input terminal for receiving a reference signal;
A reference signal circuit disposed in the peripheral well region, having a first electrode supplied with a ground voltage, and outputting the reference signal to the second input terminal of the readout circuit;
A wiring for connecting the first electrode of the reference signal circuit and the pixel ground wiring,
The resistance value R1 of the electrical path from one of the plurality of pixel well contacts to the first electrode and the resistance value R2 of the electrical path from the peripheral ground wiring to the first electrode have a relationship of R1 <R2. Fulfill,
A solid-state imaging device. A solid-state imaging device according to any one of claims 1 to 15,
A video signal processing unit for processing an output signal from the readout circuit;
An imaging system comprising: A solid-state imaging device according to any one of claims 1 to 15,
An optical unit that focuses light from a subject onto the solid-state imaging device;
A motor for driving the optical unit;
An imaging system comprising: Disposing a pixel array in which a plurality of pixels are two-dimensionally arranged in a row direction and a column direction in a pixel well region in which a pixel ground wiring is disposed;
Arranging a readout circuit that reads out signals from the pixels in the same column with reference to a reference signal in a peripheral well region in which peripheral ground wiring is disposed;
Electrically connecting a ground terminal of a reference signal circuit that outputs the reference signal to the readout circuit to the pixel ground wiring through a first contact, the plurality of pixels in the same column as the readout circuit; The minimum value of the electrical resistance value of the pixel ground wiring from the pixel well contact to the first contact connecting the ground terminal of the pixel to the pixel ground wiring is R1, and the ground terminal of the readout circuit is connected to the peripheral ground wiring Connecting so as to satisfy R1 <R2, where R2 is the minimum electrical resistance value from the peripheral well contact to the first contact;
A method for manufacturing a solid-state imaging device, comprising:

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