JP2017188842A - Solid state image pickup device, and image pickup system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device capable of reducing image deterioration caused by lowering of a signal amplitude.SOLUTION: This solid image pickup device has a plurality of pixels disposed so as to form a plurality of rows for putting out signals each generated by photoelectric conversion, a plurality of holding capacitors disposed correspondingly to a plurality of the rows for holding signals each output from pixels of the corresponding rows, a first wire to which a signal held by at least one of a plurality of the holding capacitors is output by capacitor division, a first amplifier for amplifying the signal input to the first wire, and a second wire which is disposed adjacent to the first wire and to which the signal amplified by the first amplifier is input.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state imaging device and an imaging system.

  In Patent Document 1, in a solid-state imaging device, signals output from pixels arranged in a plurality of columns are temporarily held in clamp capacitors arranged corresponding to the columns, and sequentially transferred to a horizontal transfer line. A configuration for forwarding is disclosed. The solid-state imaging device of Patent Document 1 controls parasitic capacitance generated in a horizontal transfer switch connected to the horizontal transfer line based on the signal level of the horizontal transfer line. More specifically, according to the technique of Patent Document 1, it is possible to effectively reduce the parasitic capacitance between the gate and the back gate of the horizontal transfer switch connected to the horizontal transfer line.

JP 2001-251562 A

  A solid-state imaging device having a large imaging area is used for a highly sensitive imaging system such as a single-lens reflex camera. Such a solid-state imaging device has a long horizontal transfer line. Therefore, the parasitic capacitance between the horizontal transfer line and the semiconductor substrate or the parasitic capacitance between the horizontal transfer line and the adjacent wiring may be increased to a level that cannot be ignored compared to the parasitic capacitance generated in the horizontal transfer switch. is there. For this reason, in the technique of Patent Document 1, there is a case where reduction of parasitic capacitance associated with the horizontal transfer line is insufficient.

  If the parasitic capacitance is not sufficiently reduced, the amplitude of the signal output from the solid-state imaging device may be reduced, and the image quality of the acquired image may be reduced. In particular, when a signal is output from a storage capacitor that holds a signal to the horizontal transfer line by capacitive division, the amplitude of the output signal may be small in a horizontal transfer line having a large parasitic capacitance. As a result, the influence of noise can be large. Therefore, in such a configuration, the problem of image quality deterioration is more remarkable.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a solid-state imaging device that can reduce image quality deterioration due to signal amplitude reduction due to parasitic capacitance.

  According to one aspect of the present invention, a plurality of pixels arranged in a plurality of columns, each of which outputs a signal generated by photoelectric conversion, are arranged corresponding to the plurality of columns, each corresponding A plurality of storage capacitors that hold the signals output from the pixels of the column to be connected; a first wiring that outputs the signals held in at least one of the plurality of storage capacitors by capacitive division; A first amplifier that amplifies the signal input to the first wiring, and a second wiring that is disposed next to the first wiring and that receives the signal amplified by the first amplifier. A solid-state imaging device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state imaging device which can reduce the image quality fall by the fall of a signal amplitude can be provided.

It is a figure which shows the example of the circuit structure of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a figure which shows the example of the circuit structure of the pixel which concerns on 1st Embodiment. FIG. 3 is an equivalent circuit diagram of a horizontal transfer unit according to the first embodiment and a comparative example. It is a figure which shows the example of the signal waveform in the horizontal transfer line which concerns on 1st Embodiment and a comparative example. It is a figure which shows arrangement | positioning of the horizontal transfer line which concerns on 1st Embodiment, a shield line, and an electroconductive member. It is an equivalent circuit diagram of the horizontal transfer unit according to the second embodiment. FIG. 10 is an equivalent circuit diagram of a horizontal transfer unit according to the third embodiment. It is a figure which shows arrangement | positioning of the horizontal transfer line which concerns on 4th Embodiment, a shield line, and an electroconductive member. FIG. 10 is an equivalent circuit diagram of a horizontal transfer unit according to a fifth embodiment. It is a figure which shows arrangement | positioning of the horizontal transfer line and shield line which concern on 5th Embodiment. It is a block diagram of the imaging system concerning a 6th embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, portions having the same function are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a circuit configuration of a solid-state imaging device according to the first embodiment of the present invention. As shown in FIG. 1, the solid-state imaging device includes an imaging region 10, a vertical scanning circuit 20, a plurality of readout circuits 21, a horizontal scanning circuit 24, and a horizontal transfer unit 30. The imaging region 10 has a plurality of pixels 100 arranged to form a plurality of rows and a plurality of columns. The pixel 100 is an element that generates and outputs a signal corresponding to incident light by photoelectric conversion. In FIG. 1, only the pixels 100 corresponding to 3 rows and 2 columns are shown for the sake of simplicity. However, the number of the plurality of pixels 100 arranged in the row direction and the column direction is not particularly limited. For example, the solid-state imaging device may be a line sensor having one row instead of an area sensor in which the pixels 100 are arranged in a matrix as shown in FIG. In this specification, the row direction indicates the horizontal direction in the drawing, and the column direction indicates the vertical direction in the drawing.

  The imaging region 10 has a plurality of drive signal lines 23 arranged corresponding to each row and a plurality of vertical signal lines 22 arranged corresponding to each column. The drive signal lines 23 in each row are commonly connected to a plurality of pixels 100 arranged in the row direction. The vertical signal lines 22 in each column are commonly connected to a plurality of pixels 100 arranged in the column direction. The vertical scanning circuit 20 supplies drive signals RES, TX, and SEL to each pixel 100 via the drive signal line 23 of each row. In FIG. 1, the drive signal lines 23 are illustrated as being arranged one by one in each row, but a plurality of drive signal lines 23 may be arranged in each row. In the present embodiment, the drive signal line 23 in each row includes three lines: a line that supplies the drive signal RES, a line that supplies the drive signal TX, and a line that supplies the drive signal SEL. The vertical signal line 22 in each column is connected to a readout circuit 21 provided corresponding to each column. Each readout circuit 21 is a circuit that reads a signal from each pixel, performs a predetermined process, and outputs the signal to the horizontal transfer unit 30. The read circuit 21 may include an amplifier circuit, a current source circuit, a CDS (Correlated Double Sampling) circuit, and the like.

  The horizontal transfer unit 30 includes a storage capacitor 31, a horizontal scanning transistor 32, a horizontal transfer line 33, an output amplifier 34, and a shield line 35. One end of the storage capacitor 31 is connected to the output terminal of the readout circuit 21 and one main electrode (source or drain) of the horizontal scanning transistor 32. The other end of the holding capacitor 31 is grounded. The other main electrode of the horizontal scanning transistor 32 is connected to the horizontal transfer line 33. The horizontal transfer line 33 is connected to the input terminal of the output amplifier 34. Further, the horizontal transfer line 33 extends in a direction crossing the above-described column direction. The output terminal of the output amplifier 34 constitutes the output terminal of the solid-state imaging device. The output amplifier 34 can be configured by a source follower circuit using a MOS transistor, for example. In the above description, as an example, the output of the horizontal transfer unit 30 constitutes the output terminal of the solid-state image pickup device. However, the solid-state image pickup device is further provided with an additional circuit such as a signal processing circuit after the horizontal transfer unit 30. You may have. In this case, the output amplifier 34 of the horizontal transfer unit 30 functions as an output amplifier for outputting a signal to the additional circuit.

  The horizontal scanning circuit 24 sequentially outputs pulses of the drive signal PH to the gates of the horizontal scanning transistors 32 in each column, and performs horizontal scanning for sequentially turning on the horizontal scanning transistors 32. As a result, the horizontal scanning circuit 24 performs control to sequentially output the signals held in the holding capacitors 31 of each column from the solid-state imaging device via the output amplifier 34. The shield line 35 is connected to the output terminal of the output amplifier 34 and is arranged next to the horizontal transfer line 33. That is, similarly to the horizontal transfer line 33, the shield line 35 also extends in a direction crossing the above-described column direction. Here, the output amplifier 34 may be a non-inverting amplifier. In this case, the voltage of the horizontal transfer line 33 and the voltage of the shield line 35 have the same sign. For example, the input and output of the output amplifier 34 can be in phase. In this case, the voltage of the shield line 35 is in phase with the voltage of the horizontal transfer line 33.

  As described above, in this embodiment, the output amplifier 34 that is the first amplifier of the horizontal transfer unit 30 amplifies and outputs the signal transferred to the horizontal transfer line 33 that is the first wiring. The output signal is output to a subsequent circuit in the solid-state imaging device or the outside of the solid-state imaging device, and is also output to the shield line 35 as the second wiring.

  FIG. 2 is a diagram illustrating an example of a circuit configuration of the solid-state imaging device according to the first embodiment. As shown in FIG. 2, the pixel 100 includes a photodiode 101, a transfer MOS transistor 102, a reset MOS transistor 103, an amplification MOS transistor 104, a selection MOS transistor 105, and a power supply voltage line 107 (voltage VDD). A drive signal TX is input to the gate of the transfer MOS transistor 102, a drive signal RES is input to the gate of the reset MOS transistor 103, and a drive signal SEL is input to the gate of the selection MOS transistor 105.

  The anode of the photodiode 101 is grounded, and the cathode of the photodiode 101 is connected to the source of the transfer MOS transistor 102. The drain of the transfer MOS transistor 102 is connected to the source of the reset MOS transistor 103 and the gate of the amplification MOS transistor 104. A connection point between the drain of the transfer MOS transistor 102, the source of the reset MOS transistor 103, and the gate of the amplification MOS transistor 104 forms a floating diffusion unit 106. The drains of the reset MOS transistor 103 and the amplification MOS transistor 104 are connected to the power supply voltage line 107. The source of the amplification MOS transistor 104 is connected to the drain of the selection MOS transistor 105. The source of the selection MOS transistor 105 is connected to the vertical signal line 22.

  The photodiode 101 is a photoelectric conversion element that generates a signal charge corresponding to incident light by photoelectric conversion. When the drive signal TX becomes high level, the transfer MOS transistor 102 becomes conductive, and transfers the signal charge generated in the photodiode 101 to the floating diffusion unit 106. The amplification MOS transistor 104 outputs a signal voltage corresponding to the charge transferred to the floating diffusion unit 106 to the vertical signal line 22 via the selection MOS transistor 105. The amplification MOS transistor 104 and a current source (not shown) form a source follower circuit. The floating diffusion 106 that is a gate node of the amplification MOS transistor 104 serves as an input node of the source follower circuit. When the drive signal RES becomes high level, the reset MOS transistor 103 becomes conductive. By this operation, the floating diffusion unit 106 is reset to a predetermined potential (reset potential).

  When the drive signal SEL of a certain row becomes high level, the selection MOS transistor 105 of that row becomes conductive, and the row is selected. The signal voltage generated by the pixels 100 in the selected row is output to the vertical signal line 22 and input to the storage capacitor 31 via the readout circuit 21. The holding capacitor 31 holds a signal output from the pixel 100 by holding a charge corresponding to the signal voltage between the terminals. Thereafter, horizontal scanning is performed, the horizontal scanning transistors 32 in each column are sequentially turned on, and the signal held in the holding capacitor 31 is transferred to the horizontal transfer line 33.

  A parasitic capacitance may be generated between the horizontal transfer line 33 and a conductive member or the like disposed near the horizontal transfer line 33 by capacitive coupling. When the horizontal scanning transistor 32 becomes conductive, charge movement occurs so that the voltage of the horizontal transfer line 33 and the voltage of the storage capacitor 31 match. At this time, a part of the charge held in the holding capacitor 31 is used for charging the parasitic capacitance described above. The voltage of the horizontal transfer line 33 becomes a voltage corresponding to the charge held in the holding capacitor 31 and the combined capacitance of the holding capacitor 31 and the parasitic capacitance of the horizontal transfer line 33 by capacitive division. Accordingly, the voltage of the horizontal transfer line 33 is lower than the voltage of the storage capacitor 31 before the horizontal scanning transistor 32 is turned on. That is, the signal amplitude can be reduced by capacitive division between the storage capacitor 31 and the parasitic capacitance generated in the horizontal transfer line 33. Note that in this specification, the capacity division means that when the first capacitor is connected to another second capacitor by a transistor or the like, the voltage held in the first capacitor is the first and second capacitors. It means that the voltage is converted into a voltage according to the combined capacity of That is, in this embodiment, the voltage held in the holding capacitor 31 is converted into a voltage corresponding to the combined capacitance of the holding capacitor 31 and the horizontal transfer line 33. When a capacitive element is connected to the horizontal transfer line 33, the capacity of the horizontal transfer line 33 is a combined capacity of a component due to the parasitic capacitance of the horizontal transfer line 33 and a component due to the connected capacitive element.

  The shield wire 35 of this embodiment has an effect of reducing the amount of signal amplitude reduction due to the above-described factors. With reference to FIG. 3A, FIG. 3B, and FIG. 4, the effect of the shield wire 35 will be described. FIG. 3A is an equivalent circuit diagram of the horizontal transfer unit 30a according to the present embodiment. FIG. 3B is an equivalent circuit diagram of the horizontal transfer unit 30b according to the comparative example assuming that the shield wire 35 is not provided. FIG. 4 is a diagram illustrating an example of a signal waveform in the horizontal transfer line 33 according to the present embodiment and the comparative example.

  In the equivalent circuit diagram of the horizontal transfer unit 30a shown in FIG. 3A, a parasitic capacitor 36, a parasitic capacitor 37, a conductive member 38, and a parasitic capacitor 39a are illustrated. The parasitic capacitance 36 is equivalent to a parasitic capacitance generated between the horizontal transfer line 33 and the shield line 35. The conductive member 38 is a member containing a material such as a conductive metal or semiconductor disposed near the horizontal transfer line 33 in the solid-state imaging device. The conductive member 38 may be a third wiring having a voltage different from the horizontal transfer line 33 and the shield line 35, such as a signal voltage, a ground voltage, or a power supply voltage. Alternatively, the conductive member 38 may be a part of a semiconductor substrate having a voltage different from that of the horizontal transfer line 33 and the shield line 35 on which the solid-state imaging device is formed. An impurity diffusion region is formed in the semiconductor substrate, and parasitic capacitance may occur between the semiconductor substrate and a wiring such as the horizontal transfer line 33. The parasitic capacitance 37 in FIG. 3A is equivalent to the parasitic capacitance between the shield line 35 and the conductive member 38. That is, the shield line 35 is disposed between the horizontal transfer line 33 and the conductive member 38 so as to shield the capacitive coupling. Thereby, the capacitance value of the parasitic capacitance 39a caused by the capacitive coupling directly generated between the horizontal transfer line 33 and the conductive member 38 can be set to a sufficiently small value. More specifically, since the shield line 35 is disposed closer to the horizontal transfer line 33 than the conductive member 38, the parasitic capacitance 39 a can be made smaller than the parasitic capacitance 36.

  On the other hand, the shield line 35 is not provided in the equivalent circuit diagram of the horizontal transfer unit 30b according to the comparative example shown in FIG. Therefore, a parasitic capacitance 39b larger than the parasitic capacitance 39a in the case of FIG. 3A is generated between the horizontal transfer line 33 and the conductive member 38.

  Each of the equivalent circuits shown in FIGS. 3A and 3B will be described with respect to a decrease in signal amplitude due to capacitive division when the horizontal scanning transistor 32 becomes conductive. Here, it is assumed that the voltage held in the holding capacitor 31 before the horizontal scanning transistor 32 becomes conductive is V1. Further, in the equivalent circuit of FIG. 3A, the voltage of the horizontal transfer line 33 after the horizontal scanning transistor 32 becomes conductive is assumed to be V2. In the equivalent circuit of FIG. 3B, it is assumed that the voltage of the horizontal transfer line 33 after the horizontal scanning transistor 32 becomes conductive is V3. Furthermore, the capacitance values of the storage capacitor 31 and the parasitic capacitors 36, 37, and 39b are assumed to be C1, C2, C3, and C4, respectively. In the following description, the capacitance value of the parasitic capacitance 39a is assumed to be negligibly small.

  First, with reference to the equivalent circuit of FIG. 3B according to the comparative example, a decrease in signal amplitude due to capacitive division will be described. Before the horizontal scanning transistor 32 becomes conductive, the voltage V1 is held in the holding capacitor 31 having the capacitance value C1. When the horizontal scanning transistor 32 becomes conductive, the capacitance value is a combined capacitance (C1 + C4) of the holding capacitor 31 and the parasitic capacitor 39b, and the voltage held by these is V3. Since the charge is stored at both times, the relationship V3 = V1 × C1 / (C1 + C4) is obtained. Since C1 / (C1 + C4) is a value smaller than 1, V3 is a voltage smaller than V1. Therefore, in the comparative example, the signal amplitude decreases from V1 to V3 due to the capacity division. When the signal amplitude decreases, the S / N (Signal-to-Noise) ratio decreases, which may cause the image quality of an image acquired by the solid-state imaging device to deteriorate.

  On the other hand, in the equivalent circuit of FIG. 3A according to the present embodiment, instead of the parasitic capacitance 39b between the horizontal transfer line 33 and the conductive member 38, it is between the horizontal transfer line 33 and the shield line 35. A parasitic capacitance 36 and a parasitic capacitance 37 between the shield wire 35 and the conductive member 38 are generated. When the voltage V2 of the horizontal transfer line 33 is calculated assuming that the shield line 35 is a float wiring in the same manner as in the comparative example described above, the relationship V2 = V1 × C1 / (C1 + C5) is obtained. Here, C5 is a combined capacitance of C2 and C3, and C5 = C2 × C3 / (C2 + C3). If C4 and C5 are approximately the same value, the same result as in the comparative example is obtained.

  However, a voltage having the same sign as that of the horizontal transfer line 33 is applied to the shield line 35 by the output amplifier 34. Typically, the voltage of the shield line 35 and the voltage of the horizontal transfer line 33 are in phase. Here, the same phase means not inverted. A phase difference due to a delay in the output amplifier 34 may occur. In this state, the difference between the voltage of the horizontal transfer line 33 and the voltage of the shield line 35 becomes small. That is, by reducing the voltage applied across the parasitic capacitor 36, the charge held in the parasitic capacitor 36 can be reduced. Thereby, substantially the same effect as the case where C2 is reduced is generated, and C2 which is a combined capacity including C2 can be regarded as being reduced from C4, and therefore V2 is larger than V3. Therefore, in this embodiment, the amount of decrease in signal amplitude due to capacity division is smaller than in the comparative example.

  With reference to FIG. 4, the difference in signal waveform in the horizontal transfer line 33 according to the first embodiment and the comparative example will be described. FIG. 4 shows changes with time of the drive signal PH and the voltage of the horizontal transfer line 33. In the graph of the voltage of the horizontal transfer line 33, the solid line shows the time change of the voltage of the horizontal transfer line 33 of this embodiment, and the broken line shows the time change of the voltage of the horizontal transfer line 33 of the comparative example. When the drive signal PH changes from the low level to the high level at time t1, the horizontal scanning transistor 32 becomes conductive. As the charge moves from the storage capacitor 31 to the parasitic capacitor 36, the voltage of the horizontal transfer line 33 starts to rise. The voltage of the horizontal transfer line 33 at the time t2 when the predetermined settling time has elapsed and the voltage of the horizontal transfer line 33 is stabilized is V2 in the first embodiment, and V3 in the comparative example. As described above, since V2 is larger than V3, it can be seen that, according to the present embodiment, a larger signal amplitude can be obtained as compared with the comparative example.

  The arrangement of the horizontal transfer line 33, the shield line 35, and the conductive member 38 according to the first embodiment will be described with reference to FIGS. 5 (a) and 5 (b). FIG. 5A is an arrangement example when the conductive member 38 is a wiring provided near the horizontal transfer line 33. FIG. 5B shows an arrangement example when the conductive member 38 is a semiconductor substrate.

  In the example of FIG. 5A, an arrangement example in the case where the horizontal transfer line 33 and the conductive member 38 are arranged in the same wiring layer on the semiconductor substrate is shown. In this case, as shown in FIG. 5A, by arranging the shield line 35 between the horizontal transfer line 33 and the conductive member 38, an arrangement for realizing the equivalent circuit of FIG. 3A is possible. . Note that there is a gap between the horizontal transfer line 33, the shield line 35, and the conductive member 38, or an interlayer insulating film (not shown) is disposed between them. The wiring length of the horizontal transfer line 33 is C, and the wiring length of the shield line 35 is D. In this case, by making the wiring length D longer than the wiring length C, the lines of electric force from the horizontal transfer line 33 to the conductive member 38 can be more reliably shielded, so that the amount of decrease in signal amplitude can be further reduced. it can. Here, the wiring length C of the horizontal transfer line 33 means the length from the position where the horizontal scanning transistor 32 is connected on the horizontal transfer line 33 to the input terminal of the output amplifier 34. As shown in FIG. 5A, when the horizontal transfer line 33 and the conductive member 38 are formed in the same layer, the shield line 35 is preferably formed in the same layer. . This is because the lines of electric force from the horizontal transfer line 33 to the conductive member 38 can be shielded more reliably, and the amount of decrease in signal amplitude can be further reduced.

  In the example of FIG. 5B, an arrangement example in the case where the horizontal transfer line 33 is arranged on the conductive member 38 which is a semiconductor substrate is shown. A shield line 35 is disposed on the conductive member 38 via an interlayer insulating film (not shown). A horizontal transfer line 33 is disposed on the shield line 35 via an interlayer insulating film (not shown). In this case, as shown in FIG. 5B, the shield line 35 is arranged in a layer between the horizontal transfer line 33 and the conductive member 38, thereby realizing the equivalent circuit of FIG. Is possible. The wiring width of the horizontal transfer line 33 is A, and the wiring length is C. The wiring width of the shield wire 35 is B, and the wiring length is D. In this case, as in the case of FIG. 5A, by making the wiring length D longer than the wiring length C, the lines of electric force from the horizontal transfer line 33 to the conductive member 38 can be more reliably shielded. The amount of decrease in amplitude can be further reduced. Further, by making the wiring width B longer than the wiring width A, the amount of decrease in signal amplitude can be further reduced for the same reason.

  In the example of FIGS. 5A and 5B, the magnitude relationship between the wiring width and the wiring length of the horizontal transfer line 33 and the shield line 35 is not limited to the above-described relation. The relationship between the wiring width and the wiring length of the horizontal transfer line 33 and the shield line 35 is the optimization of the time (t2-t1) until the voltage of the horizontal transfer line 33 described with reference to FIG. It can be designed in consideration of various factors. By designing in consideration of these factors, when the wiring length C is longer than the wiring length D, when the wiring length C and the wiring length D are the same length, when the wiring width A is longer than the wiring width B, Alternatively, even when the wiring width A and the wiring width B are the same length, a sufficient signal amplitude can be obtained.

  The arrangement of the horizontal transfer line 33, the shield line 35, and the conductive member 38 is not limited to the example shown in FIG. 5A or 5B, and the influence of the parasitic capacitance 36 can be reduced. If necessary, it can be changed as appropriate. Further, by combining the configuration of FIG. 5A and the configuration of FIG. 5B, a first shield layer is disposed between the horizontal transfer line 33 and the wiring, and the first shield layer is disposed between the horizontal transfer line 33 and the semiconductor substrate. It is good also as a structure which arrange | positions two shield layers. According to this configuration, the amount of decrease in signal amplitude can be further reduced.

  According to this embodiment, the influence of the parasitic capacitance between the horizontal transfer line 33 and the conductive member 38 is reduced by the shield line 35 having the same sign as that of the horizontal transfer line 33. As a result, it is possible to reduce image quality deterioration due to signal amplitude reduction.

(Second Embodiment)
FIG. 6 is an equivalent circuit diagram of the horizontal transfer unit 50 according to the second embodiment of the present invention. The configuration of the solid-state imaging device according to the present embodiment is the same as that of the first embodiment except that a horizontal transfer unit 50 is provided instead of the horizontal transfer unit 30 of the first embodiment. Therefore, description of parts other than the horizontal transfer unit 50 is omitted.

  The horizontal transfer unit 50 further includes an amplifier 54 in addition to the output amplifier 34. The input terminal of the amplifier 54 is connected to the horizontal transfer line 33, and the output terminal of the amplifier 54 is connected to the shield line 35. Unlike the first embodiment, the shield wire 35 is not connected to the output terminal of the output amplifier 34 in this embodiment. In other words, since the amplifier 54 of this embodiment is provided separately from the output amplifier 34, it has a function as an output amplifier that outputs a signal to a circuit in a subsequent stage in the solid-state imaging device or to the outside of the solid-state imaging device. do not do.

  In the first embodiment, since the shield line 35 is connected to the output terminal of the output amplifier 34, the wiring layout of the shield line 35 is restricted by the position of the output amplifier 34. However, in this embodiment, since the shield line 35 is connected to the output terminal of the amplifier 54 different from the output amplifier 34, the wiring layout of the shield line 35 is not restricted by the position of the output amplifier 34. Therefore, according to the present embodiment, in addition to the same effects as those of the first embodiment, the degree of freedom of the wiring layout is improved, so that the design of the wiring layout is simplified.

(Third embodiment)
FIG. 7 is an equivalent circuit diagram of the horizontal transfer unit 60 according to the third embodiment of the present invention. The configuration of the solid-state imaging device according to this embodiment is the same as that of the first embodiment, except that a horizontal transfer unit 60 is provided instead of the horizontal transfer unit 30 of the first embodiment. Therefore, description of parts other than the horizontal transfer unit 60 is omitted.

  The horizontal transfer unit 60 includes an output amplifier 61 instead of the output amplifier 34. The output amplifier 61 includes an input transistor 62, output transistors 63 and 64, and current sources 65, 66 and 67. The horizontal transfer line 33 is connected to the gate of the input transistor 62. A power supply voltage is applied to the drain of the input transistor 62. The source of the input transistor 62 is connected to the current source 65, the gate of the output transistor 63 and the gate of the output transistor 64. A power supply voltage is applied to the drain of the output transistor 63 and the drain of the output transistor 64. The source of the output transistor 63 is connected to the shield line 35 and the current source 66. The source of the output transistor 64 is connected to the current source 67 and constitutes the output terminal of the output amplifier 61. That is, the output amplifier 61 is a source follower circuit having two functions: a function of outputting a voltage corresponding to the voltage of the horizontal transfer line 33 to the shield line 35 and a function of outputting the voltage to the output terminal of the output amplifier 61.

  In other words, in the output amplifier 61, the output to the shield line 35 is driven by the output transistor 63. An output transistor 64 drives an output to the output terminal of the output amplifier 61, that is, the circuit in the subsequent stage in the solid-state imaging device or the wiring transmitted to the outside of the solid-state imaging device. Therefore, the input transistor 62 does not require a large driving force (current supply capability). Thereby, in addition to the effect of the first embodiment, the gate capacitance of the input transistor 62 can be reduced, so that the parasitic capacitance due to the output amplifier 61 that can be parasitic on the horizontal transfer line 33 can be further reduced. Therefore, it is possible to further reduce image quality deterioration due to signal amplitude reduction.

(Fourth embodiment)
FIG. 8 is a layout diagram of the horizontal transfer line 33, the shield line 35, and the conductive member 38 according to the fourth embodiment of the present invention. The configuration of the solid-state imaging device according to the present embodiment is the same as that of the first embodiment except for the arrangement of the horizontal transfer line 33, the shield line 35, and the conductive member 38 described in the first embodiment with reference to FIG. It is the same. Therefore, the overlapping description is omitted.

  With reference to FIG. 8A and FIG. 8B, the arrangement of the horizontal transfer line 33, the shield line 35, and the conductive member 38 according to the fourth embodiment will be described. FIG. 8A is an arrangement example when the conductive member 38 is a wiring provided near the horizontal transfer line 33. FIG. 8B is an arrangement example when the conductive member 38 is a semiconductor substrate.

  The layout of this embodiment shown in FIG. 8A differs from FIG. 5A of the first embodiment in that the wiring length D of the shield line 35 is shorter than the wiring length C of the horizontal transfer line 33. When the shield line 35 is long as in the first embodiment, depending on the driving power of the transistors constituting the output amplifier 34, it takes until the horizontal transfer line 33 has a stable waveform after the horizontal scanning transistor 32 becomes conductive. Settling time can be longer. When the settling time is a problem from the viewpoint of the operation speed of the solid-state imaging device, the wiring length D of the shield wire 35 is designed to be shorter than the wiring length C of the horizontal transfer line 33 as shown in FIG. Thus, the capacitance value C2 of the parasitic capacitance 36 can be reduced, and the settling time can be shortened. Further, by appropriately setting the relationship between the wiring length D of the shield line 35 and the wiring length C of the horizontal transfer line 33, it is possible to achieve both the effect of the first embodiment and the maintenance of the operation speed of the solid-state imaging device. it can.

  The layout of this embodiment shown in FIG. 8B is different from FIG. 5B of the first embodiment in that the wiring length D of the shield line 35 is shorter than the wiring length C of the horizontal transfer line 33. In the case of this example, the same effect as described above with reference to FIG.

(Fifth embodiment)
FIG. 9 is a diagram illustrating an example of a circuit configuration of a solid-state imaging device according to the fifth embodiment of the present invention. The solid-state imaging device according to the present embodiment is different from the first embodiment in that a horizontal transfer unit 70 is provided instead of the horizontal transfer unit 30 of the first embodiment. The horizontal transfer unit 70 has two output terminals (output A and output B), and is configured to be able to horizontally transfer signals from two columns in parallel. That is, in the solid-state imaging device of the present embodiment, signals output from some columns of the imaging region 10 are output from the output A, and signals output from other partial columns of the imaging region 10 are output from the output B. The horizontal transfer is speeded up by being configured to output. In FIG. 9, “a” is attached to the reference numerals of the constituent elements corresponding to the output A, and “b” is attached to the reference numerals of the constituent elements corresponding to the output B. Note that the number of horizontal transfers performed in parallel by the horizontal transfer unit 70 may be three or more.

  The horizontal transfer unit 70 includes storage capacitors 31a and 31b, horizontal scanning transistors 32a and 32b, horizontal transfer lines 33a and 33b, output amplifiers 34a and 34b, and shield lines 71a, 71b, 72a, 72b, and 73. The configuration of the horizontal transfer unit 70 of the present embodiment is different from the horizontal transfer unit 30 of the first embodiment in the arrangement of shield lines 71a, 71b, 72a, 72b, 73. The other components are substantially the same as those in the first embodiment except that there are two systems for horizontal transfer, and therefore the description of the connection relationship is omitted or simplified.

  The horizontal transfer line 33a that is the first wiring is connected to the input terminal of the output amplifier 34a that is the first amplifier. The shield lines 71a and 72a as the second wiring are both connected to the output terminal of the output amplifier 34a. The shield wire 73 as the sixth wiring is grounded. The horizontal transfer line 33b that is the fourth wiring is connected to the input terminal of the output amplifier 34b that is the second amplifier. The shield lines 71b and 72b as the fifth wiring are both connected to the output terminal of the output amplifier 34b as the second amplifier. It is not essential that the shield wire 73 is grounded, and a fixed voltage may be applied.

  FIG. 10 is a diagram showing the arrangement of horizontal transfer lines and shield lines according to the fifth embodiment. The arrangement of the horizontal transfer lines 33a and 33b and the shield lines 71a, 71b, 72a, 72b, and 73 will be described with reference to FIG. 10 in addition to FIG. The shield lines 71a and 72a are arranged adjacent to the horizontal transfer line 33a so as to sandwich the horizontal transfer line 33a. Similarly, the shield lines 71b and 72b are disposed adjacent to the horizontal transfer line 33b so as to sandwich the horizontal transfer line 33b. The shield wire 73 is disposed between the shield wire 72a and the shield wire 71b. The shield lines 71a, 71b, 72a, 72b have a function of shielding the lines of electric force between the horizontal transfer lines 33a, 33b and the conductive member 38, as in the first embodiment. In addition, the shield lines 71b and 72a also have a function as a shield between the horizontal transfer line 33a and the horizontal transfer line 33b.

  In the present embodiment, as in the first embodiment, the voltage difference between the horizontal transfer line 33a and the shield lines 71a and 72a is reduced, and the voltage difference between the horizontal transfer line 33b and the shield lines 71b and 72b is reduced. By doing so, it is possible to reduce deterioration in image quality due to a decrease in signal amplitude.

  The additional effect by providing the shield wire 73 between the shield wire 72a and the shield wire 71b will be described. When the shield line 73 is not provided, parasitic capacitance due to capacitive coupling may occur between the shield line 72a and the shield line 71b. If the voltage of the shield line 72a or the shield line 71b fluctuates due to the parasitic capacitance between the shield line 72a and the shield line 71b, the effect of reducing image quality degradation due to a decrease in signal amplitude may not be sufficient. Furthermore, the voltage waveforms of the horizontal transfer line 33a and the horizontal transfer line 33b may become unstable, and signal mixing between the horizontal transfer line 33a and the horizontal transfer line 33b may also occur. Therefore, in the present embodiment, a shield line 73 having a fixed voltage is provided between the shield line 72a and the shield line 71b. Thereby, since the parasitic capacitance generated between the shield line 72a and the shield line 71b can be reduced, the influence of the above-described problem is reduced.

(Sixth embodiment)
An imaging system 200 according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a block diagram illustrating a configuration example of the imaging system 200 according to the present embodiment.

  The imaging system 200 according to the present embodiment is not particularly limited, but can be applied to, for example, a digital still camera, a digital camcorder, a camera head, a copier, a fax machine, a mobile phone, an in-vehicle camera, an observation satellite, and the like. .

  The imaging system 200 includes a barrier 201, a lens 202, a diaphragm 203, a solid-state imaging device 204, a signal processing unit 207, a timing generation unit 208, an overall control / calculation unit 209, a memory unit 210, a recording medium control I / F unit 211, an external An I / F unit 213 is included. As the solid-state imaging device 204, the solid-state imaging device according to the first to fifth embodiments can be applied.

  The lens 202 is for forming an optical image of the subject on the solid-state imaging device 204. The diaphragm 203 is for changing the amount of light passing through the lens 202. The barrier 201 is for protecting the lens 202. The solid-state imaging device 204 is the solid-state imaging device described in the previous embodiment, and converts an optical image formed by the lens 202 into image data.

  The signal processing unit 207 is a signal processing device that performs processing such as AD (Analog-to-Digital) conversion, various corrections, and data compression on the signal output from the solid-state imaging device 204. Note that the AD conversion circuit that performs AD conversion may be mounted on the same substrate as the solid-state imaging device 204 or may be mounted on a different substrate. Further, the signal processing unit 207 may be mounted on the same substrate as the solid-state imaging device 204 or may be mounted on another substrate. The timing generator 208 is for outputting various timing signals to the solid-state imaging device 204 and the signal processor 207. The overall control / calculation unit 209 is an overall control unit that controls the entire imaging system 200. Here, timing signals and the like may be input from the outside of the imaging system 200. The imaging system 200 includes at least a solid-state imaging device 204 and a signal processing unit 207 that processes the imaging signal output from the solid-state imaging device 204. If you do.

  The memory unit 210 is a frame memory unit for temporarily storing image data. The recording medium control I / F unit 211 is an interface unit for performing recording on the recording medium 212 or reading from the recording medium 212. The recording medium 212 is a detachable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 213 is an interface unit for communicating with an external computer or the like.

  In this way, by configuring the imaging system to which the solid-state imaging device according to the first to fifth embodiments is applied, it is possible to realize an imaging system capable of capturing an image with good image quality.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. The configuration of the pixel 100 illustrated in FIG. 2 is an example, and the configuration of the pixel 100 applicable to the solid-state imaging device of the present invention is not limited to this. An imaging system 200 shown in the sixth embodiment is an example of an imaging system to which the solid-state imaging device of the present invention can be applied. An imaging system to which the solid-state imaging device of the present invention can be applied is shown in FIG. It is not limited to the configuration shown in FIG.

  The above-described embodiments are merely examples of some aspects to which the present invention can be applied, and do not prevent appropriate modifications and variations from being made without departing from the spirit of the present invention.

31 Holding Capacitor 33 Horizontal Transfer Line 34 Output Amplifier 35 Shield Line 100 Pixel

Claims (14)

A plurality of pixels arranged in a plurality of columns, each outputting a signal generated by photoelectric conversion;
A plurality of holding capacitors arranged corresponding to the plurality of columns, each holding the signal output from the pixels of the corresponding column;
A first wiring that outputs the signal held in at least one of the plurality of holding capacitors by capacitive division;
A first amplifier for amplifying the signal input to the first wiring;
A second wiring disposed next to the first wiring and to which the signal amplified by the first amplifier is input;
A solid-state imaging device. The solid-state imaging device according to claim 1, wherein the first amplifier outputs a voltage having the same phase as the voltage of the first wiring to the second wiring. The first amplifier includes an output amplifier that outputs the signal input to the first wiring to a circuit in a subsequent stage in the solid-state imaging device or to the outside of the solid-state imaging device. The solid-state imaging device described in 1. 4. The solid state according to claim 3, wherein a wiring for transmitting the signal output from the output amplifier to a subsequent circuit in the solid-state imaging device or the outside of the solid-state imaging device is different from the second wiring. Imaging device. The output amplifier which outputs the said signal input into the said 1st wiring to the circuit of the back | latter stage in a solid-state imaging device, or a solid-state imaging device is provided separately from a said 1st amplifier. 2. The solid-state imaging device according to 2. The second wiring is disposed so as to generate a parasitic capacitance between the second wiring and the first wiring,
The capacity division when the signal is output from the storage capacitor to the first wiring includes a capacitance division between the storage capacitor and the parasitic capacitor. The solid-state imaging device according to item 1. A semiconductor substrate on which the first wiring and the second wiring are formed;
The solid-state imaging device according to claim 1, wherein the second wiring is disposed between the first wiring and the semiconductor substrate. The solid-state imaging device according to claim 7, wherein a parasitic capacitance between the first wiring and the semiconductor substrate is smaller than a parasitic capacitance between the second wiring and the semiconductor substrate. A third wiring having a voltage different from that of the first wiring and the second wiring;
The solid-state imaging device according to any one of claims 1 to 6, wherein the second wiring is disposed between the first wiring and the third wiring. The parasitic capacitance between the first wiring and the third wiring is smaller than the parasitic capacitance between the second wiring and the third wiring. Solid-state imaging device. The solid-state imaging device according to claim 9 or 10, wherein the first wiring, the second wiring, and the third wiring are wirings formed in the same layer. A fourth wiring through which the signal held in at least one of the plurality of holding capacitors is output by capacitive division;
A second amplifier for amplifying the signal input to the fourth wiring;
A fifth wiring arranged next to the fourth wiring and receiving the signal amplified by the second amplifier;
A sixth wiring disposed between the second wiring and the fifth wiring and having a fixed voltage;
The solid-state imaging device according to claim 1, further comprising: The solid-state imaging device according to any one of claims 1 to 12, wherein the first wiring and the second wiring each extend in a direction intersecting the column. A solid-state imaging device according to any one of claims 1 to 13,
An image pickup system comprising: a signal processing device that processes the signal output from the solid-state image pickup device.

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