JP2009225301A - Method of driving photoelectric conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress generation of a gain difference in a read signal while reducing a chip area. <P>SOLUTION: In a photoelectric conversion apparatus including a capacitor, third wiring for outputting a signal from the capacitor via a switch and a plurality of first wiring between the capacitor and the third wiring, second wiring is provided with a wiring capacity different from that of each of the first wiring. While a pixel signal is output to the third wiring, at least one first wiring and the second wiring are electrically connected to the third wiring. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a readout circuit of a photoelectric conversion device and a driving method thereof.

  In recent years, photoelectric conversion devices have been used in digital cameras and the like. Representative types of this photoelectric conversion device include a CCD type and a MOS type photoelectric conversion device. The MOS photoelectric conversion device includes a pixel portion in which pixels, which are basic cells including a photoelectric conversion element such as a photodiode, are two-dimensionally arranged, a capacitor portion that holds a signal from the pixel portion, and a signal from the capacitor portion. And a common signal line for outputting to the outside.

As the number of pixels and the size of the photoelectric conversion device are increasing, the number of switching transistors and the length of the common signal line tend to increase, and the capacitance of the common signal line tends to increase. Patent Document 1 discloses a photoelectric conversion device having a configuration in which signals from a plurality of pixel portions are read out to a block wiring and then output to a common signal line in order to reduce the capacity of the common signal line.
JP 2003-224776 A

  In the method described in Patent Document 1, it is difficult to evenly distribute the switches to each block wiring depending on the number of pixels, and it is also difficult to make each block wiring have an equal length. Further, if the lengths of the block wirings are different, a gain difference occurs in the read signal.

  Accordingly, an object of the present invention is to provide a driving method for suppressing the occurrence of a gain difference in a read signal while reducing a chip area in a photoelectric conversion device having a block wiring.

  The present invention provides a plurality of photoelectric conversion elements, a plurality of capacitors for holding signals from the plurality of photoelectric conversion elements, a first switch connected to each of the plurality of capacitors, and a plurality of the first switches. A plurality of first wirings connected to one switch, a second number of second wirings connected to a plurality of first switches, a third number of wirings, and a plurality of the first wirings. A method for driving a photoelectric conversion device, comprising: a plurality of second switches that connect each of the first wirings and the third wiring, wherein the second wirings and the third wirings are And at least one of the first and second wirings in a period of being electrically connected and reading a signal from the capacitor to the third wiring through the first switch, the second wiring, and the second switch. The switch of 2 is conducting.

  In a photoelectric conversion device having a block wiring, it is possible to suppress the occurrence of a gain difference in a read signal while reducing the chip area.

  In a photoelectric conversion device having a capacitor, a third wiring that outputs a signal from the capacitor through a switch, and a plurality of first wirings between the capacitor and the third wiring, a wiring that is different from the first wiring A capacitor second wiring is provided. And while outputting a pixel signal to the 3rd wiring, it has at least 1st wiring and 2nd wiring which are electrically connected to the 3rd wiring. With such a configuration, it is possible to suppress the occurrence of a read signal gain difference while reducing the chip area.

  Here, the first wiring and the second wiring are also referred to as block wiring. The block wiring indicates a node in which a plurality of the other terminals of the switch having one terminal connected to the capacitor are connected in common. By having such a block wiring, it is possible to reduce the capacity of the third wiring, and it is possible to suppress a decrease in the gain of the read signal and improve the read speed.

  Hereinafter, it explains in detail using a drawing.

(First embodiment)
In the present embodiment, a configuration having block wirings having different wiring capacitances and a driving method in that case will be described.

  FIG. 1 is a simple circuit diagram of a photoelectric conversion device illustrating this embodiment. Reference numeral 100 denotes a pixel region. In the pixel region 100, pixels 1 including one photoelectric conversion element are arranged. In this embodiment, 16 pixels (1-1 to 1-16) in 2 rows and 8 columns are arranged for simplicity, but a larger number of pixels may be arranged. Each pixel 1 will be described in detail later with reference to FIG. Signal lines 3 (3-1 to 3-8) for outputting a signal from each pixel are arranged in each pixel column. A drive wiring 13 (13-1, 13-2) for supplying a drive signal from the vertical scanning circuit 9 to each pixel is arranged for each row. Further, a switch 4 (4-1 to 4-8) and a capacitor 2 (2-1 to 2-8) are arranged in order on each signal line 3. The signal of the pixel 1 output to each signal line 3 is held in the capacitor 2 by the switch 4. Furthermore, the first switches 5 (5-1 to 5-8) are connected to the capacitors 2 respectively. The first switch 5 is connected to the first wiring 14 (14-1, 14-2) or the second wiring 12. The plurality of first wirings 14 are respectively connected via the second switch 7 (7-1, 7-2), and the second wiring 12 is connected via the third switch 6 to one third wiring. 8 is connected. Although only two first wirings 14 are described, a larger number of first wirings may be provided, and the second wiring 12 is the same. The horizontal scanning circuit 10 controls driving from the capacitor 2 to the third wiring 8. That is, the horizontal scanning circuit 10 is a control unit that controls a switch and the like. T1 (1-1 to 1-8) and T2 (2-1 to 2-3) are drive wirings for driving each switch. Here, the capacitor 2, the first switch 5, the first wiring 14, the second wiring 12, the second switch 7, the third switch 6, and the third wiring 8 are referred to as a readout circuit 200.

  Here, the first switch 5, the first wiring 14, and the second wiring 12 will be described in detail. The first switch 5 is divided into a plurality of blocks. The first switch 5 of each block is connected to the first wiring 14 (14-1, 14-2) or the second wiring 12. In this state, it can be said that the terminals of the plurality of first switches 5 are commonly connected. Each of the plurality of first wirings 14 is designed such that the same number of first switches 5 are connected, the lengths thereof are equal, and the wiring capacity is approximately equal. The second wiring 12 is connected to a different number of first switches 5 from the first wiring 14, has a different length, and has a different wiring capacitance. In the present embodiment, the second wiring 12 is connected to the first switch 5 fewer than the first wiring 14 and is a short wiring. The first wiring 14 and the second wiring 12 are also referred to as block wiring.

  By having such a second wiring 12, it is possible to determine the number of first switches 5 included in the first wiring 14 without depending on the number of pixels, as shown in FIG. Since no extra chip area is required, the chip size can be reduced. Further, since the wiring capacity of the third wiring 8 can be reduced, it is possible to improve the gain at the time of signal reading and to speed up the signal reading.

  Next, a driving method of the readout circuit 200 in FIG. 1 will be described with reference to FIG. First, the signal of each pixel is output to the third wiring through the following two paths. One is a path through which the signal of the capacitor 2 is transmitted in this order through the first switch 5, the first wiring, and the second switch, and the other is the signal of the capacitor 2 that is transmitted to the first switch 5 and the second switch. 2 is a path through which the second wiring and the third switch are transmitted in this order. FIG. 3 shows drive pulses applied to the respective drive wirings when signals are sequentially output from the respective capacitors 2 to the third wiring 8. It is assumed that the drive pulse is binary and high (H) level, the switch is conductive (ON), and low (L) level, the switch is non-conductive (OFF).

  First, the pulse from t1 to T2-3 becomes H, and the third switch 6 is always kept on. At t2, the pulse of T2-1 becomes H and the second switch 7-1 is turned on, and at time t3 to t5, the pulses of T1-1, 1-2, and 1-3 become H sequentially, and the first switch 5 are sequentially turned on, so that the signals held in the capacitors 2-1, 2-2, 2-3 are output. Next, at t6, T2-1 becomes L and T2-2 becomes H, and the first wiring 14-2 and the third wiring 8 are connected instead of the first wiring 14-1. Similar to t3 to t5, the signal held in the capacitor 2.4.2-5.2-6 is output from t7 to t9. At t10, the pulse T2-2 is H, T1-7 becomes H, and the signal held in the capacitor 2-7 is output to the third wiring 8 through the second wiring 12. The Next, at t <b> 11, the pulse of T <b> 2-2 is H, T <b> 1-8 becomes H, and the signal held in the capacitor 2-8 is output to the third wiring 8 through the second wiring 12. .

  Thus, during the period in which a signal is output from any one of the plurality of first wirings 14 and the second wirings 12 to the third wiring 8, the first wiring 14 and the second wiring are always provided. 12 is electrically connected to the third wiring 8. Specifically, one of the second switches 7 and the third switch 6 are always turned on. By using such a driving method, it is possible to suppress the occurrence of a gain difference when signals are output from the second wiring 12 and the first wiring 14 having different wiring capacities. Note that the period in which a signal is output to the third wiring 8 is a signal reading period in which the signal is read to the outside.

Here, the gain difference which is a problem will be described in detail.
First, the length of the block wiring will be described with reference to the schematic diagram of the photoelectric conversion device having the block wiring in FIGS. 14A and 14B. 1000 is a chip, 100 is a pixel region, and 301 is a block wiring. As shown in FIG. 14A, there is a method using the same block wiring 301. In this method, an excess is made by the length y, and the chip area cannot be reduced. The length y is y = nx−N where n is the number of switches included in one block wiring, x is the number of block wirings, and N is the total number of pixels.

  As a method of reducing the chip area, there is a method of providing a block wiring 302 having a different wiring capacity to which a number of switches different from a predetermined number as shown in FIG. 14B are connected. However, when a signal is read from the block wiring 302 having a different wiring capacity, the gain of the read signal also changes.

  Further, a change in gain when the chip area is reduced as shown in FIG. 14B will be described. As shown in FIG. 1, when a signal is output from the capacitor 2 to the wiring via the first switch 5, the signal gain G is determined by the capacitance division ratio between the capacitor CT of the capacitor 2 and the wiring capacitor CH. Specifically, the gain G is CT / (CT + CH). The wiring capacitance CH is the capacitance of the wiring connected when reading the signal of the capacitance 2 (including the capacitance of the switch and the parasitic capacitance). Here, CH1 is the wiring capacity of the first wiring 14, CH2 is the wiring capacity of the second wiring 12, and CH3 is the wiring capacity of the third wiring 8. For example, one of the first wirings 14 and the second wiring are driven differently from those in FIG. 3, that is, during a period in which a signal is output from the first wiring 14 or the second wiring 12 to the third wiring 8. Consider a case in which 12 is not electrically connected to the third wiring 8. At that time, the wiring capacity is CH = CH1 + CH3 or CH = CH2 + CH3. Here, since the wiring capacitance CH1 and the wiring capacitance CH2 are different values, the wiring capacitance CH may be different, that is, the gain G may be different.

  However, in the drive of FIG. 3, the wiring capacity is always CH = CH1 + CH2 + CH3. Accordingly, the gain G is always constant, and it is possible to output a signal with a constant gain G even when a signal is output from the first wiring 14 or a signal is output from the second wiring 12.

  In addition, the number of first switches connected to the second wiring may be longer than that of the first wiring. Further, the arrangement of the first wiring and the second wiring is not limited to the arrangement shown in FIG. 1, and the second wiring may be arranged between the plurality of first wirings.

  In addition, since it is only necessary to always have a constant wiring capacity, the two first wirings 14 and the second wirings 12 may be electrically connected to the third wiring 8 during a signal reading period. .

  Further, even when the fourth wiring having a wiring capacitance different from that of the first wiring and the second wiring is included, the first wiring, the second wiring, and the fourth wiring are read during the signal reading period. It is only necessary that the wiring is electrically connected to the third wiring 8.

  Here, if there are many connected wirings, the wiring capacitance CH increases and the gain G decreases, so that the only different wiring is the second wiring and only one first wiring is used, as in this embodiment. Is preferably electrically connected to the third wiring 8. In other words, it is desirable to connect in a combination that is the least common multiple of the wiring capacity of each wiring that can be a block wiring.

  As described above, with the configuration of the present embodiment, it is possible to suppress the occurrence of a gain difference in signal readout while reducing the chip area.

  The rise of the pulses at t1 and t2 may be simultaneous, and the interval between the timing when the second switch and the third switch are turned on or off and the timing when the first switch is turned on or off can be set as appropriate. .

(Second Embodiment)
In the present embodiment, the configuration of the third switch in the first embodiment is different. This embodiment will be described with reference to the circuit diagram of FIG. 4, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  The present embodiment is characterized in that a fixed voltage is supplied to the gate of the third switch 6. When the third switch 6 is an N-type MOS transistor, for example, the power supply voltage VDD is input and is always on. Also in the configuration of FIG. 4, T2-3 is not necessary in the drive pulse shown in FIG. 3, and the other drive is possible by supplying the same drive pulse. With such a configuration, a circuit configuration for supplying the driving pulse for the third switch 6 becomes unnecessary, and the circuit can be reduced.

  Here, since the third switch 6 is always on, the second wiring 12 may be directly connected to the third wiring 8 without providing the third switch 6. However, by providing the third switch 6 as in this embodiment, it is possible to make the impedance the same for the path for reading a signal from the first wiring 14 and the path for reading the signal from the second wiring 12. Become.

(Third embodiment)
In the present embodiment, a case where an optical black pixel region (hereinafter referred to as an OB pixel region) is provided will be described with reference to FIGS. FIG. 5 is a schematic diagram of a photoelectric conversion device, and a circuit diagram corresponding to FIG. 5 is shown in FIG. FIG. 7 shows drive pulses for driving the configuration of FIG. The components having the same functions as those in the first embodiment are denoted by the same reference numerals.

  5 provided in the pixel region 100 shown in FIG. 5 is an OB pixel region, which is a region in which pixels in which a photoelectric conversion element for obtaining a reference signal is shielded are arranged. An area other than the OB pixel area 110 in the pixel area 100 is an effective pixel area 120 where light enters the photoelectric conversion element. The signal of the OB pixel region 110 is output from the second wiring 12, and the signal of the effective pixel region 120 is output from the first wiring 14.

  This will be described in more detail with reference to FIG. In FIG. 6, the pixels 1 are arranged in m columns. The capacitor 2-1 and the capacitor 2-2 that hold signals from the pixels in the OB pixel region 110 are connected to the second wiring 12 via the first switches 5-1 and 5-2. A signal from a pixel in the effective pixel region 120 is held in the capacitor 2-3 or the like, and is connected to the L first wirings 14 (14-1 to 14-L) via the first switch 5-3 or the like. The

  A driving method having such a configuration will be described. The reference numerals in FIG. 7 indicate drive pulses applied to the respective drive wirings as in FIG. A portion of driving different from that in FIG. 3 will be particularly described.

  From t1 to T2-1 in FIG. 7, the H level changes from high to low, and the third switch 6 is always on. The pulse of T2- (L-1) becomes H at t2, and the pulse of T1-1 and T1-2 becomes H at t3 and t4. Here, a pixel signal is output from the second wiring 12 in a state where the first wiring 14- (L-1) is connected. Also in this embodiment, any one of the first wirings 14 and the second wiring 12 are always connected to the third wiring 8.

  Here, unlike the first embodiment (FIG. 3), a signal is first output from the second wiring 12. By adopting such a driving method, a signal from the OB pixel region 110 can be output before the effective pixel region 120, so that processing in a separately provided signal processing circuit is facilitated.

  Further, in the present embodiment, driving for outputting a signal from an arbitrary pixel region is performed. That is, the signals of the pixels 1 arranged in the column 3 (signal line 3-3) to the column 5 (signal line 3-5) are not read out. Specifically, at t5, the pulse of T1- (m-5) becomes H in order to output the signal of the pixel 1 in the column m-5. That is, the H pulse is skipped without being input from T1-3 to T1-5. By performing such driving, it is possible to output a signal from an arbitrary pixel.

  Also in this embodiment, the first wiring 14 connected in the readout period may be any of the L wirings. For example, the first wiring 14 connected while the signal of the pixel 1 is output from the second wiring 12 may be 14-1. However, in consideration of the drive for reading out from any pixel described above, it is desirable to select the first wiring 14-(L−1) from which the signal of the pixel 1 is output next. By such driving, the number of switching of the second switch 7 is reduced, and the driving pulse can be simplified.

(Fourth embodiment)
A schematic diagram of the photoelectric conversion device of this embodiment is shown in FIG. FIG. 9 shows a circuit diagram corresponding to FIG. 8, and FIG. 10 shows driving pulses for driving the configuration of FIG. The photoelectric conversion device of the present embodiment has a configuration in which a second wiring is further provided in the third embodiment and two second wirings 12 (12-1 and 12-2) are provided. The components having the same functions as those of the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The driving method of this embodiment will be described with reference to FIG. The reference numerals in FIG. 10 indicate the driving pulses applied to the respective driving wirings as in FIG. The description of the same driving method as in FIG. 7 is omitted.

  At t13 in FIG. 10, the second wiring connected to the third wiring is switched from T2-1 to T2-5. Further, T2-4 is at the H level after t13 including a period in which a signal is output from the second wiring 12-2. That is, also in the present embodiment, any one of the first wirings 14 and any one of the second wirings 12 are always connected to the third wiring 8. With such a driving method, even when there are a plurality of wirings having different capacities, signals can be read out with the minimum wiring capacity without changing the signal read gain.

(Fifth embodiment)
The present embodiment is characterized in that the readout circuit 200 in the first embodiment is provided vertically. This will be described with reference to the circuit diagram of FIG. 11 and the driving pulse of FIG. Parts similar to those in FIGS. 1 and 3 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 11, for example, one pixel 1 has a color filter corresponding to one color. The color filter has a Bayer array. It has such a pixel region 100, and further has readout circuits 200 (200-1, 200-2) above and below the pixel region for each pixel column. With such a configuration, it becomes possible to read out a signal at higher speed.

  In addition, a driving method in the case of reading while adding signals of a plurality of pixels will be described with reference to FIG. For the sake of simplicity, the description will be given focusing on the reading circuit 200-1.

  Since the pulses of T2-5 and T2-1 become H at t1 and t2, the second wiring 12-1 and the first wiring 14-1 are connected to the third wiring 8-1. Further, at t3, the pulses of T1-1, T1-3, and T1-5 simultaneously become H, and the first switches 5-1, 5-3, and 5-5 are turned on. Then, since the signals of the three blue pixels 1-1, 1-3, and 1-5 are simultaneously output to the third wiring 8-1 through the first wiring 14-1, the third wiring 8 Add by -1. Next, T2-3 becomes H at t4, and the first wiring 14-1 connected to the third wiring is switched to the first wiring 14-3. At t5, the pulses of T1-7, 1-9, and 1-11 become H, and the first switches 5-7, 5-9, and 5-11 are turned on. Then, the signals of the three blue pixels 1-7, 1-9, and 1-11 are simultaneously output to the third wiring 8-1 through the first wiring 14-3, and the third wiring 8- 1 is added. At t6, T1-13 and T1-15 become H, and the signals of the pixels 1-13 and 1-15 are simultaneously output to the third wiring 8-1 through the second wiring 12-1, and are added. With such a configuration and driving, signals of the same color in the third wiring can be added.

  Here, when the number of the first switches to which the first wiring is connected is n and the number of pixels to be added is m, it is desirable that n is a multiple of m. This is because two first wirings must be connected to the third wiring when the capacitors (that is, pixels) holding the signals to be added are connected to different first wirings.

  As the number of added pixels increases, the number n of the first switches connected to the first wiring increases. Therefore, when the configuration as illustrated in FIG. 14A is applied, the value of the length y increases. turn into. Therefore, with the configuration of the present embodiment, it is possible to suppress an increase in chip area even when pixel addition is performed.

(Example of pixel circuit)
An example of the pixel circuit described in each embodiment will be described with reference to FIG. Reference numeral 40 denotes a photodiode as a photoelectric conversion element, 41 denotes a transfer MOS transistor, 42 denotes a reset MOS transistor, 44 denotes an amplification MOS transistor, and 45 denotes a selection MOS transistor. The amplification MOS transistor 44 constitutes a source follower circuit. A signal is read from the pixel 1 as follows. The charge generated in the photoelectric conversion element 40 is transferred to the gate node of the amplification MOS transistor 44 by the transfer MOS transistor 41. When the selection MOS transistor 45 is turned on, a signal corresponding to the potential of the gate node of the amplification MOS transistor 44 is output to the signal line 3. The reset MOS transistor 42 resets the gate node (sets to a predetermined potential). The MOS transistors of these pixels are controlled by a drive signal from the vertical scanning circuit 9 shown in FIG. In the present invention, a configuration in which three MOS transistors other than this configuration are used, and a configuration in which the MOS transistor is shared by a plurality of photoelectric conversion elements are also applicable.

(Application to imaging system)
In the present embodiment, the case where the photoelectric conversion device described in the first to fifth embodiments is applied to an imaging system will be described with reference to FIG. The imaging system is a digital still camera, a digital video camera, or a digital camera for mobile phones.

  FIG. 13 is a block diagram of a digital still camera. An optical image of the subject is formed on the imaging surface of the photoelectric conversion device 804 by an optical system including the lens 802 and the like. On the outside of the lens 802, a barrier 801 serving both as a protection function of the lens 802 and a main switch can be provided. The lens 802 can be provided with a stop 803 for adjusting the amount of light emitted therefrom. The imaging signal output from the photoelectric conversion device 804 through a plurality of channels is subjected to various corrections, clamping, and the like by the imaging signal processing circuit 805. Imaging signals output from the imaging signal processing circuit 805 through a plurality of channels are analog-digital converted by an A / D converter 806. The image data output from the A / D converter 806 is subjected to various corrections, data compression, and the like by a signal processing unit (image processing unit) 807. The photoelectric conversion device 804, the imaging signal processing circuit 805, the A / D converter 806, and the signal processing unit 807 operate in accordance with the timing signal generated by the timing generation unit 808. Here, the control signal may be directly supplied from the timing generation unit 808 to each switch or the like without using the scanning circuit of the photoelectric conversion device 804. That is, the timing generation unit 808 may also serve as the control unit in the first to fifth embodiments.

  805 to 808 may be formed on the same chip as the photoelectric conversion device 804. Each block is controlled by the overall control / arithmetic unit 809. In addition, a memory unit 810 for temporarily storing image data and a recording medium control interface unit 811 for recording or reading an image on a recording medium are provided. The recording medium 812 includes a semiconductor memory or the like and can be attached and detached. Furthermore, an external interface (I / F) unit 813 for communicating with an external computer or the like may be provided.

  Next, the operation of FIG. 13 will be described. When the barrier 801 is opened, the main power supply, the control system power supply, and the image pickup system circuit such as the A / D converter 806 are sequentially turned on. Thereafter, the overall control / arithmetic unit 809 opens the aperture 803 to control the exposure amount. A signal output from the photoelectric conversion device 804 passes through the imaging signal processing circuit 805 and is provided to the A / D converter 806. The A / D converter 806 A / D converts the signal and outputs it to the signal processing unit 807. The signal processing unit 807 processes the data and provides it to the overall control / calculation unit 809, and the overall control / calculation unit 809 performs computation to determine the exposure amount. The overall control / calculation unit 809 controls the aperture based on the determined exposure amount.

  Next, the overall control / calculation unit 809 extracts a high frequency component from the signal output from the photoelectric conversion device 804 and processed by the signal processing unit 807, and calculates the distance to the subject based on the high frequency component. Thereafter, the lens 802 is driven to determine whether or not it is in focus. If it is determined that the subject is not in focus, the lens 802 is driven again to calculate the distance.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the imaging signal output from the photoelectric conversion device 804 is corrected in the imaging signal processing circuit 805, A / D converted by the A / D converter 806, and processed by the signal processing unit 807. The image data processed by the signal processing unit 807 is accumulated in the memory unit 810 by the overall control / arithmetic unit 809.

  Thereafter, the image data stored in the memory unit 810 is recorded on the recording medium 812 via the recording medium control I / F unit under the control of the overall control / arithmetic unit 809. Further, the image data is provided to a computer or the like through the external I / F unit 813 and processed.

  Thus, the photoelectric conversion device of the present invention is applied to an imaging system. By using the photoelectric conversion device of the present invention, the gain of the signal becomes almost constant, so that the processing by the imaging signal processing circuit 805 and the like becomes easy.

  As described above, the configuration of each embodiment is not limited, and can be applied to, for example, a photoelectric conversion device in which pixels are arranged one-dimensionally. In addition, the configuration and driving method of each embodiment are not limited, and the configuration and driving method in each embodiment can be appropriately combined.

1 is a circuit diagram of a photoelectric conversion device for explaining a first embodiment. Example of pixel circuit Drive pulse diagram for explaining the first embodiment Circuit diagram of photoelectric conversion device for explaining the second embodiment Plane schematic diagram of a photoelectric conversion device for explaining a third embodiment Circuit diagram of photoelectric conversion device for explaining the third embodiment Drive pulse diagram for explaining the third embodiment Plane schematic diagram of a photoelectric conversion device for explaining a fourth embodiment Circuit diagram of photoelectric conversion device for explaining the fourth embodiment Drive pulse diagram for explaining the fourth embodiment Plane schematic diagram of a photoelectric conversion device for explaining a fifth embodiment Drive pulse diagram for explaining the fifth embodiment Block diagram explaining the imaging system (A) Plane schematic diagram explaining block wiring, (B) Plane schematic diagram explaining block wiring

Explanation of symbols

100 pixel region 200 readout circuit 2 capacitance 5 first switch 6 third switch 7 second switch 14 first wiring 12 second wiring 8 third wiring 9, 10 scanning circuit

Claims (9)

A plurality of photoelectric conversion elements;
A plurality of capacitors for holding signals from the plurality of photoelectric conversion elements;
A first switch connected to each of the plurality of capacitors;
A plurality of first wirings connected to each of the plurality of first switches;
A second wiring connected to a plurality of first switches, which is different in number from the first wiring;
A third wiring;
A method for driving a photoelectric conversion device, comprising: a plurality of second switches that connect each of the plurality of first wirings and the third wiring;
The second wiring and the third wiring are electrically connected;
At least one of the second switches is conductive during a period in which a signal is read from the capacitor to the third wiring via the first switch, the second wiring, and the second switch. A method for driving a photoelectric conversion device. The second wiring and the third wiring are connected via a third switch;
The third switch is conductive during a period in which a signal is read from the capacitor to the third wiring through the first switch, the first wiring, and the second switch. The method for driving a photoelectric conversion device according to claim 1.   3. The device according to claim 1, wherein the second wiring and the third wiring are connected via a third switch, and the third switch is always conductive. A driving method of the photoelectric conversion device.   In a period in which a signal is read from the capacitor to the third wiring through the first switch, the first wiring, and the second switch, a second different from the conductive second switch The method for driving a photoelectric conversion device according to any one of claims 1 to 3, wherein the switch is conductive. A region where light is incident on the photoelectric conversion element and a region where the photoelectric conversion element is shielded;
The signal of the photoelectric conversion element in the region where the light is incident is read through the first wiring,
5. The method of driving a photoelectric conversion device according to claim 1, wherein a signal of the photoelectric conversion element in the light-shielded region is read out through the second wiring. 6. A plurality of photoelectric conversion elements;
A plurality of capacitors for holding signals from the plurality of photoelectric conversion elements;
A first switch connected to each of the plurality of capacitors;
A plurality of first wirings connected to each of the plurality of first switches;
A second wiring connected to a plurality of first switches, which is different in number from the first wiring;
A third wiring;
A plurality of second switches for connecting each of the plurality of first wirings and the third wiring;
And a control means for controlling the first switch and the second switch,
The second wiring and the third wiring are electrically connected;
At least one of the second switches is conductive during a period in which a signal is read from the capacitor to the third wiring via the first switch, the second wiring, and the second switch. A photoelectric conversion device characterized by that. The second wiring and the third wiring are connected via a third switch;
The photoelectric conversion device according to claim 6, wherein the third switch is always conductive. A region where light is incident on the photoelectric conversion element and a region where the photoelectric conversion element is shielded;
The said 2nd wiring is connected to the capacity | capacitance which hold | maintains the signal from the said photoelectric conversion element of the said light-shielded area | region through the said 1st switch. Photoelectric conversion device. The photoelectric conversion device according to any one of claims 6 to 8,
An imaging system comprising: a signal processing unit that processes a signal obtained from the photoelectric conversion device.

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