JPH11164204A - Amplification type solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the loss of an output signal and to obtain a fast element with high sensitivity by sequentially connecting a signal of a vertical signal line to a horizontal read line, providing a resetting means of horizontal read lines which are connected to the output terminal side of each horizontal read line and are as many as output terminals and the horizontal read lines and defining the parasitic capacity of the horizontal read line according to the number of horizontal switch groups on a 2nd stage. SOLUTION: A signal charge is outputted to a horizontal read line 6 and is outputted as an output Vout through an output amplifier 7. Here, a clock ϕRSTH is inputted to a control gate terminal of a reset switch QR, and the switch QR resets the potential of the line 6 and a horizontal signal line 5 in a horizontal read group B in which read is performed to a ground level. This prevents interference of each inter-signal charge that is successively outputted from the line 6. Then, because only a horizontal switch group Q on a 2nd stage is connected to the line 6, a parasitic capacity to the line 6 is reduced suddenly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifying solid-state imaging device, and more particularly to an amplifying solid-state imaging device capable of reducing loss of an output signal.

[0002]

2. Description of the Related Art An amplification type solid-state imaging device uses an amplification type photoelectric conversion pixel including, for example, an electrostatic induction transistor (SIT) or a plurality of MOS transistors. The signal is converted to a signal, amplified and output. This amplification type solid-state imaging device is
Unlike the D solid-state imaging device, the signal outputs of the pixels arranged in a matrix are sequentially sent to the vertical signal line for each row,
The vertical signal lines are further connected to a horizontal read line sequentially in the horizontal direction and output.

FIG. 12 is a partial block circuit diagram showing a circuit configuration near a horizontal read line of a conventional amplification type solid-state imaging device. The amplification type solid-state imaging device 70 shown in FIG. 12 has a pixel matrix 1 in which amplification type photoelectric conversion pixels are arranged in rows and columns. Each pixel signal line of the pixel signal line group 2 is commonly connected to the amplification type photoelectric conversion pixel in the column direction in the pixel matrix 1, and is connected to the signal transfer switch group QT corresponding to each column in the readout circuit 3. ing. Further, the signal transfer switch group QT is connected to the horizontal read switch group Qh via the vertical signal line group 4. In the read circuit 3, storage capacitors having the other ends grounded are connected to the respective vertical signal lines of the vertical signal line group 4, and the respective storage capacitors constitute a storage capacitor group C in the row direction.
A horizontal read line 6 for sequentially transferring and outputting signal charges in the row direction is commonly connected to the output terminal side of the horizontal read switch group Qh. At each control gate end of the signal transfer switch group QT,
Clock φT is commonly input. On the other hand, the control gate terminals of the horizontal read switch group Qh are connected to the output terminals of the AND circuits in the AND circuit group A, respectively. A clock φGH is commonly input to each AND circuit, and a corresponding control output from the horizontal shift register 8 is input.

In the amplification type solid-state imaging device 70, first, a clock φT is input to the control gate terminal of each signal transfer switch, and each signal transfer switch of the signal transfer switch group QT is turned on. , Pixel matrix 1
The signal charge output from the photoelectric conversion pixels in the row selected in (1) is stored in the storage capacitor group C via the vertical signal line group 4. During this time, the horizontal read switch group Qh is all kept in the off state.

Thereafter, the signal transfer switch group QT is held in the off state by turning off the clock φT, and the signal charges stored in the storage capacitor group C are sequentially transferred by the control output from the horizontal shift register 8 to the horizontal read lines 6 and Output through the output amplifier 7. Note that the horizontal read switch group Qh
In each of the horizontal read switches, the vertical signal line group 4 side is a drain and the horizontal read line 6 side is a source.

Here, a horizontal read operation of the signal charges stored in the storage capacitor group C to the horizontal read line 6 will be described with reference to a timing chart shown in FIG. Here, the horizontal reading operation for eight columns will be described. First, the horizontal shift register 8 sequentially outputs high-level clocks φH1 to φH8 along the row direction. The control output of the horizontal shift register 8 and the clock φH are input to the AND circuit group A, that is, the AND circuits A1 to A8. Each of the AND circuits A1 to A8 is a control output φH of the horizontal shift register 8.
AND of clocks φGH and φGH (φg1 to φg
8) are output to the control gate terminals of the horizontal read switches Qh1 to Qh8, respectively. As a result, the horizontal read switches Qh1 to Qh8 are sequentially turned on, and the storage capacitors C1
To C8 are sequentially transferred to the horizontal read line 6
And the output signal Vout is output from the output amplifier 7. Each time a signal charge corresponding to one photoelectric conversion pixel is output, the clock φRSTH is reset by the reset switch Q
The signal is input to the control gate terminal of R, and the potential of the horizontal read line 6 is reset so that the output of the signal charge of each photoelectric conversion pixel unit does not interfere.

In this amplification type solid-state imaging device, the peripheral circuit portion of the pixel matrix 1 is covered with a light-shielding aluminum 71,
Malfunction due to light incidence is prevented.

[0008]

By the way, in the conventional amplification type solid-state imaging device shown in FIG. 12, a parasitic capacitance CH exists in the horizontal read line 6, and various problems occur due to the existence of the parasitic capacitance CH.

First, the value of the parasitic capacitance CH is: (1) the capacitance by the horizontal read line 6 (2) the capacitance by the output amplifier 7 (3) the capacitance of the source of one horizontal read switch Qh1 × the capacitance of the horizontal read switch group Qh. Total number (4) Horizontal read line 6 and one horizontal read switch Qh
1 × capacity of wiring connecting to horizontal readout switch group Qh
Is the sum of the total number of

Further, as described above, in the conventional amplification type solid-state imaging device, since the peripheral circuit portion of the pixel matrix 1 is covered with the light-shielding aluminum 71, the "capacitance due to the horizontal read line 6" shown in (1) and ( The “capacity of the wiring connecting the horizontal read line 6 and one horizontal read switch Qh1 × the total number of the horizontal read switch group Qh” shown in 4) means that the conductive layer of each wiring is formed with the underlying silicon. And a capacitance formed between the conductive layer and the light-shielding aluminum 71.

Therefore, when the signal charges stored in the storage capacitor group QT are read out to the horizontal read line 6 by sequentially turning on the horizontal read switches of the horizontal read switch group Qh,
Due to the above-mentioned parasitic capacitance CH of the horizontal read line 6, a loss of the output signal Vout occurs.

For example, assuming that the value of each storage capacitor of the storage capacitor group C is “Ct” and the value of the capacitance of the parasitic capacitance CH of the horizontal read line 6 is “Ch”, the signal charge of the storage capacitor QT1 becomes
The capacity is divided into the capacity Ct and the capacity Ch, and Ct / (Ct + C
h) It is input to the output amplifier 7 after being reduced by a factor of two. Therefore, in order to reduce the charge loss, the parasitic capacitance CH
Is preferably smaller.

Further, if the value of the capacitance Ch of the parasitic capacitance CH becomes large, there is a problem that a signal delay is caused and the speed-up of pixel reading by the amplification type solid-state imaging device is hindered.

Therefore, the present invention eliminates such a problem.
It is an object of the present invention to provide a high-sensitivity and high-speed amplifying solid-state imaging device by reducing the value of the parasitic capacitance CH of the horizontal read line 6 to eliminate loss of an output signal.

[0015]

According to a first aspect of the present invention, there is provided a plurality of amplifying photoelectric conversion pixels which are arranged in a matrix along a row and column direction and accumulate and amplify signal charges corresponding to optical signals, respectively. A pixel signal line extending along the photoelectric conversion pixels arranged in a column direction and connected to a pixel in each column, and temporarily stores output signals for one row of the photoelectric conversion pixels via the pixel signal lines. A readout circuit having a plurality of capacitors for
A plurality of vertical signal lines connected to the capacitance of the readout circuit, the same number of horizontal readout lines as output terminals for sequentially selecting and outputting signals from the vertical signal lines, and one vertical signal line. In contrast, a plurality of first-stage horizontal switches connected at one ratio, a plurality of horizontal signal lines commonly connected to a plurality of outputs of the first-stage horizontal switches,
A second horizontal switch connected to the book at one ratio and having an output connected to the horizontal read line, a horizontal switch circuit for sequentially connecting the signal of the vertical signal line to the horizontal read line, The output terminal of the horizontal read line is connected to the output terminal side, and the number of output terminals and horizontal read lines is equal to the number of horizontal read line reset means. For this reason, since the parasitic capacitance of the horizontal read line is determined by the number of horizontal switch groups in the second stage, deterioration of signal charges due to voltage distribution can be prevented, and signal charges can be read with high sensitivity and high speed. Since the horizontal read line reset processing is performed by the horizontal read line reset means, signal charges can be read with higher sensitivity.

According to a second aspect of the present invention, there is provided a horizontal shift register for sequentially generating a control signal in the horizontal direction in synchronization with a horizontal clock, and a logic circuit for performing a logical operation on an output of the horizontal shift register and a predetermined control clock, A signal logically operated by the logic circuit is used as a control signal for driving the first-stage horizontal switch and the second-stage horizontal switch. For this reason, the logic circuit uses the clock used when outputting the signal charge to the horizontal read line using only the first-stage horizontal switch as it is, and uses the first-stage horizontal switch and the second-stage horizontal switch. The horizontal switch can be controlled.

In a third aspect based on the second aspect, the logic circuit receives a control signal of the horizontal shift register and the predetermined control signal clock as inputs and outputs an output signal corresponding to the first stage. And an AND circuit group composed of a plurality of AND circuits for supplying to respective control terminals of the horizontal switch group, and an AND circuit group provided corresponding to the second-stage horizontal switch group. And an OR circuit group comprising a plurality of OR circuits each of which receives a control signal of the horizontal shift register and supplies an output signal to each control terminal of the corresponding horizontal switch group of the second stage. Features. Therefore, similarly to the second invention, the AND circuit group and the OR circuit group use the clock used when outputting the signal charge to the horizontal read line using only the first-stage horizontal switch as it is. ,
Control of the first-stage horizontal switch and the second-stage horizontal switch can be realized.

In a fourth aspect based on the first aspect, the number of the first-stage horizontal switches connected to one second-stage horizontal switch and forming one group is a horizontal read line. It is characterized in that the number is smaller than the number of second-stage horizontal switches connected to one switch. The fourth invention expresses an appropriate number of the second-stage horizontal switch groups in the first invention, and the operation is the same as that of the first invention.

In a fifth aspect based on the first aspect, the number of the first-stage horizontal switches connected to one horizontal switch of the second stage and forming one group is two;
It is characterized by four or eight. The fifth invention expresses an appropriate number of the second-stage horizontal switch groups in the first invention, and the operation is the same as that of the first invention.

In a sixth aspect based on the first to third aspects, the second stage is connected to one horizontal switch and connected to one group of the first stage horizontal switches. While outputting the output of the vertical signal line sequentially,
A second stage horizontal switch connected to a group of the first stage horizontal switches to be read next is turned on. As a result, a step of an output signal is generated due to a floating state of a horizontal signal line in a group of the first horizontal switches to be read next, and a vertical stripe of an image is generated due to a step of the output signal. Can be reliably prevented.

According to a seventh aspect based on the first to third aspects, the second horizontal switch is connected to one of the second horizontal switches and is connected to the first horizontal switch which forms one group. When the output of the vertical signal line is started, the second stage horizontal switch connected to the first stage horizontal switch group to be read next is turned on. According to the seventh invention, similarly to the sixth invention, the generation and output of the step of the output signal caused by the horizontal signal line in the group of the first-stage horizontal switch to be read next is in a floating state. It is possible to reliably prevent the occurrence of vertical stripes in an image due to a signal step.

In an eighth aspect based on the first aspect, the ring type shift register operates in synchronization with the horizontal clock, and operates in synchronization with the output of the ring type shift register, and the number of stages is reduced to an integral number. A thinned horizontal shift register, wherein the number of stages of the ring type shift register and the ratio of thinning out the number of stages of the horizontal shift register are connected to one horizontal switch of the second stage to form one group. The control terminals of the horizontal switches, which are equal in number to the first-stage horizontal switches to be formed and have the same output order in each group of the first-stage horizontal switches, are commonly connected between the groups and the corresponding ring And the control terminal of the second-stage horizontal switch is connected to the output of the horizontal shift register in which the number of stages is thinned out. To. This eliminates the need for a logic circuit that generates a new clock for controlling the first-stage and second-stage horizontal switches in each group, for example, a large number of AND circuit groups and OR circuit groups. Peripheral circuits required for a charge reading operation can be simplified. Further, similarly to the first invention, since the number of the second-stage horizontal switches connected to the horizontal read line is small, the signal charges can be read with high sensitivity and at high speed.

According to a ninth aspect, in the first aspect, the semiconductor device has at least a plurality of horizontal read lines and output terminals,
The horizontal switch group of the second stage and the horizontal switch group of the second stage are formed in separate wells, and each horizontal switch group and the well are shielded from light by a light shielding film of a metal layer other than the first layer. A region of the underlying substrate is formed between the wells, and at least a part of the region of the underlying substrate is removed of a light-shielding film made of a metal layer other than the first layer. The signal wiring is bridged between the horizontal switches in the tier by using a metal layer of the same layer as the light-shielding film and in a portion of the base substrate where there is no light-shielding film. According to the ninth aspect, a light-shielding film is formed on each element and well in the peripheral circuit of the amplification type solid-state imaging device. Therefore, even if a two-layer aluminum process is used, signal deterioration is small, and the peripheral circuit due to light irradiation is reduced. Adverse effects on the body can be eliminated.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an amplification type solid-state imaging device 10 according to a first embodiment of the present invention. In FIG. 1, this amplification type solid-state imaging device 10
It has a pixel matrix 1 in which amplification-type photoelectric conversion pixels are arranged in rows and columns. The arrangement of this pixel matrix 1 is
(M, n) matrix. Pixels in each column of the pixel matrix 1 are commonly connected to corresponding pixel signal lines of the pixel signal line group 2, and each pixel signal line is connected to the signal transfer switch group QT.
Connected to the corresponding signal transfer switch.

The read circuit 3 has the above-described signal transfer switch group QT, and the number of each signal transfer switch constituting the signal transfer switch group QT is set corresponding to the number of columns of the pixel matrix 1. FIG. 1 shows twelve signal transfer switches QT1 to QT12, but the actual pixel matrix 1 has several hundred or more columns, and the corresponding signal transfer switches A number of signal transfer switch groups QT are required. For example, V
GA (Video Graphics Array) class is about 700,
1 for SVGA (Super Video Graphics Array) class
About 300, HDTV (High Definition Television)
In the class, the number of columns is about 2000, and it is necessary to arrange the signal transfer switch group QT having the number of signal transfer switches corresponding to these. In FIG. 1, the signal transfer switches QT1 to QT12 are part of the signal transfer switch group QT.
Is shown.

The output terminals of the signal transfer switches QT1 to QT12 are connected by a vertical signal line group 4 connecting the input terminals of the first horizontal switches QH1 to QH12 arranged corresponding to the signal transfer switches QT1 to QT12. Connected.
Here, the first-stage horizontal switches QH1 to QH12 are:
A part of the first-stage horizontal switch group QH is formed.

The readout circuit 3 further corresponds to the signal transfer switches QT1 to QT12, and has a storage capacitor C1 for storing signal charges of a selected row sent from the pixel matrix 1.
The storage capacitors C1 to C12 have the other end grounded and one end connected to each vertical signal line of the vertical signal line group 4.

The control gate of each of the signal transfer switches QT1 to QT12 in the read circuit 3 has a clock φT
Are commonly input.

First-stage horizontal switches QT1 to QT12
Are grouped for every four first-stage horizontal switches according to the horizontal reading order of signal charges, and belong to the horizontal reading groups B1 to B3, respectively. For example, the first-stage horizontal switches QT1 to QT4 belong to the horizontal readout group B1.

In each of the horizontal read groups B1 to B3, the first-stage horizontal switches QH1 to QH4, QH5 to QH
8, output terminals of QH9 to QH12 are commonly connected by horizontal signal lines 51 to 53, respectively. The commonly connected horizontal signal lines 51 to 53 are respectively connected to the input terminals of the second-stage horizontal switches Q1 to Q3, and the output terminals of the second-stage horizontal switches Q1 to Q3 are connected to the horizontal read line 6. Connected in common. Here, the second-stage horizontal switch groups Q1 to Q1
Q3 has a drain on the input side and a source on the output side because the medium to be transferred is an electron. Also,
One horizontal switch Q1 to Q3 in the second stage is arranged in each of the horizontal readout groups B1 to B3.

The horizontal shift register 8 outputs to the AND circuit group A a clock group φH for sequentially transferring the signal charges of the selected row of the pixel matrix 1. That is, the clocks φH1 to φH12 correspond to the clocks φH1 to φH1.
2 and are sequentially output to AND circuits A1 to A12 corresponding to. A clock φGH is further commonly input to the AND circuit group A. AND circuits A1 to A1 of AND circuit group A
2 takes the logical product of the clocks φH1 to φH12 and the clock φGH, and outputs the result to the first horizontal switch QH.
1 to GH12.

Each of the horizontal readout groups B1 to B3 has an OR circuit G1 to G3, respectively. The OR circuits G1 to G3 have a clock group φ output from the horizontal shift register 8.
H, that is, clocks φH1 to φH4, φH5 to φH
8, φH9 to φH12 are input, respectively. Each of the OR circuits G1 to G3 receives the input clocks φH1 to φH4,
The logical sum of φH5 to φH8 and φH9 to φH12 is calculated, and the result is output to the second-stage horizontal switches Q1 to Q3, respectively.

Therefore, each of the horizontal readout groups B1 to B3 includes four first-stage horizontal switches QH1 to QH1.
QH4, QH5 to QH8, QH9 to QH12, one second-stage horizontal switch Q1 to Q3, and one OR circuit G1
To G3, four AND circuits A1 to A4, A5 to A8, A
9 to A12.

Note that the number of the horizontal readout group B is a number obtained by adding 1 to a quarter of the number of columns of the pixel matrix 1 or a quarter of the number of columns of the pixel matrix 1.
When the number of columns of the pixel matrix 1 is not divisible by “4”,
This is because the number of the first-stage horizontal switches in the last horizontal readout group may be a number obtained by adding a surplus number to “4”, or may be only the surplus number.

The horizontal read line 6 is connected to an output amplifier 7, and the output amplifier 7 amplifies the read signal charges.
Output from the output terminal T4 as an output signal Vout. The horizontal read line 6 has a reset switch Q with the other end grounded.
R is connected, and the reset switch QR sets the potential of the horizontal read line 6 and the potential of the horizontal signal line 5 in the horizontal read group that is currently performing horizontal read to the ground level by the clock φRSTH input to the control gate terminal from the terminal T3. Reset.

Next, the vertical reading operation of the amplification type solid-state imaging device 10 will be described. First, the clock φT is input to the control gate terminals of the signal transfer switches QT1 to QT12,
The signal transfer switches QT1 to QT12 are turned on.
On the other hand, since the horizontal read operation is not performed while the signal transfer switches QT1 to QT12 are on, the first-stage horizontal switches QH1 to QH12 hold the off state.

Accordingly, from the pixel signal line group 2, signal charges are output from the photoelectric conversion pixels in the row selected in the pixel matrix 1, and the signal charges are output from the signal transfer switch QT.
1 to QT12, and are stored in storage capacitors C1 to C12. As a result, signal charges for one row selected in the pixel matrix 1 are stored in the storage capacitors C1 to C12,
The vertical read operation for one row ends, and thereafter, the horizontal read operation for one row starts. The horizontal read operation for one row will be described with reference to the timing chart of FIG. Note that FIG. 2 illustrates horizontal reading of signal charges stored in the storage capacitors C1 to C8.

In FIG. 2, clocks φH1 to φH8 from horizontal shift register 8 according to the horizontal reading order for one row.
Are sequentially output to AND circuits A1 to A8,
The clocks φH1 to φH4 and φH5 to φH8 are output to the OR circuits G1 to G2.

Each of AND circuits A1 to A8 has a clock φGH and a correspondingly input clock φH1 to φH.
The logical product (φg1 to φg8) with H8 is taken, and the logical product outputs φg1 to φg8 are output to the first-stage horizontal switches QH1 to QH1.
Input to the control gate terminals of QH8.

On the other hand, the OR circuit G1 outputs clocks φH1 to φH1.
The logical sum (φG1) of φH4 is taken and the logical sum output φG
1 is input to the control gate terminal of the second-stage horizontal switch Q1. The OR circuit G2 is connected to the clocks φH5 to φH8.
(ΦG2), and inputs the logical sum output φG2 to the control gate terminal of the second-stage horizontal switch Q2.
Here, since each ON state of the clocks φH1 to φH8 forms a continuous waveform of the ON states of the adjacent clocks φH1 to φH8, the OR circuit G1 performs a logical sum to turn on the clocks φH1 to φH4. One clock φG1 in which the states are continuous is generated and output, and the OR circuit G2 performs a logical sum, thereby generating and outputting one clock φG2 in which the ON states of the clocks φH5 to φH8 are continuous.

Therefore, the logical product outputs φg1 to φg4 from the AND circuits A1 to A4 are sequentially output to the horizontal switch Q of the first stage.
When the first-stage horizontal switches QH1 to QH4 are sequentially turned on after being input to the control gate terminals of H1 to QH4, the signal charges stored in the storage capacitors C1 to C4 are reduced to the first level.
It is output to the horizontal signal line 51 via the horizontal switches QH1 to QH4 of the stage, and during this time, the logical sum output φG1 of the OR circuit G1 is further input to the control gate end of the horizontal switch Q1 of the second stage, Since the second-stage horizontal switch Q1 is in the ON state, the signal charge is output to the horizontal read line 6 and output as the output signal Vout via the output amplifier 7.

Similarly, the logical product outputs φg5 to φg8 from the AND circuits A5 to A8 are sequentially input to the control gate terminals of the first-stage horizontal switches QH5 to QH8, and
When the first-stage horizontal switches QH5 to QH8 are sequentially turned on, the signal charges accumulated in the storage capacitors C5 to C8 are output to the horizontal signal line 52 via the first-stage horizontal switches QH5 to QH8. Further, the logical sum output φG2 of the OR circuit G2 is input to the control gate terminal of the second-stage horizontal switch Q2, and the second-stage horizontal switch Q2 is turned on. Horizontal read line 6
And output as an output signal Vout via the output amplifier 7.

Here, the clock φRSTH is input to the control gate terminal of the reset switch QR, and the reset switch QR sets the potential of the horizontal read line 6 and the horizontal signal line 5 in the horizontal read group B from which the reading is being performed to the ground. Since the signal charges are reset to the level, interference between signal charges sequentially output from the horizontal read line 6 is prevented.

Therefore, the horizontal read line 6 has the first-stage horizontal switch group QH corresponding to all one row of signal charges.
Are not connected, but the second-stage horizontal switch group Q
Since only these are connected, the parasitic capacitance to the horizontal read line 6 is drastically reduced. That is, “(source capacity of one horizontal read switch Qh1) × (total number of horizontal read switch groups Qh)” in the above item (3) is “(source capacity of one second-stage horizontal switch Q1) × (second-stage)”. Horizontal switch Q
The total number of the horizontal read switch group Qh × the capacitance of the wiring connecting the horizontal read line 6 and one horizontal read switch Qh1 in the above item (4) is “the total number of horizontal read lines 6 and one horizontal read switch Qh1”. "Capacity of wiring connecting second-stage horizontal switch Q1 x total number of second-stage horizontal switch group Q".

As a result, the parasitic capacitance of the horizontal read line 6 is drastically reduced, so that the charge distribution of the signal charge to be read horizontally to the parasitic capacitance is reduced, so that the loss of the signal charge is extremely reduced. Reading is also possible.

The signal charge readout operation by the above-described amplification type solid-state imaging device 10 is performed by the clocks φH, φGH, φ used in the conventional amplification-type solid-state imaging device 70 shown in FIG.
It is realized using only T and φRSTH, and does not use a new clock. That is, new clocks φG1 to φG
2 is obtained by the logical sum output by the OR circuit group G, and the clocks φg1 to φg8 are obtained by the logical product output by the AND circuit group A, so that the peripheral circuits of the amplification type solid-state imaging device 10 are not complicated. The amplification type solid-state imaging device 1
0 can be realized.

Also, one pixel selected from the pixel matrix 1
After horizontally reading out all the signal charges for the rows, all the storage capacitor groups C in the readout circuit 3 are reset during the horizontal retrace period,
After that, it is necessary to horizontally read out the signal charges of the next one row selected from the pixel matrix 1, but this reset processing is performed while the signal transfer switch group QT is kept in the off state during the horizontal retrace period. This can be realized by turning on the first-stage horizontal switch group QH, the second-stage horizontal switch group Q, and the reset switch QR.
In this case, the potential of the horizontal signal line 5 is also reset at the same time.

Further, in the above-described first embodiment,
Although the case where the number of the first-stage horizontal switches per one horizontal readout group is four has been described, the number may be other than four. However, in consideration of the effect of reducing the parasitic capacitance, the number of the first-stage horizontal switches per one horizontal readout group is smaller than the number of the second-stage horizontal switches per one horizontal readout line. Preferably, considering the balance between the effect of the variation in the output characteristics of the second-stage horizontal switch and the effect of reducing the parasitic capacitance, the number of the first-stage horizontal switches per one horizontal read group is 2
It is preferable to use any of four, four, or eight.

That is, FIG. 3 shows the parasitic capacitance based on the relationship between the number of the first-stage horizontal switches per one horizontal read group and the number of the second-stage horizontal switches per one horizontal read line. FIG. 4 is a diagram illustrating a relationship with output efficiency. In FIG. 3, by providing a plurality of first-stage horizontal switches, the parasitic capacitance Ch is significantly reduced. However, as the number of horizontal switches in the first stage increases,
The decrease rate of the parasitic capacitance Ch is small, and the number of the first-stage horizontal switches per one horizontal read group is almost equal to the number of the second-stage horizontal switches per one horizontal read line. From the point of view, reduction of the parasitic capacitance cannot be expected so much. The same applies to the output efficiency (Ct / (Ct + Ch)) based on the distribution of the signal charges.
From the vicinity where the number of horizontal switches of the second stage per horizontal read line becomes substantially the same, a large increase in output efficiency cannot be expected. Therefore, it is preferable that the number of first-stage horizontal switches per one horizontal reading group is smaller than the number of second-stage horizontal switches per one horizontal reading line. It is preferable that the number of the horizontal switches in the first stage is 2, 4, or 8. The one shown in the leftmost column of FIG. 3 shows an example of a conventional amplification type solid-state imaging device which is not divided into a first-stage and a second-stage horizontal switch. The values shown in FIG. 3 are values based on the approximate values obtained based on the actual amplification type solid-state imaging device. In general, captured images are compressed and stored by the JPEG method. In JPEG compression, processing is performed by dividing an image into groups of 8 pixels vertically and 8 pixels horizontally. In the first embodiment, for example, when the number of horizontal switches in the first stage per one horizontal read group is set to eight, it can exactly match the group of eight horizontal pixels in the JPEG compression processing. . By doing so, even if a discontinuity occurs in the image at the boundary between the horizontal readout groups, the discontinuity is hidden by the JPEG compression noise, so that the effect of being less noticeable is obtained.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 shows a second embodiment of the present invention.
FIG. 5 is a timing chart illustrating a horizontal read operation of signal charges stored in a storage capacitor group C according to the second embodiment.

The amplification type solid-state imaging device 20 further includes a connection line group L1 in addition to the configuration of the amplification type solid-state imaging device 10. Each connection line of the connection line group L is connected so that the last clock input from the horizontal shift register 8 in the preceding horizontal reading group is input to the OR circuit in the next horizontal reading group. For example, the connection line L1 causes the last clock φH4 input into the horizontal read group B1 to be input to the OR circuit G2 in the horizontal read group B2.
The connection line L2 connects the last clock φH8 input into the horizontal read group B2 to the OR circuit G3 in the horizontal read group B3. Therefore, the connection line group L
Is the number obtained by subtracting 1 from the number of the horizontal readout group B.

The operation of reading and accumulating one selected row from the pixel matrix 1 by the amplification type solid-state imaging device 20 is the same as the operation of the amplification type solid-state imaging device 10 shown in FIG.

The horizontal read operation by the amplification type solid-state imaging device 20 is substantially the same as the operation of the amplification type solid-state imaging device 10, except that the OR circuit group G turns on / off the second-stage horizontal switch group Q. The operation is different. That is, in the configuration of the amplification type solid-state imaging device 10, the operation of reading signal charges from a certain horizontal read group to the horizontal read lines 6 is completed, and the operation of reading signal charges from the next horizontal read group to the horizontal read lines 6 is completed. Is started, the horizontal signal line 5 in the next horizontal readout group is in a floating state,
The potential of the horizontal signal line 5 cannot be predicted. Further, immediately after the second-stage horizontal switch G in the next-stage horizontal readout group is also turned on,
In some cases, the potential of the horizontal signal line 5 has not reached the steady state. Therefore, a step may be generated in the output signal at the time of transition between adjacent horizontal read groups. The generation of the step in the output signal causes vertical stripes in the image, and adversely affects the image quality.

On the other hand, in the amplification type solid-state imaging device 20, the last clock input from the horizontal shift register 8 in the preceding horizontal reading group is transmitted to the OR circuit in the next horizontal reading group by the connection line group L. Since the connection for inputting is performed, a predetermined time before the next horizontal reading group starts the horizontal reading operation, here, one period of the clock input from the horizontal shift register 8,
The second-stage horizontal switch in the next-stage horizontal reading group is turned on (see φG1 and φG2 in FIG. 5), and when the horizontal reading of the next-stage horizontal reading group starts, the next horizontal switch has already been set. The potential of the horizontal signal line 5 in the horizontal reading group of the stage shifts from the floating state to the steady state.

As a result, in the amplification type solid-state imaging device 20, the transition of the horizontal read operation between the horizontal read groups B can be smoothly performed, and the horizontal signal line 5 is floated at the transition between the adjacent horizontal read groups. It is possible to reliably prevent generation of a step in the output signal due to the state and generation of vertical stripes in the image due to the step in the output signal.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 shows a third embodiment of the present invention.
FIG. 7 is a diagram illustrating a configuration of an amplification type solid-state imaging device 30 according to the third embodiment. FIG. 7 is a timing chart illustrating a horizontal read operation of signal charges stored in a storage capacitor group C according to the third embodiment.

The amplifying solid-state imaging device 30 further includes a connection line group LL1 in addition to the configuration of the amplifying solid-state imaging device 10. Each connection line of the connection line group LL performs a logical sum output from an OR circuit in the preceding horizontal reading group and a connection to be input to an OR circuit in the next horizontal reading group. For example,
The connection line LL1 is connected to the OR circuit G in the horizontal readout group B1.
1 is input to the OR circuit G2 in the horizontal readout group B2. Similarly, the connection line LL2 is connected to the OR output G2 of the OR circuit G2 in the horizontal readout group B2.
Is input to the OR circuit G3 in the horizontal readout group B3. Therefore, the total number of the connection line groups LL is a number obtained by subtracting 1 from the number of the horizontal readout group groups B.

The operation of reading and accumulating one selected row from the pixel matrix 1 by the amplification type solid-state imaging device 30 is the same as the operation of the amplification type solid-state imaging device 10 shown in FIG.

The horizontal read operation by the amplifying solid-state imaging device 30 is substantially the same as the operation of the amplifying solid-state imaging device 10, except that the OR circuit group G turns on / off the second-stage horizontal switch group Q. The operation is different. That is, in the configuration of the amplification type solid-state imaging device 10, the operation of reading the signal charge from a certain horizontal read group to the horizontal read line 6 is completed, and the operation of reading the signal charge from the next horizontal read group to the horizontal read line 6 is completed. Is started, the horizontal signal line 5 in the next horizontal readout group is in a floating state,
The potential of the horizontal signal line 5 cannot be predicted. Further, immediately after the second-stage horizontal switch G in the next-stage horizontal readout group is also turned on,
In some cases, the potential of the horizontal signal line 5 has not reached the steady state.

On the other hand, in the amplification type solid-state imaging device 30, a connection for inputting the OR output of the OR circuit in the preceding horizontal reading group to the OR circuit in the next horizontal reading group is made by the connection line group LL. Therefore, a predetermined time before the horizontal readout group of the next stage starts the horizontal readout operation, in this case, four periods of the clock input from the horizontal shift register 8 before the horizontal readout group of the next stage, Of the second stage is turned on (φ in FIG. 5).
G1 and φG2), when horizontal reading of the next horizontal reading group starts, the potential of the horizontal signal line 5 in the next horizontal reading group has already shifted from the floating state to the steady state.

Thus, in the amplification type solid-state image pickup device 30, the transition of the horizontal reading operation between the horizontal reading groups B can be smoothly performed, and the horizontal signal line 5 is floated during the transition between the adjacent horizontal reading groups. It is possible to reliably prevent generation of a step in the output signal due to the state and generation of vertical stripes in the image due to the step in the output signal.

In the second and third embodiments, the predetermined time at which the horizontal reading of the next horizontal reading group is started is set to one cycle of the horizontal shift register 8 or 4 hours.
The predetermined period is a period during which the horizontal signal lines 5 in the next horizontal reading group can reach a steady state at the time when the next horizontal reading group starts horizontal reading. Often, for example, in the second embodiment shown in FIG.
2, a connection line for inputting φH3 to the OR circuit G2 may be further added.

Next, referring to FIGS. 8 and 9, the fourth embodiment of the present invention will be described.
An embodiment will be described. FIG. 8 is a diagram illustrating a configuration of an amplification type solid-state imaging device 40 according to a fourth embodiment of the present invention, and FIG. 9 is a diagram illustrating a storage capacitor group C according to the fourth embodiment.
5 is a timing chart showing a horizontal read operation of signal charges stored in the memory.

The amplifying solid-state imaging device 40 shown in FIG. 8 has a pixel matrix 1, a pixel signal line group 2, a readout circuit 3, a vertical signal line group 4, There is a horizontal readout group BB grouped into four first stage horizontal switches and one second stage horizontal switch. However, the horizontal readout group group BB
In each of the horizontal readout groups, the AND circuit group A and the OR circuit group G are not provided, and a configuration for controlling the first-stage horizontal switch group QH and the second-stage horizontal switch group Q is provided. This is different from the amplification type solid-state imaging device 10 shown in FIG.

That is, the amplification type solid-state imaging device 40 has a ring-type shift register 41, and the ring-type shift register 41 has a clock φR1 corresponding to the number of first-stage horizontal switches in each horizontal readout group. ΦR4 to output. The clocks φR1 to φR4 are input to AND circuits AA1 to AA4, respectively, and the AND circuits AA1 to AA4 output the input clocks φR1 to φR4, respectively.
4 and a clock φGH enabling horizontal reading, and outputs the logical product outputs φr1 to φr4 to the control gate terminals of the first-stage horizontal switches corresponding to the horizontal reading order of the horizontal reading groups BB1 to BB3. Output common. For example,
An AND output φr1 of the AND circuit AA1 is commonly input to the control gate terminals of the first-stage horizontal switches QH1, QH5, QH9,... On each first
The horizontal switches QH1, QH5, QH9,... Of the stage are simultaneously turned on.

The output terminals of the first-stage horizontal switches in each horizontal readout group are commonly connected by a horizontal signal line 5, and are connected to the input terminals of the second-stage horizontal switches in each horizontal readout group. You. Output terminals of the second-stage horizontal switches Q1 to Q3 are commonly connected to a horizontal read line 6.

The horizontal read line 6 amplifies the signal charge read through the second-stage horizontal switch group Q by the output amplifier 7 and outputs the amplified signal charge as the output signal Vout. The horizontal read line 6 is connected to a reset switch QR whose other end is grounded. The reset switch QR is connected to the horizontal read line 6 and a horizontal read group that is currently performing horizontal read by a clock φRSTH input to a control gate end. Of the horizontal signal line 5 is reset to the ground level.

On the other hand, the horizontal shift register 42 is a shift register thinned out by three stages from the horizontal shift register 8, and the clock φR1 of the ring type shift register 41 is used.
In synchronization with the second horizontal switch group Q
Clock group φh is output to each of the control gate terminals.

Next, the vertical read operation of the amplification type solid-state imaging device 40 will be described.
Vertical reading operation is performed in the same manner as in the amplification type solid-state imaging device 10,
The clock φT is input to the control gate terminals of the signal transfer switches QT to QT12, and the signal transfer switches QT1 to QT1
2 is turned on. On the other hand, the signal transfer switches QT1 to QT1
Since the swimming readout operation is not performed while QT12 is on, the first-stage horizontal switches QH1 to QH12 are kept off.

Accordingly, from the pixel signal line group 2, signal charges are output from the photoelectric conversion pixels in the row selected in the pixel matrix 1, and the signal charges are output from the signal transfer switch QT.
1 to QT12, and are stored in storage capacitors C1 to C12. As a result, signal charges for one row selected in the pixel matrix 1 are stored in the storage capacitors C1 to C12,
The vertical read operation for one row ends, and thereafter, the horizontal read operation for one row starts. The horizontal read operation for one row will be described with reference to the timing chart of FIG. Note that FIG. 9 shows horizontal reading of signal charges stored in the storage capacitors C1 to C8.

In FIG. 9, ring type shift register 4
When the clocks .phi.R1 to .phi.R4 are output from the AND circuit 1, the AND circuits AA1 to AA4 take the logical product of the clock .phi.GH and the clocks .phi.R1 to .phi.R4, respectively. Switch QH
1 to QH8. The output order of the logical product outputs φr1 to φr4 is φr1 → φr2 → φ
r3 → φr4 → φr1 →..., the first-stage horizontal switches QH1 and QH5 → the first-stage horizontal switches QH
2, QH6 → First stage horizontal switch QH3, QH7 →
The first-stage horizontal switches are turned on in the order of the first-stage horizontal switches QH4, QH8 → the first-stage horizontal switches QH1, QH5 →.

On the other hand, the horizontal shift register 42 synchronizes the clock φR1 with the clock φh1 → clock φh2.
To output to the control gate terminal of each second-stage horizontal switch group Q in the order of →, the second-stage horizontal switch group Q
Are turned on in the order of the second-stage horizontal switch Q1 → the second-stage horizontal switch Q2 →.

As a result, first, the second-stage horizontal switch Q
The first and first-stage horizontal switches QH1 are turned on, and then the first-stage horizontal switches QH2 to QH4 are sequentially turned on while the second-stage horizontal switch Q1 remains on. Then, when the second-stage horizontal switch Q1 is turned off, the second-stage horizontal switch Q2 is turned on, and the first-stage horizontal switches QH5 to QH8 are sequentially turned on.

Therefore, the signal charges stored in the storage capacitors C1 to C8 are read out to the horizontal read line 6 when both the first horizontal switch and the second horizontal switch are turned on. The signal charges stored in the storage capacitor C8 are sequentially read from the signal charges stored in the storage capacitor C1 in the row direction, and the read signal charges are output to the output amplifier 7.
And output as an output signal Vout.

Here, every time a signal charge corresponding to one photoelectric conversion pixel is output, a clock φRSTH is input to the control gate end of the reset switch QR, and the reset switch QR reads the horizontal read line 6 and performs reading. Since the potential of the horizontal signal line 5 in the horizontal read group BB is reset, interference between signal charges sequentially output from the horizontal read line 6 is prevented.

As described above, also in the fourth embodiment, as in the first to third embodiments, the number of horizontal switches (second-stage horizontal switches) connected to the horizontal read lines is drastically reduced. Therefore, the parasitic capacitance to the horizontal read line 6 becomes very small, and the signal loss due to this parasitic capacitance can be greatly reduced.
Enables high-speed reading.

Also, in the fourth embodiment, the first to third
Since the logic circuits provided in the first embodiment, that is, the AND circuit group A and the OR circuit group G are not required, peripheral circuits required for reading signal charges can be further simplified.

Further, the ring-type shift register 41 and the horizontal shift register 42 can be controlled by well-known driving pulses such as a clock pulse, a start pulse, and a gate control signal of the horizontal shift register. The signal charge reading operation can be performed without adding a pulse, and the peripheral circuit is not complicated.

The parasitic capacitance of the horizontal signal line 5 includes [the wiring capacitance of the horizontal signal line 5], [the drain capacitance of the second horizontal switch group Q], and [the horizontal signal line 5 and the second stage. [The wiring capacitance between the first horizontal switch group Q], [the source capacitance of the first horizontal switch QH] × [the number of the first horizontal switches QH per one horizontal readout group], and [ The wiring capacitance between the horizontal signal line 5 and the first-stage horizontal switch QH] × [the number of first-stage horizontal switches QH per one horizontal readout group], and the storage capacitance group C Are mixed little by little through the parasitic capacitance of the horizontal signal line 5 for each horizontal read group. However, since the wiring constituting this parasitic capacitance is short and the number of horizontal switches is small, This parasitic capacitance can be made sufficiently small. Therefore, the influence of signal charge mixing due to parasitic capacitance can be sufficiently reduced.

In the above-described second to fourth embodiments, similarly to the first embodiment, after all the signal charges of one row selected from the pixel matrix 1 are horizontally read, a horizontal retrace period is performed. During this time, it is necessary to reset all the storage capacitor groups C in the readout circuit 3 and then horizontally read out the signal charges for the next one row selected from the pixel matrix 1. This reset processing is performed during the horizontal blanking period. While the signal transfer switch group QT is kept in the off state, the first stage horizontal switch group QH, the second stage horizontal switch group Q, and the reset switch QR are turned on. Can be. In this case, the potential of the horizontal signal line 5 is also reset at the same time.

Further, in the above-described second to fourth embodiments, the case where the number of the first-stage horizontal switches per one horizontal readout group is four has been described. Similarly, the number may be other than four. However, in consideration of the effect of reducing the parasitic capacitance, the number of the first-stage horizontal switches per one horizontal readout group is smaller than the number of the second-stage horizontal switches per one horizontal readout line. Preferably, considering the balance between the influence of the variation in the output characteristics of the second-stage horizontal switch and the effect of reducing the parasitic capacitance, the number of the first-stage horizontal switches per one horizontal readout group is two, four, or four. Pcs or 8
It is preferable to use any of the above.

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a diagram illustrating a configuration of an amplification type solid-state imaging device 50 according to a fifth embodiment of the present invention. The amplification type solid-state imaging device 50 shown in FIG. 10 has two horizontal read lines 6A and 6B, and converts the signal charges stored in the storage capacitor group C into odd-numbered signal charges and even-numbered signal charges in the row direction. , And the divided signal charges are simultaneously read from the horizontal read lines 6A and 6B based on the configuration of the amplification type solid-state imaging device 10 shown in FIG.

That is, the signal charges stored in the odd-numbered storage capacitors C1, C3, C5, and C7 in the row direction are:
First stage horizontal switches QH1, QH3, QH
5, QH7, the horizontal signal line 5A, and the second-stage horizontal switch QA1 are output to the horizontal read line 6A, and the signal charges are amplified and output by the output amplifier 7A. On the other hand, even-numbered storage capacitors C2, C
4, C6, and C8, respectively.
The horizontal switches QH2, QG4, QH6, QH8 of the stage,
The signal is output to the horizontal read line 6B via the horizontal signal line 5B and the second-stage horizontal switch QB1, and this signal charge is amplified and output by the output amplifier 7B.

The signals input to the control gate terminals of the first-stage horizontal switches QH1 to QH8 and the second-stage horizontal switches QA1 and QB1 are the same as those of the amplification type solid-state imaging device 10 shown in FIG. It is generated by four AND circuits A1 to A4 and one OR circuit G1 in one horizontal read group BR1.

However, corresponding to the two horizontal read lines 6A and 6B, in one horizontal read group BR1, FIG.
Since the switch configuration in one horizontal readout group of the amplification type solid-state imaging device 10 shown in FIG.
The AND output of the AND circuits A1 to A4 and the OR output of the OR circuit G1 are commonly used.

That is, the first stage horizontal switch QH
1, QH2 and QH3, QH4 and QH5, QH6 and QH
7 and QH8 are commonly connected to each other, and the AND outputs of the AND circuits A1 to A4 are input to the control gate terminals of the first-stage horizontal switches QH1, QH3, QH5, and QH7, respectively. It is input to the control gate terminals of the first-stage horizontal switches QH2, QH4, QH6, QH8. The second-stage horizontal switches QA1 and QB1 are commonly connected to each other, and the OR output of the OR circuit G1 is simultaneously input to the control gate terminals of the second-stage horizontal switches QA1 and QB1.

Therefore, a pair of the odd-numbered signal charges and the even-numbered signal charges stored in the storage capacitor group C, for example, the signal charge stored in the storage capacitor C1 and the signal charge stored in the storage capacitor C2. And the horizontal read line 6
A and 6B are output simultaneously.

Therefore, the number of clock groups φH output from horizontal shift register 8 shown in FIG. 10 is half the number of clock groups φH output from horizontal shift register 8 shown in FIG.

The reset switches QRA and QRB
Are connected to the horizontal read lines 6A and 6B, respectively, and the control gate terminals are connected in common. Therefore, the horizontal read lines 6A and 6B and the horizontal read group BR in the horizontal read group BR where the read is performed by one clock φRSTH. The reset of the signal lines 5A and 5B is performed simultaneously.

The configuration of read circuit 3 is the same as that of read circuit 3 shown in FIG. 1, and the vertical read operation is also the same.

Therefore, in the fifth embodiment, since the configuration of the horizontal switch connected to each of the vertical signal lines 6A and 6B is the same as the configuration shown in FIG. 1, the same operation and effect as those of the first embodiment are obtained. Have.

In the fifth embodiment described above, the case where the number of horizontal read lines is two has been described. However, the present invention is not limited to this, and multi-line output in which the number of horizontal read lines is further increased can be performed. In this case, the configuration of the first-stage and second-stage horizontal switches in each horizontal readout group is an overlapping configuration.

With such a multi-line output configuration, it is possible to perform correction using noise called fixed pattern noise (FPN) generated due to the variation of each photoelectric conversion element in the pixel matrix 1. . That is,
The noise output in the dark state and the signal output in the light state in the pixel matrix 1 are output from two horizontal read lines, respectively, and the difference between them is output, whereby a true signal output can be obtained at high speed.

When the method of outputting the noise output in the dark state and the signal output in the bright state by two horizontal read lines is applied to the fifth embodiment, four horizontal read lines are required. .

Incidentally, in the amplification type solid-state imaging device 50 according to the fifth embodiment, a bridging portion 61 of the signal wiring is required. That is, a portion where the horizontal signal line 5B crosses the vertical signal line 4 and a portion where the horizontal read line 6B crosses the input terminal side wiring of the second-stage horizontal switch QA1 are
The bridging portion 61 needs to be formed.

In this case, in order to reduce the signal deterioration in the bridging portion 61, it is preferable that the signal wiring in the bridging portion 61 is made of metal wiring. However, this amplification type solid-state imaging device 50 is formed by a two-layer aluminum process. If
When the first layer aluminum is used for the signal wiring and the second layer aluminum is also used for the bridging wiring in the bridging portion 61, the second layer aluminum is used for the light shielding aluminum 11 in the region of the bridging portion 61.
Can no longer be used as. If the light-shielding aluminum 11 is eliminated, there is a possibility that the amplification type solid-state imaging device 50 malfunctions when strong light enters.

Therefore, in the sixth embodiment, adverse effects on peripheral circuits due to light irradiation when the fifth embodiment is realized are eliminated.

That is, FIG. 11 is a diagram showing a circuit mounting configuration of the amplifying solid-state imaging device 50 shown in FIG. 10 according to the sixth embodiment. In particular, FIG. FIG. 60 shows a schematic AA line cross section of FIG. In FIG. 11, the amplification type solid-state imaging device 60 has a plurality of horizontal read lines 6A and 6B as in the fifth embodiment. The first-stage horizontal switches QH1 to QH8 are formed in the well 62b, and the second-stage horizontal switches GA1,
The QB1 is formed in a well 62a different from the well 62b, and shields the wells 62a, 62b from light with a second layer of metal aluminum 64a, 64b, and a region of a base substrate between the wells 62a, 62b. 63 are formed. At least a part of the region 63 of the base substrate does not have the metal aluminum for light shielding by the second metal layer, and the bridging portion 61 of the signal wiring is formed of the second metal layer. Is formed in a portion where there is no metal aluminum for light shielding corresponding to at least a part of.

As a result, a light-shielding film is formed on each element and well of the peripheral circuit. Therefore, by using a two-layer aluminum process, there is little deterioration of the signal and the adverse effect on the peripheral circuit due to light irradiation is eliminated. , An amplification type solid-state imaging device capable of performing the above-described operations can be realized.

The horizontal reading group group BR can be obtained by providing the connection line group L or LL shown in the second or third embodiment in the fifth and sixth embodiments.
The transition of horizontal read operation between can be performed smoothly,
At the time of transition between adjacent horizontal read groups, the horizontal signal lines 5
Generation of a step in the output signal due to the floating state of A and 5B and generation of vertical stripes in the image due to the step in the output signal can be reliably prevented.

Also, in the fifth and sixth embodiments described above, as in the first embodiment, the pixel matrix 1
After the horizontal readout of all the signal charges of one row selected from the above, all the storage capacitor groups C in the readout circuit 3 are reset during the horizontal retrace period, and then the next one row selected from the pixel matrix 1 is reset. It is necessary to read out the signal charge of
In this reset processing, the first-stage horizontal switch group QH, the second-stage horizontal switch group Q, and the reset switch QR are held during the horizontal retrace period while the signal transfer switch group QT is kept in the off state. It can be realized by turning on. In this case, the horizontal signal lines 5A, 5A
The potential of B is also reset.

Further, in the fifth and sixth embodiments described above, the number of the first-stage horizontal switches per one horizontal read group is eight (four per horizontal read line). Although described, the number may be other than eight (four) as in the first embodiment. However, in consideration of the effect of reducing the parasitic capacitance, the number of the first-stage horizontal switches per one horizontal readout group is smaller than the number of the second-stage horizontal switches per one horizontal readout line. Preferably, in consideration of the balance between the influence of the variation in the output characteristics of the second-stage horizontal switch and the effect of reducing the parasitic capacitance, the number of the first-stage horizontal switches per one horizontal read group is one horizontal read. 2 per line, 4
Or eight.

[0103]

As described above in detail, in the first to sixth inventions, since the parasitic capacitance of the horizontal read line is determined by the number of the horizontal switch groups in the second stage, the signal charge by the voltage distribution And has the advantage that signal charges can be read out with high sensitivity and high speed.
Since the horizontal read line reset processing is performed by the horizontal read line reset means, there is an advantage that signal charges can be read with higher sensitivity.

According to the first to third aspects of the present invention, a horizontal shift register and a logic circuit are further provided, and a signal logically operated by the logic circuit is supplied to the first horizontal switch and the second horizontal switch. Is used as a control signal for driving the first stage, and the clock used when outputting signal charges to the horizontal read line using only the first stage horizontal switch is used as it is, and the first stage horizontal switch is used. The switch and the second-stage horizontal switch can be controlled, and there is an advantage that the configuration of the entire amplification type solid-state imaging device can be simplified.

In the second and third inventions, the second-stage horizontal switches connected to the group of the first-stage horizontal switches to be read next are turned on in advance. Generation of a step in the output signal due to the floating state of the horizontal signal lines in the group of the first-stage horizontal switches read out in the first stage, and generation of vertical stripes in the image due to the step in the output signal. Has the advantage that it can be

In the fourth invention, a logic circuit for generating a new clock for controlling the first and second horizontal switches in each group, for example, a large number of AND circuit groups and OR circuit groups is provided. Since it is not required, it has the advantage that peripheral circuits required for the signal charge readout operation can be simplified, and the second-stage horizontal switch connected to the horizontal readout line as in the first invention. Is small, so that there is an advantage that signal charges can be read out with high sensitivity and high speed.

In the sixth aspect of the present invention, a light-shielding film is formed on each element and well in the peripheral circuit of the amplification type solid-state imaging device. This has the advantage that an amplifying solid-state imaging device that can eliminate adverse effects on peripheral circuits can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an amplification type solid-state imaging device 10 according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a horizontal read operation in the amplification type solid-state imaging device 10 shown in FIG.

FIG. 3 is an explanatory diagram showing a relationship among the number of first-stage and second-stage horizontal switches per one horizontal readout group, parasitic capacitance, and output efficiency.

FIG. 4 is a circuit diagram showing a configuration of an amplification type solid-state imaging device 20 according to a second embodiment of the present invention.

5 is a timing chart showing a horizontal read operation in the amplification type solid-state imaging device 20 shown in FIG.

FIG. 6 is a circuit diagram showing a configuration of an amplification type solid-state imaging device 30 according to a third embodiment of the present invention.

7 is a timing chart showing a horizontal read operation in the amplification type solid-state imaging device 30 shown in FIG.

FIG. 8 is a circuit diagram illustrating a configuration of an amplification type solid-state imaging device 40 according to a fourth embodiment of the present invention.

9 is a timing chart showing a horizontal read operation in the amplification type solid-state imaging device 40 shown in FIG.

FIG. 10 is a circuit diagram showing a configuration of an amplification type solid-state imaging device 50 according to a fifth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of an amplification type solid-state imaging device 60 according to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a circuit configuration near a horizontal read line of a conventional amplification type solid-state imaging device.

13 is a timing chart showing a horizontal read operation of the amplification type solid-state imaging device shown in FIG.

[Explanation of symbols]

10, 20, 30, 40, 50, 60 Amplification type solid-state imaging device 1 Pixel matrix 2 Pixel signal line group 3 Readout circuit 4 Vertical signal line 5 Horizontal signal line 6 Horizontal read line 7 Output amplifier 8, 42 Horizontal shift register 11, 64a, 64b Light-shielding aluminum 41 Ring-type shift register 62a, 62b Well 63 Substrate area A AND circuit group B Horizontal reading group group C Storage capacitor group G OR circuit group QT Signal transfer switch group QH First-stage horizontal switch group Q Second-stage horizontal switch group QR reset switch φT, φH, φGH, φRSTH, φR1 to φR4, φ
h clock L, LL connection line group

Claims (9)

[Claims] 1. A plurality of amplifying photoelectric conversion pixels arranged in a matrix along a row and a column direction, each accumulating and amplifying a signal charge corresponding to an optical signal, and the photoelectric conversion pixels arranged in a column direction And a readout circuit having a plurality of capacitors for temporarily storing an output signal for one row of the photoelectric conversion pixel via the pixel signal line. A plurality of vertical signal lines connected to the capacitance of the read circuit; the same number of horizontal read lines as output terminals for sequentially selecting and outputting signals from the vertical signal lines; A plurality of first-stage horizontal switches connected at a ratio of one to one, a plurality of horizontal signal lines commonly connected to a plurality of outputs of the first-stage horizontal switches, and a single horizontal signal line. Connect the output at one ratio and read the output horizontally. A horizontal switch circuit including a second stage horizontal switch connected to the horizontal line, and sequentially connecting the signal of the vertical signal line to the horizontal read line; and an output connected to the output terminal side of each horizontal read line. Amplifying solid-state imaging devices, comprising: the same number of terminals and horizontal read lines as resetting means for horizontal read lines. 2. A horizontal shift register that sequentially generates a control signal in a horizontal direction in synchronization with a horizontal clock, and a logic circuit that performs a logical operation on an output of the horizontal shift register and a predetermined control clock. 2. The amplification type solid-state imaging device according to claim 1, wherein a signal obtained by performing a logical operation is used as a control signal for driving the first-stage horizontal switch and the second-stage horizontal switch. 3. The logic circuit inputs a control signal of the horizontal shift register and the predetermined control signal clock, and supplies an output signal to each control terminal of the first-stage horizontal switch group corresponding to the control signal. And an AND circuit group including a plurality of AND circuits, and a control signal of the horizontal shift register provided for each of the first-stage horizontal switch groups. 3. An OR circuit group comprising a plurality of OR circuits for supplying an output signal to each control terminal of the corresponding second-stage horizontal switch group. Amplification type solid-state image sensor. 4. The number of the first-stage horizontal switches connected to one second-stage horizontal switch and forming one group is connected to one horizontal read line. 2. The amplifying solid-state imaging device according to claim 1, wherein the number of horizontal switches in the second stage is smaller than the number of horizontal switches. 5. The number of first-stage horizontal switches connected to one second-stage horizontal switch and forming one group is two, four, or eight. The amplification type solid-state imaging device according to claim 1, wherein: 6. In the course of sequentially outputting the outputs of the vertical signal lines connected to one horizontal switch of the second stage and connected to the horizontal switches of the first stage forming one group. The second stage horizontal switch connected to the group of the first stage horizontal switch to be read next is turned on. Amplification type solid-state image sensor. 7. When output of a vertical signal line connected to one horizontal switch of the second stage and connected to the horizontal switch of the first stage forming one group is started,
The amplifier according to any one of claims 1 to 3, wherein a second-stage horizontal switch connected to a group of the first-stage horizontal switches to be read next is turned on. Type solid-state imaging device. 8. A ring-type shift register that operates in synchronization with a horizontal clock, and operates in synchronization with an output of the ring-type shift register,
A horizontal shift register in which the number of stages is decimated to an integral number, and a ratio of decimating the number of stages of the ring type shift register and the number of stages of the horizontal shift register is one for the second horizontal switch. The number of the horizontal switches of the first stage that are connected to each other to form a group is equal to the number of horizontal switches of the first stage, and the control terminals of the horizontal switches in which the output order in each group of the first stage of horizontal switches is the same are common to the groups. Connected to a corresponding output of the ring-type shift register, wherein a control terminal of a second-stage horizontal switch is connected to an output of the horizontal shift register in which the number of stages is thinned out. The amplification type solid-state imaging device according to claim 1. 9. A horizontal switch group having at least a plurality of horizontal read lines and output terminals, wherein the first-stage horizontal switch group and the second-stage horizontal switch group are formed in separate wells, respectively. And shielding the well with a light-shielding film of a metal layer other than the first layer, forming a region of the base substrate between the wells, and forming at least a part of the region of the base substrate with a metal other than the first layer. The light-shielding film by the layer is removed, and the signal wiring between the first-stage horizontal switch and the second-stage horizontal switch is bridged by using a metal layer of the same layer as the light-shielding film. 2. The amplifying solid-state imaging device according to claim 1, wherein the amplification is performed in a portion where no light-shielding film is provided.