JPS60149270A - Driving method of solid state image pickup device - Google Patents

Abstract

PURPOSE:To increase the anti-blooming magnification ratio without changing the ratio between a photodetecting period and an adverse transfer period, by defining an operation where the electric charge stored to a photodetecting element is transferred to a vertical register and reset as a cycle, and repeating this cycle. CONSTITUTION:Vertical transfer electrodes P1-P4 extending horizontally are formed on the surface of a semiconductor substrate 1 via an insulated film 4. Then transfer control signals phi1-phi4 which are applied to electrodes P1-P4 are all set at the 2nd high voltage Vh2 in a reception mode A. While the signals phi1-phi4 vary between the medium voltage Vm and the low voltage Vl in an adverse transfer mode. The signals phi2 and phi4 are kept at Vl in a read-out state C together with signals phi1 and phi3 increased up to Vh1. Then signals phi2 and phi4 are set at Vl in a reset state E after the forward transfer, and signals phi1 and phi3 are changed to Vh1 from Vm. Then the electric charge stored to a photodetecting element S is transferred to a vertical register 3 and reset. This operation is defined as a cycle and repeated to increase the anti-blooming magnification ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel method for driving a solid-state imaging device, and particularly to a method for driving a solid-state imaging device using a frame transfer method between a light receiving/vertical transfer section and a horizontal transfer section of a vertical interline transfer type solid-state imaging device. A method for driving a hybrid solid-state imaging device that has a structure provided with an accumulation section like that of a solid-state imaging device, and in which a vertical register for transferring signal charges transfers signals and sweeps out unnecessary charges in a time-sharing manner. This is an attempt to improve anti-blooming characteristics and to improve vertical register usage efficiency.

BACKGROUND ART Solid-state imaging devices using charge transfer devices such as charge-coupled devices are broadly classified into frame transfer type and vertical interline transfer type. A frame transfer type solid-state imaging device generally has a light receiving/vertical transfer section and a storage section as main components, and a vertical interline transfer type solid-state imaging device has a light receiving/vertical transfer section and a horizontal transfer section. However, it does not have a storage section like a frame transfer type solid-state imaging device has. Although the vertical interline transfer type solid-state imaging device has advantages such as not needing to increase the number of external terminals even when the number of pixels increases, the image quality of reproduced images deteriorates due to smearing and blooming phenomena. Therefore, a solid-state imaging device is a further development of the vertical interline transfer type by providing a storage section similar to that of the frame transfer type between the light receiving/vertical transfer section and the horizontal transfer section of the vertical interline solid-state image pickup device. It is proposed as such. In this specification, this vertical interline transfer type solid-state imaging device will be referred to as a "hybrid solid-state imaging device."

In such hybrid solid-state imaging devices, attempts have been made to provide an overflow drain region for sweeping out unnecessary charges in order to prevent blooming, but providing an overflow drain region results in a decrease in sensitivity. Therefore, a solid-state imaging device has been developed in which a vertical register that performs vertical transfer is used in a time-sharing manner for the original vertical transfer and for sweeping out unnecessary charges. FIGS. 1 and 2 show a planar structure and a cross-sectional structure of a light receiving element and its surrounding area of such a solid-state imaging device.

In the drawings, reference numerals S1 and S2 denote light receiving elements, which are formed by partially providing an N0 type semiconductor region on the surface of a P type semiconductor substrate l. 2 is a channel stopper formed to surround each light receiving element S1.32;
It consists of a P medium-sized semiconductor region (indicated by a satin pattern in FIG. 1) with a concentration higher than that of the P-type semiconductor substrate l. T1.
T3 is a P-
This is a type read gate section.

3.3 is a vertical register provided corresponding to each vertical column of light-receiving elements, and 0Ml and M3 are vertical registers 3, each consisting of an N-type semiconductor region formed along the vertical transfer direction on the surface of the semiconductor substrate 1. This is a measuring section located at a location corresponding to the readout gate sections T1 and T3.

Pl, T2, T3, T4 are vertical transfer electrodes formed on the surface of the semiconductor substrate l so as to extend in the horizontal direction via the insulating film 4, and Pl, T2, T3 . T
They are arranged in the following order: 4, Pl, T2, T3, T4. Each of the vertical transfer electrodes PL, P2, T3, T4-.phi. is formed not in a band shape but in a comb shape so as not to overlap with the light receiving elements S1, S2, .phi.. Further, T2 and T4 are the lower layers, and Pl and T3 are the upper layers. Then, the read gate section Tl and the vertical register 3
The area M1 is controlled by the vertical transfer electrode Pl, and the read gate part T3 and the measuring part M3 are controlled by the vertical transfer electrode P3.

FIG. 3 shows transfer control signals φl, φ2, φ3, φ in a conventional driving method applied to the vertical transfer electrodes PL, P2, T3, T4 of the solid-state imaging device shown in FIGS. 1 and 2.
4.

In this solid-state imaging device, forward transfer of signal charges and reverse transfer for sweeping out unnecessary charges are performed by a four-phase driving force type. Therefore, the transfer control signals φ1, φ2, φ3, and φ4 become clock pulses that can be driven in four phases in the range of, for example, +5V to -5V during the reverse transfer period and the transfer period.

Also, the vertical register 4 through the read gate parts T1 and T3
The signal charges are read out to the regions Ml and M3 using the transfer electrode P.
This is done by increasing voltages 1 and T3 to, for example, +IOV and lowering transfer electrodes P2 and P4 to -5V. During the light reception period, all of the transfer electrodes P1 to P4 are set to +8, for example, in order to quickly sweep out unnecessary charges in the vertical register 3.
v is set to a high level.

Problems with the Background Art By the way, such a solid-state imaging device has the following problems according to the conventional driving method described above. That is, the signal charge Qs accumulated in the light receiving element during the light receiving period and the unnecessary charge Qm accumulated in the light receiving element S during the reverse transfer period are read out to the vertical register 3, and the signal charge Qs and unnecessary charge Qm are read out.
is transferred by vertical register 3. The unnecessary charge Qm has a correlation with the signal charge Qs, so it does not significantly reduce the quality of the reproduced image to the point where it cannot be seen, but it does not change linearly with the amount of incident light but depends on the transfer frequency. It has knee characteristics, which limits the improvement of anti-blooming characteristics. Specifically, according to the conventional driving method described above, the blooming resistance multiplier is Qs reverse transfer period. Therefore, if we set Qm=Qs, approximately 35
In reality, it is about 30 to 40 times higher, and it was difficult to increase it higher than that. and,
Since the charges transferred by the vertical register 3 include unnecessary charges, the utilization efficiency of the vertical register 3 naturally deteriorates.

Purpose of the Invention Accordingly, the present invention provides a novel method for driving a hybrid solid-state imaging device that can increase the blooming resistance magnification and vertical register usage efficiency without changing the ratio between the light reception period and the reverse transfer period. That is.

Summary of the Invention To achieve the above object, a method for driving a solid-state imaging device of the present invention is a light receiving/vertical transfer method in which light receiving elements are arranged in the horizontal and vertical directions and a vertical register is arranged corresponding to each vertical column of the light receiving elements. In a driving method for a solid-state imaging device, the solid-state imaging device has a structure in which an accumulation section is arranged between a horizontal transfer section and a horizontal transfer section, and each of the vertical registers is used for time-sharing signal transfer and sweeping out unnecessary charges. The generated signal charge is vertically transferred to the storage section side.The transfer control signal applied to the transfer control electrode is used to store the photoelectrically converted signal charge in each light receiving element, and the unnecessary charge existing in each vertical register is de-accumulated. a reverse transfer state in which charges are transferred to the vertical register; a read state in which charges accumulated in each light receiving element during the light receiving state period and the reverse transfer state are transferred from the light receiving element to the vertical register; and a read state in which charges are transferred from the light receiving element to the vertical register. This operation is repeated as one cycle, in which a normal transfer state in which the charge is vertically transferred to the storage section side and a reset state in which the charge accumulated in the light receiving element is transferred to the vertical register in the same manner as the readout state are sequentially realized. It is characterized by:

Embodiments Below, a method for driving a solid-state imaging device of the present invention will be explained in detail according to embodiments shown in the accompanying drawings.

4 and 5 are for explaining an example of the implementation of the method for driving the solid-state imaging device of the present invention, FIG. 4 is a time chart of transfer control signals φ1 to φ4, and FIG. 5 (A) ~
(F) shows potential profiles in each state of the solid-state imaging device. The solid-state imaging device whose transfer is controlled by the transfer control signal shown in FIG. 4 is the same as the solid-state imaging device shown in FIGS. 1 and 2.

(1) At the time of light reception, the transfer control signals φl to φ4 applied to the vertical transfer electrodes P1 to P4 all become the second high voltage Vh2 (for example, +15V). FIG. 5(A) shows the potential profile during this light reception.

Note that the potential difference Δφa between the vertical register 3 and the readout gate portion M of the solid-state imaging device is determined by the impurity concentration difference between the vertical register 3 and the readout gate portion M, the film thickness difference of the insulating film, etc., and the potential difference Δφa is measured. The maximum amount of charge that can be measured by section M, that is, the maximum amount of charge that can be read out QromaX
Determine. Consideration is taken to equalize the lengths of the respective electrodes so that the read maximum charge amount Qromax and the maximum charge amount that can be transferred by the vertical register 3, ie, the maximum charge amount Qremax, do not match.

During this light-receiving period, the readout gate portion T has a shallower potential than the light-receiving element S, and the potential difference during this light-receiving period is assumed to be Δφb. This potential difference Δφ
b determines the maximum signal charge amount Qsmax accumulated in the light receiving element S during the light reception period, but the maximum signal charge amount Qs■a
The potential difference Δφb is set so that x matches the readout maximum charge amount Q romax (and the maximum handling charge amount Qremax). Note that the potential difference Δφb can be set to an appropriate value between the first high voltage Vhl and the second high voltage Vh2. This is because the potential difference between the light-receiving element S and the readout gate section T is equal to the vertical transfer electrodes Pi, P.
This is because the voltage difference Vhl-Vh2 between the voltages applied to the vertical transfer electrodes P1 and P3 during light reception and readout determines the potential difference Δφb.

By the way, when the signal charge QS generated in the light receiving element S during the d light period is less than the maximum signal charge amount Qsmax, the generated signal charge Qs is accumulated in the light receiving element S. When the charge generated in the light-receiving element S becomes larger than the maximum signal charge amount Qswax, the excess charge, that is, the excess charge e- crosses the readout gate section T and enters the measuring section M of the vertical register 3. Flow into. The excess charge e- that has flowed into the measuring section M is absorbed into a drain (not shown) through the vertical register 4.

(2) Reverse transfer At the time of reverse transfer, the transfer control signals φ1 to φ4 are at intermediate voltage Vm(
This is a four-phase drive lock pulse that varies between a low voltage Vt (for example, +5V) and a low voltage Vt (for example, -5V). Note that this clock pulse is omitted in Figure 1, and the charge remaining in the vertical register 3 (
Unnecessary materials) are transferred to a drain region (not shown) and swept out. FIG. 5(B) shows a potential profile at the end of this reverse transfer, and the potential of the read gate portion T during reverse transfer is made to be shallower than the potential during light reception. Also during this reverse transfer period, a charge Q rri '' is generated in the light receiving element S, and the unnecessary charge Qm' generated during the reverse transfer period is accumulated in the light receiving element S together with the signal charge Qs. Unlike the signal charge Qs, the charge Qm' does not vary linearly with the amount of incident light, but has a knee characteristic that depends on the transfer frequency.

(3) When the read reverse transfer period ends, the read state is entered. In the read state, transfer control signal φ2. φ4 maintains the low voltage VL (-5V), and transfer control signals φl and φ3 maintain the intermediate voltage Vm (+5V).
) to this first high voltage vh1 (+17V). FIG. 5(C) shows a potential profile at a point where the transfer control signals φl and φ3 rise to reach the first high voltage vhl.

As the transfer control signals φ1 and φ3 rise from the intermediate voltage Vm (+5V) to the first high voltage vht, the potentials of the vertical register 3 and the read gate portion T become deeper. Then, although the difference Δφl between the potential of the vertical register 3 and the vocative of the successive gate section T does not change, the difference in potential between the gate readout section T and the light receiving element S is changed by the transfer control signals φl and φ3. 1 disappears when the high voltage Vhl is reached. ΔφC is the potential difference between the light receiving element S and the channel stopper 2.

When the potential changes in this manner, the charges Qs and Qm' accumulated in the light receiving element S flow into the vertical register 3 through the read gate section T.

The inflowing charge, that is, the readout charge is Qyr(kQs
+Q m '), and when the signal charge Qs is relatively small, the read charge Qr is stored only in the vertical register 3. However, the signal charge Qs continues to increase and the maximum charge amount Qr
If the amount is about the same as omax, the signal charge Qs will be accumulated in the range of potential difference Δφ1 in the area of the vertical register 3, but the unnecessary charge Qm' will be read out from the vertical register 3 (game) T section and light receiving section. It will be accumulated in a region spanning the element S. In that case, a potential difference Δφ is created between the charge Qr accumulation surface and the channel stopper 2 so that the read charge Qr does not flow onto the channel stopper.
It is necessary to ensure that d(>O) occurs.

(4) The first high voltage Vhl (
After that, the voltage Vhl decreases to the intermediate voltage Vh (+5V). Then, the potentials of the vertical register 3 and the readout game section T are the difference Δ between them.
Both become shallow while maintaining φa. FIG. 5(D) shows that the transfer control signals φ1 and φ3 vary from the first high voltage Vhl to the intermediate voltage Vm.
This shows the potential profile during the process of decreasing to .

In this way, when the potential of the vertical register 3 and the readout gate section T becomes shallow, the unnecessary charge Qm' existing in the area spanning the measuring section M, the readout gate section T, and the light receiving element S of the vertical register 3 is reduced to the vertical register 3. , read gate section T
The light-receiving element S has a deeper potential relative to
, as shown by the arrow, and all unnecessary charges Q m ' are returned into the light receiving element S.

Therefore, it is possible to limit the charge transferred by the vertical register 3 to only the signal charge Qs.

In FIG. 5(D), the two-dot chain line indicates the transfer control signal φl.
, φ3 is reduced to the intermediate voltage Vm.

For perfect metering operation, as shown in the figure, it is necessary to create a potential difference (Δφa+Δφe) that is slightly larger than Δφa between the vertical register 3 and the light receiving element S.

(5) When the forward transfer measurement is completed, a state is entered in which the signal charge Qs is forward transferred. During forward transfer, transfer control signals φl to φ4 are at intermediate voltage Vh.
(+5V),! It becomes a four-phase driving clock pulse that changes in the range of 1-low voltage JEVl (-5 .mu.), and transfers the signal charge Qs to the storage section side. The forward transfer state differs from the above-mentioned reverse transfer state only in that the transfer direction is opposite.

Incidentally, even in this forward transfer state, unnecessary charge Qm' is generated in the light receiving element S. This unnecessary charge Qm' (indicated by diagonal lines) is approximately the same amount as the unnecessary charge Qm' (indicated by satin pattern) generated during the forward transfer period and the reverse transfer period. Therefore, during the normal transfer period, the amount of unnecessary charge accumulated within the light receiving element S reaches 2Qm' (Qm).

(6) When the reset normal transfer period ends, the transfer control signals φ2 and φ4 become the low voltage v1, while the transfer control signals φ1 and φ3 rise from the intermediate voltage Vm to the first high voltage Vhl. That is, the state is the same as the read state described above. FIG. 5(E) shows the potential profile at that time. Therefore, unnecessary charges 2Qm' accumulated in the light receiving element S are swept out into the vertical register 3. In this way, by transferring the unnecessary charge 2Qm' into the vertical register 3, it is possible to prevent the unnecessary charge 2Qm' from being mixed with the signal charge Qs accumulated in the light-receiving element S during the light-receiving period of the next field. This can prevent the occurrence of afterimages.

Thereafter, the transfer control signals φ1 and φ3 are lowered from the first high voltage Vhl to the intermediate voltage Vm, and light reception of the raft-shaped field is started.

Incidentally, if the unnecessary charge 2Q swept into the vertical register 3
In the case of a design in which m' exceeds the readout maximum charge amount Qsmax, the swept out unnecessary charge 2Qm' cannot be contained only in the measuring section 3 of the vertical register 3 and is transferred to the readout gate section T and the light receiving element S. It will also be delayed. Therefore, if the light reception of the next field is performed as it is, the unnecessary charges accumulated in the readout gate section T and the light receiving element S will be transferred to the light receiving element S.
You will end up going inside. Therefore, it is necessary to set the device to the read state and reset it again as shown by the two-dot chain line in FIG. 4, so that the unnecessary charges are swept out into the vertical register 3 again. Note that if it is not possible to flush out the particles by resetting twice, it is necessary to reset the number of times more than twice.

As described above, the driving method shown in FIG. 4 is characterized in that a read state for resetting (/) is created after the end of normal transfer and before the start of light reception. According to such a driving method, the charges read from the light receiving element S to the vertical register 4 through the read gate section T can be divided into signal charges and unnecessary charges, and only the signal charges can be transferred by the vertical register 3. , the utilization efficiency of the vertical register 3 can be improved.

However, in order to make the effect more effective, the following conditions are required. First, it is necessary to make the maximum signal charge amount Qsmax accumulated in the light receiving element S during light reception coincide with the readout maximum charge amount Qromax that can be measured by the measuring section M of the vertical register 3. It is necessary to equalize the lengths of the respective electrodes so that the readout maximum charge amount Qromax directly matches the maximum charge amount Qremax handled by the vertical register 3. Furthermore, the maximum readout charge amount Q rom
Maximum charge amount Qrem handled by ax or vertical register 3
ax is influenced by the potential difference between the vertical register 3 and the read gate section T, and the potential difference is determined by the concentration of the vertical register 3 and the read gate section T, etc.

According to such a driving method, it becomes possible to transfer only signal charges by the vertical register 3, and it is possible to improve the utilization efficiency of the vertical register. Also, in the past, the blooming resistance magnification was .

Qs is the reverse transfer period, which is 35 times longer when Qm and Qs are approximately equal. However, according to the driving method shown in FIG. 4, the blooming resistance magnification can be increased to 3 to 5 times even more than 35 times.

Effects of the Invention As described above, the driving method of the solid-state imaging device of the present invention is a light receiving element vertical transfer method in which the light receiving elements are arranged in the horizontal and vertical directions and a vertical register is arranged corresponding to each vertical column of the light receiving elements. In a driving method for a solid-state imaging device, the solid-state imaging device has a structure in which an accumulation section is arranged between a horizontal transfer section and a horizontal transfer section, and each of the vertical registers is used for time-sharing signal transfer and sweeping out unnecessary charges. By the transfer control signal applied to the transfer control electrode that vertically transfers the generated signal charge to the storage section side,
A light-receiving state in which photoelectrically converted signal charges are accumulated in each light-receiving element, a reverse transfer state in which unnecessary charges existing in each vertical register are transferred to the anti-accumulation part side, a period of the light-receiving state in each light-receiving element, and a reverse transfer state A read state in which the charge accumulated in the previous period is transferred from the light receiving element to the vertical register, a forward transfer state in which the charge from the light receiving element transferred to the vertical register is vertically transferred to the storage section side, and the same as the above-mentioned successive state. Reset to transfer the charge accumulated in the light receiving element to the vertical register
') The feature is that the operation of sequentially realizing the states is one cycle, and this operation is repeated.

Therefore, according to the present invention, since a reset is performed to flush out unnecessary charges in the light receiving element into the vertical register during transition from the normal transfer state to the light receiving state of the next field, the unnecessary charge is accumulated in the light receiving element at the end of the normal transfer. It is possible to prevent the unnecessary charges that are being removed from being mixed into the signal charges accumulated in the light receiving element during the light receiving period of the next field.

By setting the maximum amount of signal charge accumulated in the light receiving element during the light receiving period to an amount corresponding to the maximum amount of charge handled by the vertical register, it is possible to increase the utilization efficiency of the vertical register. This is because if the amount of signal charge accumulated in the photodetector during the light reception period is close to the maximum signal charge amount, unnecessary charges accumulated in the photodetector during the reverse transfer period after light reception will be read out. During this period, the signal charges are read out vertically into a register along with the signal charges, but as soon as the reading ends, they are separated from the signal charges and returned to the light receiving element. Therefore, only signal charges can be transferred using the vertical register. Then, the unnecessary charge returned to the light receiving element is returned to the vertical register by a reset before starting the next field of light reception, together with the unnecessary charge generated during the normal transfer period after the end of reading. Therefore, it is possible to prevent unnecessary charges accumulated in the light receiving element during the forward transfer period and the reverse transfer period from being mixed with the signal charges in the next field, resulting in an afterimage, and it is possible to improve the anti-blooming characteristic.

Another Embodiment FIG. 6 is a pulse chart of transfer control signals showing another embodiment of the solid-state imaging device of the present invention.

In this embodiment, when the normal transfer ends, the transfer control signals φ2 and φ
4 is not lowered to a low voltage v1, but raised from an intermediate voltage Vm to a second high voltage Vh2, and φ2 and φ4 are set to a second high voltage vh.
When the transfer control signals φ1 and φ3 are increased from the intermediate voltage Vm to the first high voltage vht, the unnecessary charge 2 Q m ' stored in the light receiving element S without isolating between the measuring parts M1 and M2. It is slightly different from the embodiment shown in FIG. 4 in that the transfer control signals φ2 and φ4 are lowered to the low voltage v1 and reset when the transfer control signals φl and φ3 are in the state of the first high voltage Vhl. However, in other respects they are exactly the same.

[Brief explanation of the drawing]

Fig. 1 and Fig. 2 show an example of a hybrid type face-piece imaging device, Fig. 1 is a plan view showing a part of the light receiving/vertical transfer section, and Fig. 2 is taken along line A-A in Fig. 1. A cross-sectional view along
FIG. 3 is a pulse chart of a transfer control signal showing an example of a conventional driving method, and FIGS. 4 and 5 (A) to (E) show an example of implementing the method of driving a solid-state imaging device of the present invention. ,
Figure 4 is a pulse chart of the transfer control signal, Figure 5 (A)
-(E) are diagrams showing potential profiles in each state of the solid-state imaging device in one order, and FIG. 6 is a pulse chart of a transfer control signal showing another embodiment of the method for driving the solid-state imaging device of the present invention. Explanation of symbols 3...Vertical register, S--stand light receiving element. P... Vertical transfer electrode, φφ/Φ transfer control signal, Q
Sll...signal charge, Qm, Qm'...unnecessary charge

Claims (2)

[Claims] (1) It has a structure in which a storage section is arranged between a light receiving/vertical transfer section in which light receiving elements are arranged horizontally and vertically and a vertical register is arranged corresponding to each vertical column of light receiving elements, and a horizontal transfer section. In the driving method of a solid-state imaging device in which each of the vertical registers is used for time-sharing signal transfer and sweeping out unnecessary charges, the signal charge generated in each light receiving element is applied to a transfer control electrode that vertically transfers it to the storage section side. A light receiving state in which photoelectrically converted signal charges are accumulated in each light receiving element by a transfer control signal, and a reverse transfer state in which unnecessary charges existing in each vertical register are transferred to the anti-accumulation part side, and each light receiving element is in the above light receiving state a read state in which the charges accumulated during the period and the period before the reverse transfer state are transferred from the light receiving element to the vertical register; a forward transfer state in which the charge from the light receiving element transferred to the vertical register is vertically transferred to the storage section side; and the above-mentioned forward transfer state. A method for driving a solid-state imaging device, characterized in that one cycle is an operation of successively realizing a reset state in which charges accumulated in a light receiving element are transferred to a vertical register in the same way as a read state, and this operation is repeated. (2) Claim 1 characterized in that the number of times the reset state is realized during one cycle of operation is one.
(3) A method for driving a solid-state imaging device according to claim 1, characterized in that the number of times the reset state is realized during one cycle of operation is plural.