JPH0377711B2 - - Google Patents

Info

Publication number
JPH0377711B2
JPH0377711B2 JP57008447A JP844782A JPH0377711B2 JP H0377711 B2 JPH0377711 B2 JP H0377711B2 JP 57008447 A JP57008447 A JP 57008447A JP 844782 A JP844782 A JP 844782A JP H0377711 B2 JPH0377711 B2 JP H0377711B2
Authority
JP
Japan
Prior art keywords
photoelectric conversion
region
charge
accumulation period
bias voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57008447A
Other languages
Japanese (ja)
Other versions
JPS58125974A (en
Inventor
Ikuo Akyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57008447A priority Critical patent/JPS58125974A/en
Publication of JPS58125974A publication Critical patent/JPS58125974A/en
Publication of JPH0377711B2 publication Critical patent/JPH0377711B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14887Blooming suppression

Description

【発明の詳細な説明】 本発明は固体撮像装置の光電変換特性を制御す
る方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling photoelectric conversion characteristics of a solid-state imaging device.

一般に撮像装置においてダイナミツクレンジを
大きくするために光電変換のガンマ特性を変化さ
せる方法は信号処理または光学素子等を用いて行
なわれている。
Generally, in order to increase the dynamic range of an imaging device, a method of changing the gamma characteristic of photoelectric conversion is carried out using signal processing, optical elements, or the like.

従来電荷転送装置特に電荷結合素子(CCD)
を用いた撮像装置の光電変換特性制御方法につい
ては特開昭50−76918号、或いは1976年アイイ−
イ−イ インターナシヨナル ソリツドステート
サーキツト カンフアレンス(IEEE
International Solid−State Circuits
Conference)のダイジエスト オブ テクニカ
ル ペーパー(Digest of Technical Papers)
第38頁乃至第39頁(Method for Varying
Gamma in Charge−Coupled Imagers)に見ら
れるようにCCD撮像装置の光情報を蓄積する電
荷蓄積電極のバイアス電圧を電荷蓄積期間の初期
より終点時の電極電位を大きくすることにより電
荷転送撮像装置のダイナミツクレンジを広げる方
式が提案されている。しかしこの従来の方式にお
いて蓄積期間における最大蓄積電荷量は蓄積電極
電位によつて決まり、最大蓄積電荷量以上の電荷
が発生した場合、その電荷は基板内に掃き出され
る。しかしこの掃き出された過剰電荷は基板内を
拡散して飽和した絵素近傍の電位井戸へ吸収され
る。これは当業者において知られているプルーミ
ング現象で撮像装置としては好ましくない。蓄積
期間の終点近くで蓄積電極の電位を大きくすると
すでに飽和している電位井戸は再び電荷蓄積をす
る。従つて従来の撮像方式による撮像画面を観察
すると光強度の高い入射像ではプルーミング現象
(完全に飽和はしていない)の上に光の強い部分
の画像が現れるため見苦しい撮像画面になる欠点
があつた。
Conventional charge transfer devices, especially charge-coupled devices (CCDs)
For a method of controlling photoelectric conversion characteristics of an imaging device using
IEEE International Solid State Circuits Conference (IEEE
International Solid-State Circuits
Digest of Technical Papers (Digest of Technical Papers)
Pages 38 to 39 (Method for Varying)
As seen in Gamma in Charge-Coupled Imagers), the bias voltage of the charge storage electrode that stores optical information in the CCD imager is increased from the initial potential of the charge storage period to the electrode potential at the end of the charge storage period. A method has been proposed to extend the honey cleanse. However, in this conventional method, the maximum amount of accumulated charge during the accumulation period is determined by the storage electrode potential, and if a charge greater than the maximum amount of accumulated charge is generated, that charge is swept out into the substrate. However, this swept-out excess charge diffuses within the substrate and is absorbed into potential wells near the saturated picture elements. This is a pluming phenomenon known to those skilled in the art and is undesirable for imaging devices. When the potential of the storage electrode is increased near the end of the storage period, the already saturated potential well accumulates charge again. Therefore, when observing an imaging screen using a conventional imaging method, there is a drawback that in an incident image with high light intensity, an image of a portion of strong light appears on top of a pluming phenomenon (not completely saturated), resulting in an unsightly imaging screen. Ta.

本発明の目的はかかる欠点を除いた新規の固体
撮像装置の光電変換特性制御方法を提供すること
にある。
An object of the present invention is to provide a novel method for controlling photoelectric conversion characteristics of a solid-state imaging device that eliminates such drawbacks.

本発明によれば、半導体基板の主面に、前記基
板と反対の導電型を形成してなる接合領域で、前
記接合深さが浅い第1の領域と、前記接合深さが
深い第2の領域を設け、前記第1の領域の主面に
光電変換素子群を形成し、前記第2の領域の主面
に前記光電変換素子群からの信号を読み出す装置
を形成し、前記第1の領域及び第2の領域と前記
半導体基板間に逆バイアス電圧を印加することに
よつて、前記光電変換素子群の各々の電位井戸に
蓄積できる最大電荷量以上の過剰電荷を前記半導
体基板に吸収する固体撮像装置において、電荷蓄
積期間の初期における前記第1の領域の障壁電位
の高さを電荷蓄積期間の終点時の前記障壁電位よ
り低くすることを特徴とする固体撮像装置の光電
変換制御方法が得られる。さらに具体的には、逆
バイアス電圧を蓄積期間の初期より終点時の方を
低くすることにより光電変換特性が制御され、さ
らには逆バイアス電圧を電荷蓄積期間中に順次低
くするように複数回階段状に変化させるか、ある
いは任意の時刻から直線状に低くすることによつ
て固体撮像装置の光電変換特性が制御される。
According to the present invention, in the junction region formed on the principal surface of a semiconductor substrate and having a conductivity type opposite to that of the substrate, the first region has a shallow junction depth and the second region has a deep junction depth. forming a photoelectric conversion element group on the main surface of the first area; forming a device for reading out signals from the photoelectric conversion element group on the main surface of the second area; and a solid that absorbs excess charge into the semiconductor substrate that is greater than or equal to the maximum amount of charge that can be accumulated in each potential well of the photoelectric conversion element group by applying a reverse bias voltage between the second region and the semiconductor substrate. In the imaging device, there is provided a photoelectric conversion control method for a solid-state imaging device, characterized in that the height of the barrier potential of the first region at the beginning of the charge accumulation period is lower than the barrier potential at the end of the charge accumulation period. It will be done. More specifically, the photoelectric conversion characteristics are controlled by lowering the reverse bias voltage at the end of the charge accumulation period than at the beginning of the charge accumulation period, and the reverse bias voltage is lowered in stages multiple times during the charge accumulation period. The photoelectric conversion characteristics of the solid-state imaging device are controlled by changing it linearly or decreasing it linearly from an arbitrary time.

次に本発明による固体撮像装置の光電変換特性
の制御方法について、図面を用いて詳細に説明す
る。なおここでは説明を簡単にするためNチヤネ
ルの半導体装置について述べることにする。
Next, a method for controlling the photoelectric conversion characteristics of a solid-state imaging device according to the present invention will be described in detail with reference to the drawings. In order to simplify the explanation, an N-channel semiconductor device will be described here.

第1図は本出願人による特願55−130517によつ
て提案したインターライン転送方式と呼ばれてい
る固体撮像装置の平面図であり、同一電荷転送電
極群で駆動する複数列の垂直シフトレジスタ10
と、各垂直シフトレジスタの一側に隣接し、且つ
互いに電気的に分離された光電変換部11と、垂
直シフトレジスタと光電変換部間の信号電荷転送
を制御するトランスフアゲート電極12と、各垂
直シフトレジスタの一端に電気的結合した電荷転
送水平シフトレジスタ13と、水平シフトレジス
タの一端に信号電荷を検出する装置14が設けら
れている。
FIG. 1 is a plan view of a solid-state imaging device called an interline transfer method proposed in Japanese Patent Application No. 55-130517 by the present applicant, in which multiple columns of vertical shift registers are driven by the same charge transfer electrode group. 10
, a photoelectric conversion section 11 adjacent to one side of each vertical shift register and electrically isolated from each other, a transfer gate electrode 12 for controlling signal charge transfer between the vertical shift register and the photoelectric conversion section, A charge transfer horizontal shift register 13 electrically coupled to one end of the shift register and a device 14 for detecting signal charges are provided at one end of the horizontal shift register.

第2図は第1図に示す撮像装置における−
線上における断面を模式的に示したものであり、
N型半導体基板15の主面にはこの基板15とp
−n接合を形成し且つ、接合深さが異なる二つの
P型領域22,23が形成されている。またP型
領域22,23の上面には絶縁層16を介して垂
直シフトレジスタの電荷転送電極17、光電変換
部から垂直シフトレジスタへの信号電荷転送を制
御するトランスフアゲート電極18、領域22,
23と異つた導電型層19で構成される光電変換
部が形成されており、光電変換部は隣接する垂直
シフトレジスタと、例えば領域22,23の不純
物濃度より高い不純物層をもつチヤネルストツプ
領域20によつて分離されている。また、光電変
換部以外は例えば金属層21で光遮蔽されてい
る。
Figure 2 shows - in the imaging device shown in Figure 1.
It schematically shows a cross section on a line,
On the main surface of the N-type semiconductor substrate 15, this substrate 15 and p
Two P-type regions 22 and 23 forming a -n junction and having different junction depths are formed. Further, on the upper surfaces of the P-type regions 22 and 23, a charge transfer electrode 17 of the vertical shift register is provided via an insulating layer 16, a transfer gate electrode 18 for controlling the signal charge transfer from the photoelectric conversion section to the vertical shift register, the regions 22,
A photoelectric conversion section is formed of a layer 19 of a conductivity type different from 23, and the photoelectric conversion section is formed between an adjacent vertical shift register and a channel stop region 20 having an impurity layer higher in impurity concentration than the regions 22 and 23, for example. They are separated. In addition, parts other than the photoelectric conversion part are shielded from light by, for example, a metal layer 21.

このようなインターライン転送方式による撮像
装置は、光電変換部11で入射光量に応じて蓄積
した信号電荷を、例えばトランスフアゲート12
を介してそれぞれ対応する垂直シフトレジスタ1
0へ転送する。垂直シフトレジスタへ信号電荷を
転送した後、トランスフアゲートが閉じられ、光
電変換部11は次の周期の信号電荷を蓄積する。
一方、垂直シフトレジスタ10へ転送された信号
電荷は並列に垂直方向に転送し、各垂直シフトレ
ジスタの一水平ライン毎に、水平シフトレジスタ
13に転送される。水平シフトレジスタへ送られ
た電荷は次の垂直シフトレジスタから信号が転送
されて来る間に水平方向に信号電荷を転送し電荷
検出部14から信号として外部に取り出される。
An imaging device using such an interline transfer method transfers signal charges accumulated in the photoelectric conversion unit 11 according to the amount of incident light to the transfer gate 12, for example.
through the corresponding vertical shift register 1
Transfer to 0. After transferring the signal charge to the vertical shift register, the transfer gate is closed, and the photoelectric conversion unit 11 accumulates the signal charge for the next cycle.
On the other hand, the signal charges transferred to the vertical shift register 10 are transferred in parallel in the vertical direction, and transferred to the horizontal shift register 13 for each horizontal line of each vertical shift register. The charge sent to the horizontal shift register is transferred in the horizontal direction while a signal is transferred from the next vertical shift register, and is taken out as a signal from the charge detection section 14 to the outside.

第3図は、本発明に最も関係の深い光電変換部
19の動作をさらに詳細に説明するための図で、
第2図に示す光電変換部の−線上、すなわち
光電変換部の深さ方向の電位分位を示している。
第3図の横軸は深さ方向の距離、縦軸は電位を表
わしている。今第2図に示すチヤネルストツプ領
域20の電位を基準電位、(この場合0ボルト)
とする。N型光電変換部19はトランスフアゲー
ト18の電位をVTG、トランスフアゲートの閾値
電圧をVTとするとVTG−VTの電位でセツトされ
る。またP型領域22と基板15に印加する逆バ
イアス電圧を曲線31で示す低い電圧V1から、
より高い逆バイアス電圧V2にすると曲線32の
ようにP型領域22は完全に空乏化する。光電変
換領域19に光が照射され信号電荷が蓄積する
と、光電変換領域19の電位は曲線32から曲線
33のように小さくなつてゆき最終的には曲線3
4のように光電変換部19とP型領域22の接合
は順方向となり、これ以上光電変換部19で発生
した電荷はP型領域22を介して半導体基板15
へ流れ込む。すなわち第2図で示すトランスフア
ゲート18直下、チヤネルストツプ領域20直
下、および図示していないが光電変換部19を囲
む全ての領域の表面電位より光電変換部19とP
型領域22の接合電位が高くなるように基板半導
体とP型領域22に逆バイアス電圧を印加するこ
とにより、光電変換部19で発生する過剰電荷は
完全に基板半導体へ掃き出すことができ、高輝度
被写体撮像時のプルーミング現象を完全に抑制す
ることができる。また蓄積時間を一定としたとき
の入射光量に応じて光電変換部19に発生蓄積さ
れる信号電荷量とは比例する。すなわちガンマは
1であることも知られている。
FIG. 3 is a diagram for explaining in more detail the operation of the photoelectric conversion unit 19, which is most closely related to the present invention.
It shows the potential distribution on the - line of the photoelectric conversion section shown in FIG. 2, that is, in the depth direction of the photoelectric conversion section.
In FIG. 3, the horizontal axis represents distance in the depth direction, and the vertical axis represents potential. Now, the potential of the channel stop region 20 shown in FIG. 2 is the reference potential (in this case, 0 volts).
shall be. The N-type photoelectric conversion section 19 is set at a potential of V TG -V T , where the potential of the transfer gate 18 is V TG and the threshold voltage of the transfer gate is V T . Further, from the low voltage V 1 shown by the curve 31, the reverse bias voltage applied to the P-type region 22 and the substrate 15 is
When a higher reverse bias voltage V 2 is applied, the P-type region 22 is completely depleted as shown by a curve 32. When the photoelectric conversion region 19 is irradiated with light and signal charges are accumulated, the potential of the photoelectric conversion region 19 decreases from curve 32 to curve 33, and finally reaches curve 3.
4, the junction between the photoelectric conversion section 19 and the P-type region 22 is in the forward direction, and any more charges generated in the photoelectric conversion section 19 are transferred to the semiconductor substrate 15 via the P-type region 22.
flows into. In other words, the photoelectric conversion section 19 and the P
By applying a reverse bias voltage to the substrate semiconductor and the P-type region 22 so that the junction potential of the type region 22 becomes high, excess charges generated in the photoelectric conversion section 19 can be completely swept out to the substrate semiconductor, resulting in high brightness. It is possible to completely suppress the pluming phenomenon when photographing a subject. Furthermore, the amount of signal charge generated and accumulated in the photoelectric conversion section 19 is proportional to the amount of incident light when the accumulation time is constant. That is, it is also known that gamma is 1.

次に、P型領域22と基板15に印加する逆バ
イアス電圧を曲線34で示す高い電圧V2から低
いバイアス電圧V3にすると、光電変換部の深さ
方向の電位分布は曲線35のようになる。すなわ
ち、曲線35の状態では曲線34の状態に比べ
て、光電変換部19にさらに多くの信号電荷が蓄
積可能である。このことは、P型領域22と基板
15に印加する逆バイアス電圧を適切に変化させ
ることにより、光電変換部19に蓄積される最大
電荷量を任意に制御できることを示している。た
だし曲線35の状態においても、ブルーミング現
象を抑制するためには、光電変換部19を囲む全
ての領域の表面電位より光電変換部19とP型領
域22の接合電位の方が高くなるように、前記逆
バイアス電圧を選ばねばならない。
Next, when the reverse bias voltage applied to the P-type region 22 and the substrate 15 is changed from the high voltage V 2 shown by the curve 34 to the low bias voltage V 3 , the potential distribution in the depth direction of the photoelectric conversion section becomes as shown by the curve 35. Become. That is, in the state of curve 35, more signal charges can be accumulated in the photoelectric conversion unit 19 than in the state of curve 34. This shows that by appropriately changing the reverse bias voltage applied to the P-type region 22 and the substrate 15, the maximum amount of charge accumulated in the photoelectric conversion section 19 can be arbitrarily controlled. However, even in the state of curve 35, in order to suppress the blooming phenomenon, the junction potential between the photoelectric conversion section 19 and the P-type region 22 is set higher than the surface potential of all the regions surrounding the photoelectric conversion section 19 The reverse bias voltage must be selected.

次に、前述した光電変換部に蓄積される最大電
荷量が任意に制御できる機能を使つて、光電変換
特性を制御する方法について説明する。まず、第
4図は前記P型領域22と基板15間に印加すべ
き逆バイアス電圧の変化を示す図で、電荷蓄積期
間の初期では第3図に示す電圧V2に保持されて
いるが、蓄積期間の途中の任意の時刻t1で同図の
実線で示すごとく前記電圧V2よりも低い電圧V3
に変化する。第5図は第4図に示す逆バイアス電
圧が印加されたときに光電変換部19に蓄積され
る電荷量と蓄積時間の関係を示す図で、逆バイア
ス電圧V2、V3のそれぞれに対応して蓄積されう
る最大電荷量をQ2、Q3としている。また曲線5
0,51,52はそれぞれ異なる入射光量に応じ
て蓄積される電荷量の時間変化を示すものであ
り、それぞれの傾きが入射光量に対応している。
すなわち傾きが大きいほど入射光量が大きいこと
を示している。同図において、曲線50に示す入
射光量以下の光照射に対しては、入射光量と蓄積
電荷量は比例している。すなわちガンマは1であ
る。ところが曲線50と51の間の入射光量に対
する蓄積電荷量は、最大電荷量Q2で一旦飽和し
たのち、時刻t1以降で再び蓄積が開始され、蓄積
期間の終了時刻t2で最大電荷量Q3以下の電荷量と
なる。このことは、入射光量に対する蓄積電荷量
の割合が、曲線50に示す入射光量以下の場合に
比べて圧縮されていることを示している。次に、
曲線51に示す入射光量以上の光照射、例えば曲
線52に対する蓄積電荷量は、最大電荷量Q3
必ず飽和する。以上に述べた入射光量と蓄積電荷
量の関係をまとめると第6図の実線のごとくな
る。ここでは比較のため、従来の光電変換特性を
破線で示している。同図に示すごとく、本発明に
よる光電変換制御方法によれば、入射光量に対し
て蓄積電荷量が圧縮された領域60が存在するた
め、撮像可能な入射光量範囲を拡大することがで
きる。すなわち、複写体コントラスト比が非常に
大きい場合でも、出力される映像振幅は規定値に
抑えられるので、固体撮像装置の後段に設けられ
る映像信号処理回路で白圧縮、白クリツプ等を行
なう必要はない。なお第4図において、逆バイア
ス電圧を蓄積期間の時刻t1から蓄積期間の終了時
刻t2の間で破線で示すごとく直線状に低くして
も、前述したのと全く同様な光電変換特性が得ら
れる。
Next, a method of controlling the photoelectric conversion characteristics using the above-described function that can arbitrarily control the maximum amount of charge accumulated in the photoelectric conversion section will be described. First, FIG. 4 is a diagram showing changes in the reverse bias voltage to be applied between the P-type region 22 and the substrate 15. At the beginning of the charge accumulation period, the voltage V2 shown in FIG. 3 is maintained. At any time t 1 during the accumulation period, a voltage V 3 lower than the voltage V 2 as shown by the solid line in the same figure.
Changes to FIG. 5 is a diagram showing the relationship between the amount of charge accumulated in the photoelectric conversion unit 19 and the accumulation time when the reverse bias voltage shown in FIG. 4 is applied, and corresponds to each of the reverse bias voltages V 2 and V 3 . The maximum amount of charge that can be accumulated is Q 2 and Q 3 . Also curve 5
0, 51, and 52 each indicate a time change in the amount of charge accumulated according to a different amount of incident light, and each slope corresponds to the amount of incident light.
In other words, the larger the slope, the larger the amount of incident light. In the figure, for light irradiation below the amount of incident light shown by curve 50, the amount of incident light and the amount of accumulated charge are proportional. That is, gamma is 1. However, the amount of accumulated charge with respect to the amount of incident light between curves 50 and 51 is once saturated at the maximum amount of charge Q2 , and then accumulation starts again after time t1 , and reaches the maximum amount of charge Q at the end time of the accumulation period t2 . The amount of charge is 3 or less. This indicates that the ratio of the amount of accumulated charge to the amount of incident light is compressed compared to the case where the amount of incident light is less than or equal to the amount of incident light shown by curve 50. next,
When the amount of light irradiated is greater than the amount of incident light shown by curve 51, for example, the amount of accumulated charge for curve 52 is always saturated at the maximum amount of charge Q3 . The relationship between the amount of incident light and the amount of accumulated charge described above can be summarized as shown by the solid line in FIG. For comparison, conventional photoelectric conversion characteristics are shown here by broken lines. As shown in the figure, according to the photoelectric conversion control method according to the present invention, since there is a region 60 in which the amount of accumulated charge is compressed with respect to the amount of incident light, it is possible to expand the range of the amount of incident light that can be imaged. In other words, even if the contrast ratio of the copy is very large, the output video amplitude can be suppressed to a specified value, so there is no need to perform white compression, white clipping, etc. in the video signal processing circuit installed after the solid-state imaging device. . In FIG. 4, even if the reverse bias voltage is lowered linearly as shown by the broken line between the time t1 of the accumulation period and the end time t2 of the accumulation period, the same photoelectric conversion characteristics as described above will be obtained. can get.

第7図は到発明の他の実施例を説明するための
図で、P型領域22と基板15間に印加する逆バ
イアス電圧を蓄積期間中の時刻t1とt2とで、実線
で示すごとく2回階段上に変化させるか、あるい
は破線で示すごとく直線状の電圧変化の傾きを2
回変化させている。第5図の説明に従うと、この
場合の入射光量に対する蓄積電荷量の関係は、第
8図に示すように3点の折れ曲がり点a、b、c
ができ、撮像可能な入射光量範囲をさらに拡大す
ることができる。
FIG. 7 is a diagram for explaining another embodiment of the present invention, in which the reverse bias voltage applied between the P-type region 22 and the substrate 15 is shown by solid lines at times t 1 and t 2 during the accumulation period. The slope of the linear voltage change is 2 times as shown by the dashed line.
It has been changed several times. According to the explanation of FIG. 5, the relationship between the amount of accumulated charge and the amount of incident light in this case is as shown in FIG. 8 at three bending points a, b, and c.
This makes it possible to further expand the range of incident light that can be imaged.

以上説明したように本発明によれば、光電変換
素子に蓄積できる最大電荷量以上の過剰電荷逆バ
イアス電圧を使つて半導体基板に吸収する機能を
備えた固体撮像装置において、電荷蓄積期間初期
の逆バイアス電圧を蓄積期間終点時の電圧より大
きくすることにより、ブルーミング現象のない撮
像装置の光電変換特性を任意に制御できる。
As explained above, according to the present invention, in a solid-state imaging device equipped with a function of absorbing excess charge into a semiconductor substrate using a reverse bias voltage that exceeds the maximum amount of charge that can be accumulated in a photoelectric conversion element, a By setting the bias voltage higher than the voltage at the end of the accumulation period, it is possible to arbitrarily control the photoelectric conversion characteristics of the imaging device without the blooming phenomenon.

なお、本発明による撮像装置の駆動において、
再生画像の雑音を少なくするためには、第4図あ
るいは第7図に示す逆バイアス電圧の変化を水平
プランキング期間中で行なわせるのが好ましい。
Note that in driving the imaging device according to the present invention,
In order to reduce noise in the reproduced image, it is preferable to change the reverse bias voltage as shown in FIG. 4 or 7 during the horizontal planking period.

また、本実施例では二次元のインターライン転
送方式撮像装置について説明したが他の方式の二
次元撮像装置または一次元固体撮像装置にも適用
できることは明らかである。
Further, in this embodiment, a two-dimensional interline transfer type imaging device has been described, but it is obvious that the present invention can also be applied to other types of two-dimensional imaging devices or one-dimensional solid-state imaging devices.

さらに、実施例ではNチヤネル型半導体装置に
ついて説明したが各領域の導電型を反対にするこ
とでPチヤネル半導体装置に適用できることは言
うまでもない。
Further, in the embodiment, an N-channel semiconductor device has been described, but it goes without saying that the present invention can be applied to a P-channel semiconductor device by reversing the conductivity type of each region.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は電荷転送装置を用いた撮像装置の平面
図、第2図は第1図に示す−線上の断面図、
第3図は第2図に示す−線上の電位分布模式
図、第4図と第7図は本発明に用いる逆バイアス
電圧の時間変化を示す図、第5図は蓄積時間と蓄
積電荷量の関係を示した本発明の動作を説明する
ための図、第6図と第8図は本発明により得られ
た撮像装置の光電変換特性の一例である。 図において、10は垂直シフトレジスタ、1
1,19は光電変換素子、12,18はトランス
フアゲート電極、13は水平シフトレジスタ、1
4は信号電荷検出装置、15は半導体基板、16
は絶縁層、17は垂直シフトレジスタの電荷転送
電極、20はチヤネルストツプ領域、21は金属
層、22は基板と反対の導電型をもち接合が浅い
領域、23は基板と反対の導電型をもち接合が深
い領域を示している。
FIG. 1 is a plan view of an imaging device using a charge transfer device, and FIG. 2 is a sectional view along the line shown in FIG. 1.
Figure 3 is a schematic diagram of the potential distribution on the line shown in Figure 2, Figures 4 and 7 are diagrams showing time changes in the reverse bias voltage used in the present invention, and Figure 5 is a diagram showing the accumulation time and amount of accumulated charge. FIGS. 6 and 8, which are diagrams for explaining the operation of the present invention showing relationships, are examples of photoelectric conversion characteristics of an imaging device obtained according to the present invention. In the figure, 10 is a vertical shift register, 1
1 and 19 are photoelectric conversion elements, 12 and 18 are transfer gate electrodes, 13 is a horizontal shift register, 1
4 is a signal charge detection device, 15 is a semiconductor substrate, 16
17 is an insulating layer, 17 is a charge transfer electrode of the vertical shift register, 20 is a channel stop region, 21 is a metal layer, 22 is a region with a conductivity type opposite to that of the substrate and has a shallow junction, and 23 is a junction with a conductivity type opposite to that of the substrate. indicates a deep area.

Claims (1)

【特許請求の範囲】 1 半導体基板の主面に、前記基板と反対の導電
型を形成してなる接合領域で、前記接合深さが浅
い第1の領域と、前記接合深さが深い第2の領域
を設け、前記第1の領域の主面に光電変換素子群
を形成し、前記第2の領域の主面に前記光電変換
素子群からの信号を読み出す装置を形成し、前記
第1の領域及び第2の領域と前記半導体基板間に
逆バイアス電圧を印加することによつて、前記光
電変換素子群の各々の電位井戸に蓄積できる最大
電荷量以上の過剰電荷を前記半導体基板に吸収す
る固体撮像装置において、電荷蓄積期間の初期に
おける前記第1の領域の障壁電位の高さを電荷蓄
積期間の終点時の前記障壁電位より低くすること
を特徴とする固体撮像装置の光電変換制御方法。 2 第1の領域及び第2の領域と半導体基板間に
印加する逆バイアス電圧において電荷蓄積期間の
初期より電荷蓄積期間の終点時の方を低くするこ
とを特徴とする特許請求の範囲第1項記載の固体
撮像装置の光電変換制御方法。 3 逆バイアス電圧を電荷蓄積期間中に順次低く
するように複数回階段状に変化させることを特徴
とする特許請求の範囲第2項記載の固体撮像装置
の光電変換制御方法。 4 逆バイアス電圧を電荷蓄積期間中の任意の時
刻から直線状に低くすることを特徴とする特許請
求の範囲第2項記載の固体撮像装置の光電変換制
御方法。
[Scope of Claims] 1. A junction region formed on the main surface of a semiconductor substrate and having a conductivity type opposite to that of the substrate, including a first region with a shallow junction depth and a second region with a deep junction depth. A photoelectric conversion element group is formed on the main surface of the first area, a device for reading out signals from the photoelectric conversion element group is formed on the main surface of the second area, and a photoelectric conversion element group is formed on the main surface of the second area. By applying a reverse bias voltage between the region and the second region and the semiconductor substrate, excess charge exceeding the maximum amount of charge that can be accumulated in each potential well of the photoelectric conversion element group is absorbed into the semiconductor substrate. A photoelectric conversion control method for a solid-state imaging device, characterized in that the height of the barrier potential of the first region at the beginning of a charge accumulation period is lower than the barrier potential at the end of the charge accumulation period. 2. Claim 1, characterized in that the reverse bias voltage applied between the first region and the second region and the semiconductor substrate is lower at the end of the charge accumulation period than at the beginning of the charge accumulation period. A photoelectric conversion control method for a solid-state imaging device as described above. 3. A photoelectric conversion control method for a solid-state imaging device according to claim 2, characterized in that the reverse bias voltage is changed stepwise multiple times so as to be lowered sequentially during a charge accumulation period. 4. The photoelectric conversion control method for a solid-state imaging device according to claim 2, characterized in that the reverse bias voltage is lowered linearly from an arbitrary time during the charge accumulation period.
JP57008447A 1982-01-22 1982-01-22 Photoelectric conversion controlling method of solid- state image pickup device Granted JPS58125974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57008447A JPS58125974A (en) 1982-01-22 1982-01-22 Photoelectric conversion controlling method of solid- state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57008447A JPS58125974A (en) 1982-01-22 1982-01-22 Photoelectric conversion controlling method of solid- state image pickup device

Publications (2)

Publication Number Publication Date
JPS58125974A JPS58125974A (en) 1983-07-27
JPH0377711B2 true JPH0377711B2 (en) 1991-12-11

Family

ID=11693374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57008447A Granted JPS58125974A (en) 1982-01-22 1982-01-22 Photoelectric conversion controlling method of solid- state image pickup device

Country Status (1)

Country Link
JP (1) JPS58125974A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020687A (en) * 1983-07-15 1985-02-01 Nippon Kogaku Kk <Nikon> Electronic still camera
JPS60136158U (en) * 1984-02-20 1985-09-10 ソニー株式会社 semiconductor image sensor
JP3951879B2 (en) 2002-10-04 2007-08-01 ソニー株式会社 Solid-state imaging device and driving method thereof

Also Published As

Publication number Publication date
JPS58125974A (en) 1983-07-27

Similar Documents

Publication Publication Date Title
US4450484A (en) Solid states image sensor array having circuit for suppressing image blooming and smear
Hynecek A new device architecture suitable for high-resolution and high-performance image sensors
US4302779A (en) Methods of reducing blooming in the drive of charge-coupled image sensors
JPS5819080A (en) Solid-state image sensor
EP0186162B1 (en) Solid state image sensor
JPS6369267A (en) Solid-state image sensing device
JPH05137072A (en) Solid-state image pickup device
JPH0414546B2 (en)
JPH04298175A (en) Solid-state image pickup device
JP3878575B2 (en) Solid-state imaging device and driving method thereof
EP0399551B1 (en) Method of Driving a CCD Imager of Frame Interline Transfer Type
US4985776A (en) Method of driving solid-state imaging element
JPH08139303A (en) Method of driving solid-state image pickup
JPH0377711B2 (en)
JPH04268764A (en) Solid-state image sensing device
US5382978A (en) Method for driving two-dimensional CCD imaging device
JPH031871B2 (en)
JPH06113207A (en) Solid-state image pickup device drive method and signal procesing method
JPH0421351B2 (en)
JPH0150156B2 (en)
JP2762059B2 (en) CCD solid-state imaging device and signal processing method thereof
JPS6373658A (en) Solid-state image sensing device
JP2892912B2 (en) Inspection method for solid-state imaging device
JPH03195278A (en) Photoelectric conversion control method for solid-state image pickup device
JPH0525184B2 (en)