JPS61183765A - Data transfer controlling system - Google Patents

Abstract

PURPOSE:To raise the data transfer efficiency by inputting a memory address in which an input/output control of a low data transfer density of an input or an output is executed, and executing a data input/output control basd on this memory address. CONSTITUTION:A data which is outputted by an output device 26 is written in a buffer memory 29 by a DMAC27, and a data whose transfer is requested by an input device 25 is read out of the buffer memory 29 by a DMAC28. Also, a data transfer density of the time of an output by the DMAC28 is high, and a data transfer density by the DMAC27 of the time of an input is low, therefore, a CPU21 controls a data output of a data transfer by the DMAC28, and executes freely a data input of a data transfer by the DMAC27.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The invention relates to an improvement in a data transfer control method in which data input/output control of a memory in which data can be written and read is performed by a direct memory access controller (hereinafter referred to as DMAC). It is also ゛.

□ [Technical background of the invention and its problems] Conventionally, a method is known in which a DMAC is used to control data input to a memory in which data can be written and read. This DMAC transfers a specified number (length) of data from a human-powered device to a memory, regardless of the control unit, in response to a request from the data transfer destination, and notifies the control unit to that effect after the data transfer is completed. . In this way, DM
The AC is busy transferring data because it is not under the control of the control unit. h cooing j1
Buffer 1 memory and FIFO, which are the core 1 possible memory
When data was transferred for Mesori, the following problem occurred. In other words, when the data transfer density of input data and the data transfer density of output data are different, the address where the data is input and the address where the data is output are close to each other, and eventually the data is input. The data will be output after passing the address specified, and invalid data will be transferred.

For example, if you start data input and data output at the same time,
In order to transfer the same number of data, generally more time is required for data input, so data input ends later. In this case, the data transfer density during data input is high. Note that when data transfer requests occur at 1-second intervals and when data transfer requests occur at 2-second intervals, the former case is expressed as having a high data transfer density.

To deal with this, we have developed a method to divide the memory area into several small areas and control data input and output so that they do not occur within the same small area, and to prevent data input and output from exceeding the number of areas. A method of controlling this is adopted.

FIG. 1 is an explanatory diagram of a method of controlling a memory area by dividing it into small areas. In the figure, 1 is a memory in which data can be written and read. This memory 1 has small areas 118, . . . 1 . It is divided into Also,
2a indicates data input to the memory IK, and 2b indicates data output from the memory 1. The control unit assigns a number to each area divided into small areas in this way, and controls input/output using a pointer. For example, the control unit is DM
Give AC the start address and length of small area 11,
It gives a data read command to this small area 11, gives the start address and length of the small area to K, and gives a data write command to this area 18. From now on, the control unit is DMAC2>.

When the data transfer is completed, the pointer is referenced and the small area 1. or subregion 4,
Before the data transfer (data input) regarding the small area ζ is completed, the small area 1. When the data transfer (data output) for the small area 18 is completed, data output is stopped until the data transfer for the small area 18 is completed. After the data transfer regarding small area 4 is completed, the data transfer for small area 1. Data is output from a certain small area 1 (not shown). data input.

However, according to the above method, if either one of the data input/output ends in one small area, only the remaining one of the data input/output is performed, resulting in a disadvantage that the data transfer efficiency deteriorates.

FIG. 2 is an explanatory diagram of a control method using a counter. In the figure, 1 is a memory in which data can be written and read, and 3 is an up/down counter. 4
a indicates a write signal, and 4b indicates a read signal.

The write signal 4a is given to the memory 1, and
The readout signal 4b is given to the UP terminal of the up/down counter 3.
k k +i IP tape 7 M -, J, t'
It is given to the DOWN terminal of yn★3. The up/down counter 3 counts up each time it receives a busy write signal from the UP terminal, and counts down each time it receives a read signal from its DOWN terminal.

The up/down counter 3 outputs a signal 3a when the up/down count is greater than the down count, and outputs a signal 3b when the down count is equal to the up/down count. Signal 38% 3b
is given to DMAC. DMAC uses signal 3at
- When the receiver receives, both data input and output continue, and when the receiver receives signal 3b, only data input is performed.◎ According to this method, data input and output continues until the limit is reached, where invalid data is output due to data transfer. Since one side does not stop, data transfer efficiency does not deteriorate. However, if the capacity of the memory 1 is large, there is a drawback that the circuit configuration of the up/down counter 3 becomes enormous. Furthermore, when the capacity of the memory l is changed, the up-down count 3 changes accordingly.
The drawback was that the frog S limit o had to be changed.

[Purpose of the invention]

The present invention was made in view of the drawbacks of the conventional data transfer control as described above, and its purpose is to avoid deteriorating the efficiency of data transfer, and to prevent data transfer when the memory capacity is large or when the memory capacity is changed. An object of the present invention is to provide a data transfer control method that does not require changing the node square even when there is a problem.

[Summary of the invention]

Therefore, in the present invention, a memory address where data input/output control is being performed for either input or output with low data transfer density is taken in, and based on this memory address, data for data transfer of either input or output with high data transfer density is It is designed to perform input/output control.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawing.

FIG. 3 is a block diagram of a data transfer system employing the method of the present invention. In the figure, -21 is the CPU (central processing unit fi)! show. A main memory device is connected to this CPU 21 via a memory bus 22. CPU21
performs data input/output control based on the program of the flowchart shown in FIG. 4 in the main memory Tauchi. Also,
The CPU 21 is connected via an I10 path 24 to an input device 26, an output device 26, a DMAC 27 for input control, a DMAC 4 for output control, and a buffer 1 memory Q in which data can be written and read.

In this embodiment, the data output by the output device % is transferred to the buffer memory 4 by the DMA C27.
The data input and requested to be transferred by the input device 5 is read out from the buffer 1 memory 29 by the DMAC 28 . Furthermore, since the data transfer density during output by DMA028 is high and the data transfer density by DMA027 during input is low, the CPU 21 controls data output for data transfer by DMAC28 and freely inputs data for data transfer by DMAC27VC. have it done. DMAC
27, the CPU 21 sets the start address of the buffer 1 memory device, and here, the buffer 1 memory is set to 27 for use in the 29 ft backup memory.
The capacity (corresponding to the length) of the memory 29 is set.

In response to a data transfer request from the input device 5, the DMA027 stores the given data in its own register (pointer).
Transfer to the buffer 1 memory 4 address indicated by . Each time data is sequentially given, the DMAC 27 increments the address indicated by its own register by 1, and when the data has been transferred to the highest address of buffer memory 4, it then transfers the data to its own register at the beginning of buffer memory 4. Set the address and start data transfer to the first address of buffer 1 memory 4 again.

On the other hand, when the operation of the DMAC 27 is started, the CPU 21 operates as an acquisition means based on the program shown in the flowchart of FIG.
The MAC 27 reads and captures the address of the buffer memory 29 to which data is being transferred.

Next, in step 102, the CPU 21 selects the address 1 from the above address.
,．． 11- DMA for output control at the end of the pulling axe
The start address and length are set so that data transfer by C28 is performed. This allows the DMA
C28 becomes operational], reads the data in the buffer 1 memory from the start address set by the CPU 21 to the address represented by the length, and transfers it to the output device % via the I10 path 24. During this time, CPU2
1 is the DMA02 for output control in step 103.
8 is completed. When detecting that the data transfer has ended, the CPU 21 returns to step 101 and repeats the subsequent operations. In this way, according to this embodiment, data is always transferred (data output)
Data transfer is possible up to the maximum possible limit, and the data transfer is controlled by simple software, so even if the capacity of the buffer 1 memory is large, the hardware will not become large. , buff 1
Even if the capacity of the memory 4 is changed, there is no need to change the hardware or software.

In this embodiment, the CPU 21 always monitors the end of data transfer by the DMA 028 for output control in step 103, but the CPU 21 always monitors the completion of data transfer by the DMA 028 for output control, but the CPU 21 monitors the end of data transfer by the DMA 028 for output control.
You may also execute the following.

Further, in this embodiment, the data transfer density by the DMAC 28 for output control is higher than the data transfer density by the DMAC 27 for input control, but the present invention can be carried out even in the reverse case. In such a case, the DMAC for input control may be controlled by a program of a flowchart similar to the program of the flowchart of FIG. 4. In addition, if the data transfer density of the DMAC for input control and the data transfer density of the DMAC for output control are arbitrarily high or low, the trap will occur depending on each case. , DMAC' for input control or DMACt for output control enables optimal data transfer.

Furthermore, in the embodiment, a DMAC for input control and a DMAC for output control are independently provided, but in reality, there are DMACs such as 4 channels, and according to this, it is possible to control both input and output with one DMAC. It is.

[Effects of the Invention] As explained above, according to the present invention, data transfer is performed efficiently, and there is no need to change the hardware even when the memory capacity is large or when the memory capacity is changed. It is convenient because there is no

[Brief explanation of drawings]

1 and 2 are diagrams for explaining conventional data transfer control methods, FIG. 3 is a block diagram of a data transfer system employing the data transfer control method of the present invention, and FIG. 4 is a block diagram of a data transfer system employing the data transfer control method of the present invention. It is a flowchart for explaining one example. 21...CPU 23...Main memory 2
5... Input device 26... Output device 27.28
...DMAC29...Buffer 1 memory agent Patent attorney Nori Chika Kensuke (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 4R

Claims (2)

[Claims] (1) In a data transfer control method in which a direct memory access controller performs data input/output control of a memory in which data can be written and read, if either input or output has a low data transfer density, the data input/output control is performed by the direct memory access controller. It has a capture means for fetching a memory address for data transfer which is carried out by the direct memory controller, and based on the memory address fetched by the fetch means, one of the input/output input and output data for data transfer by the direct memory controller having a high data transfer density is selected. A data transfer control method characterized by output control. (2) Perform data input/output control for data transfer with a high data transfer density for either input or output until the memory address is one less than the memory address captured by the capture means, and either input or output has a high data transfer density. 2. The data transfer control system according to claim 1, wherein data transfer is performed freely with low data input/output.