JPS61183751A - Access controlling circuit - Google Patents

Abstract

PURPOSE:To set most suitably the access time of a CPU in accordance with peripheral equipment by controlling a clock of the CPU in accordance with an access time of a peripheral equipment to which access is to be executed. CONSTITUTION:A clock of a CPU10 is supplied from a VCO11 which can control an oscillation frequency by a control signal from the outside. In a RAM12 and a ROM13 which have been placed as peripheral equipment of the CPU10. In a memory address space, when the ROM13 whose access time is longer is selected by chip enable from a chip selector 14, a level converter 15 lowers a frequency of the clock supplied from the VCO11 by a control signal. In this way, the access time of the CPU10 is set in accordance with the access time of the ROM13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an access control circuit, and more particularly to an access control circuit that accesses a peripheral device such as a memory at optimal timing.

[Technical background of the invention and its problems]

Generally, in information processing devices such as computers, the central processing unit (CPU) controls access to peripheral devices 1, such as memory such as RAM and ROM, and various input/output devices (1/, ), and transfers data. There is. R・niM、ROM
.

The CPU's address bus to access the ST.

A part of the address data supplied above is coded by a chip selector, and each piece of address data is placed in the memory address space.

We have given examples of RAM, ROM, and Ilo as objects to be controlled by the CPU, but as the access speed of the CPU becomes faster.

Peripheral device access time is longer than CPU access time 0x1 CPU may not be able to access at normal timing. Therefore, the CPU.

It has a wait function that waits and synchronizes processing until peripheral devices finish processing. This is for stable access to slow controlled objects.

This adds a wait cycle to the CPU to extend the access timing.

The conventional access control circuit using the above wait function is
It is shown in FIG. 4 and will be explained.

In the figure, the operating standard of a CPU 40 is defined by a clock CLK from an oscillator 41. Jin's CPU
40O peripherals ft (!: L te, RAM42.
ROM43-4s is arranged on the t memory address space. The division of this RAM42°ROM43 is CP
The chip selector material that reads the upper bits of the address bus A of U40 outputs the bits individually.

By setting the frequency of the clock CLK from the oscillator 41 to 5 MHz (period: 200 nsec).

The access time of the CPU 40 is 40Qnsec.

Also, the read access time of RAM42 is 3QQn
sec.

The access time of the ROM 43 is assumed to be 450 nsec.

In this case, there is sufficient margin for the CPU 40 to access the RAM 42, but there is a shortage of 50 nsec for the CPU 40 to access the R,0M43. So, when ROM43 is selected.

The wait signal generation circuit TS provides the wait signal WAIT to the terminal WAIT of the CPU 40 to perform the above-described wait operation. In other words, one wait cycle is created for the CPU 40, and the access time is set to 400.
+ 200 = 600 n sec as ROM4
The read access time of 3 is longer than the read access time of ROM4.
Reading data from 3.

Next, let's look at the operation of the above conventional access control circuit.

This will be explained with reference to the timing chart shown in FIG.

The chip selector material decodes the upper bits of the address bus A (FIG. 5C) of the CPU 40 and detects that the ROM 43 has been accessed. Then, during the output period of the read signal RD (FIG. 5d) from the CPU ω.

Chip enable CB2 (fifth
Output Figure e). This chip enable CE2 is applied to the D-type flip 70. of the wait signal generation circuit 6. P (
Since it is applied to the 4500D input (hereinafter referred to as FF), the signal Q (FIG. 5f) is output from the Q output at the rising edge of the clock CLK (FIG. 5b). This signal Q1
is delayed by one clock CLK in the FF 451, and its inverted output signal (FIG. 5f) is obtained from the Q output. When this signal Q and the above signal Q are both ``0'', the wait signal WAIT becomes @O'' (Fig. 5h).

Obtained from ORGATE 452. CPU40 is cycle T!
At the falling edge of the clock CLK (FIG. 5a), this wait signal WAIT is input from the terminal WAIT, and the following one cycle is defined as a wait cycle Tw. Therefore.

The read signal RD is still output from the CPU 40.

The ROM 43 is not accessed. In the latter half of this wait cycle Tw, data is supplied from the ROM 43 to the data bus D (FIG. 5i).

At the falling edge of the clock CLK in the wait cycle Tw, the wait signal WAIT is @1'', so the CPU 40 sets the next cycle as cycle T3. At the timing of the falling edge of this cycle T3,
After 500 ns, the CPU 40 inputs the data supplied from the ROM 43 to the data bus D. Thereafter, the read signal RD becomes @1'm, the cycle Ts ends, and the access operation to the ROM 43 is completed.

As described above, conventional access control circuits can easily
By extending the access time of ROM 40, it is possible to access even ROM 43, which has a slow access time. The access time for Totoro is 600n.
sec, so there is a margin of 150 nsec. That is, although the wait cycle Tw is only 50 nsec short, the CPU 40 can only insert the wait cycle Tw at an integral multiple of the clock CLK, resulting in nearly 150 nsec of wasted waiting time.

This leads to an increase in processing time, so in information processing devices that require extremely high-speed processing.

It had become a serious problem.

[Purpose of the invention]

An object of the present invention is to provide an access control circuit that optimally sets the access time of a CPU according to the access time of a peripheral device to be accessed.

[Summary of the invention]

In this invention, for example, as shown in FIG.
A clock CLK is supplied from the VCO 11 whose oscillation wave number can be controlled by an external control signal Vc, and the CPU
RAM 12.10 is located in the memory address space as a peripheral device of 10. When the ROM 13 with the longer access time is selected among the ROMs 13 by the chip enable CE2 from the chip selector 14, the level converter 1
5 lowers the frequency of the clock CLK supplied from the vCO 11 by the control signal Vc. As a result, C
The above objective is achieved by setting the access time of PU10 to correspond to the access time of the ROM 13.

[Embodiments of the invention]

An embodiment of the access control circuit according to the present invention will be described below with reference to one drawing.

In the circuit diagram of the access control circuit shown in FIG.
The operating standard of Ul0 is defined by the clock CLKK from VCOII whose oscillation frequency is controlled by the control signal Vc. As a peripheral device of this CPU10,
Access time is 300ns and 450ns respectively
ec RAM12. R,0M13 is arranged in the memory address space. This RAM12. The ROM 13 is classified by the chip selector 14 as the chip enable CEI.
, CE2 are output.

These R, AM12. ROM
In order to appropriately set the access time of CPU10 to CPU13, level converter 15 sets chip enable CE2
A control signal Vc whose level is converted is generated to control the oscillation frequency of vcou. The characteristics of this VCOII are as shown in the graph of FIG. 2, and the control signal Vlc is V,
When it is 5MHz, when it is V, it is 4MH! It outputs a clock CLK with a frequency of . Therefore, when the ROM 13 is selected and the chip enable CE2 is 10'', the level converter 15 outputs the final control signal Me.
When a ROM other than ROM 13 is selected, the control signal Vc of vl is set to be output when the chip enable CE2 is 11''.

According to the above, 9. CP when accessing RAM12
The access time of U10 is that the clock CLK is 5MHz.
On the other hand, when accessing R,0M13, the clock CLK is 4MHz, so it takes 400nsec.
00nsec. Therefore, it is possible to obtain the optimum access time of CPU10 according to the access time of the peripheral device to be accessed.

Next, the operation of the above embodiment will be explained with reference to the timing chart shown in FIG.

The chip selector 14 decodes the upper bits of the address bus A (C in Figure 3) of the CPU
Detect that has been accessed. And CPU1
During the output period of the read signal RD from 0 (FIG. 3d).

Chip enable CE2 (third
Output Figure e). This chip enable CB2 is C
To convert the operating clock CLK (FIG. 3b) of PU10 into the control signal VC (FIG. 3f) of supplying VCO 11.

The signal is input to the level converter 15.

In this embodiment, when the ROM 13 is not accessed, that is, when the chip enable CE2 is 1'', the control signal Vc is Vl, so the 5MHz clock CLK is Vl.
Supplied from CO11. Therefore, the access time of CPU10 when ROM13 is not accessed is:

40QnsecK is set. On the other hand, when the ROM 13 is accessed, the control signal Vc becomes vo, fi, VC
A 4 MHz clock CLK is supplied from OII.

Therefore.

Cycle T in which CPU10 accessed ROM13, (
FIG. 3a) From the middle of cQ to the middle of cycle T, the clock CLK is 4 MHz, so the access time of CPU10 is set to 500 nsec. Therefore, R
, 0M13 after an access time of 450 nsec has elapsed, the data output to the data bus D (third diagram) is input to the CPU10 at the falling edge timing of the cycle T1.

As explained above, in the embodiment, when accessing the ROM 13 with slow access time, VCOll
Lower the frequency of the clock CLK of ficPUlo to slow down the operation of CPU10 itself. and,
By setting the access time of the CPU 10 in correspondence with the access time of the ROM 13, optimum access timing without waste is obtained. Therefore.

RAM 12 and ROM 1 with different access times
Even when processing is performed by accessing 3, the processing time does not increase.

In addition, in this embodiment, RAM,
Although ROM is mentioned, the present invention is not limited to this. In addition, by arranging two or more peripheral devices, a clock with a frequency suitable for the access time of each peripheral device is set to V.
It may also be supplied from CO. In this case, a control signal may be generated by converting the levels of a plurality of chip enables using a D/A converter.

〔Effect of the invention〕

According to the present invention, the CPU clock is controlled according to the access time of the peripheral device to be accessed.

Since the access time of the CPU can be optimally set according to the peripheral device, it is possible to shorten the processing time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the access control circuit according to the present invention, FIG. 2 is a graph explaining the operation of a part of the embodiment shown in FIG. 1, and FIG. 3 is a diagram showing the operation of the embodiment. FIG. 4 is a circuit diagram showing a conventional access control circuit, and FIG. 5 is a timing chart explaining the operation of the circuit shown in FIG. 4. 10...CPU 11...vCO Minoru...RAM 13...R,0M 14...Chip selector 15...Level converter agent Patent attorney Nori Chika Kensuke (and 1 other person) 2nd m Figure 3 Figure 5

Claims (1)

[Scope of Claims] A central processing unit whose access time is defined by the frequency of a supplied clock; a plurality of peripheral devices whose access times are controlled by the central processing unit and have different access times; and an access time of the central processing unit. a clock supply means that varies the frequency of the clock that defines the frequency of the clock according to an applied control signal and supplies the clock to the central processing unit; 1. An access control circuit comprising: clock control means for setting by a control signal according to time.