JP4176920B2 - Data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique effective when applied to a peripheral module access method in a microcomputer. For example, the peripheral module access method in a microcomputer in which the frequency of an operation clock of a peripheral module is lower than the frequency of an operation clock of a central processing unit. It is related to effective technology.
[0002]
[Prior art]
In a one-chip microcomputer including a central processing unit (hereinafter referred to as a CPU) and peripheral modules such as a timer circuit, a serial communication interface circuit, and an A-D conversion circuit, in order to reduce power consumption and noise, Some peripheral modules are operated at a lower speed than the CPU by setting the frequency of the operation clock of the peripheral module lower than the frequency of the operation clock of the CPU. In addition, in order to enable transmission and reception of signals between the CPU and the peripheral module having different operating frequencies, a signal is bridged between the CPU bus connected to the CPU and the peripheral bus connected to the peripheral module. Some have a bus control means (bus state controller).
[0003]
[Problems to be solved by the invention]
As described above, in the conventional microcomputer configured to operate the peripheral module at a frequency lower than that of the CPU, the access cycle of the built-in peripheral module by the CPU is determined by the operating frequency of the module. For example, when the CPU performs read access to a peripheral module that operates at an operating frequency that is ¼ of the operating frequency of the CPU, the peripheral module receives the access request from the CPU and can output data before the peripheral module can output data. One cycle is required at the operating frequency, and the CPU reads data during the next one cycle. In addition, even when the CPU performs write access to the peripheral module, the peripheral module requires one cycle at the operating frequency of the peripheral module until it can take in data after receiving an access request from the CPU. Data will be captured in the next cycle.
[0004]
For this reason, the reading and writing of the peripheral module takes at least 2 cycles at the operating frequency of the peripheral module, that is, 8 cycles at the operating frequency of the CPU. In the conventional microcomputer, the CPU cannot perform other processes during this period, leading to a decrease in CPU performance. Here, the reading and writing of the peripheral module means reading and writing of data in registers provided in the peripheral module.
[0005]
The object of the present invention is to reduce the power consumption and noise as described above, and when the peripheral module is operated at a lower frequency than the CPU, the access cycle of the peripheral module increases and the performance of the CPU decreases. Is to prevent it.
[0006]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
[0008]
That is, in a data processing device such as a microcomputer or a microcontroller including at least a CPU (central processing unit) and a peripheral module that operates with an operation clock having a frequency lower than that of the CPU, a CPU bus connected to the CPU; Output from the CPU to the CPU bus when the CPU performs a write access to the peripheral module to the bus state controller that is provided between the peripheral buses connected to the peripheral module and bridges signals between the two buses. And at least one write buffer for receiving and holding the address signal and the data signal.
[0009]
According to the above means, if the CPU outputs the write command and address and data of the peripheral module, then the bus state controller decodes the command and address to form and output a signal for the peripheral module. Since the bus cycle end signal is returned to the CPU, the CPU can perform other processing after outputting the write command, address, and data of the peripheral module. As a result, the throughput of the CPU is improved.
[0010]
Preferably, the write buffer is a first-in first-out multi-stage buffer. As a result, even when continuous write operations are performed on the peripheral modules, a plurality of write data can be stored in the write buffer, so that the CPU can shift to another process in a short time. The CPU throughput is further improved.
[0011]
Further, the bus state controller is provided with a read buffer that holds the same contents as the contents of a predetermined register in the peripheral module, and a register copy control circuit for reading the changed register value from the peripheral module. As a result, even when the CPU reads the contents of the peripheral module registers, the CPU can obtain desired data in one cycle, and the throughput of the CPU is improved.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the drawings.
[0013]
FIG. 1 shows a schematic configuration of an embodiment of a microcomputer provided with a CPU and peripheral modules to which the present invention is applied. Although not particularly limited, each circuit block shown in FIG. 1 is formed on one semiconductor chip such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
[0014]
As shown in FIG. 1, the microcomputer of this embodiment includes a central processing unit CPU of a program control system, a read-only memory ROM for storing programs executed by the CPU and fixed data necessary for control. A random access memory RAM for providing a work area for the CPU and temporarily storing data obtained as a result of execution of the program, and an arithmetic unit for performing arithmetic processing such as multiplication on behalf of the CPU In place of the CPU, a MULT and a DMA controller DMAC that performs DMA (direct memory access) type data transfer between a storage device such as an external hard disk device and an internal RAM are provided. These circuits are connected via a CPU address bus IAB and a CPU data bus IDB.
[0015]
The microcomputer of this embodiment is provided with a peripheral address bus PAB and a peripheral data bus PDB separately from the CPU buses IAB and IDB. The peripheral address bus PAB and the peripheral data bus PDB include an interrupt controller INTC for making an interrupt request to the CPU based on the occurrence of a predetermined interrupt factor, and a program for the CPU at a breakpoint specified by the user during emulation. Peripheral module PRM such as user break controller UBC that requests execution stop, analog-digital conversion circuit ADC, serial communication interface SCI for serial communication with external device, timer circuit TIM for time management, and external device An input / output port PORT for inputting / outputting signals between the two is coupled. Note that CPU buses IAB and IDB to which a CPU is connected are also connected to the input / output port PORT so that the CPU or DMAC can directly exchange data with an external device.
[0016]
A bus state controller BSC is provided between the CPU buses IAB and IDB and the peripheral buses PAB and PDB to adjust the timing of signals on the two buses and to bridge signals between the CPU and peripheral modules. It has been. Although not particularly limited, in this embodiment, the ROM is constituted by a flash memory capable of erasing data in a predetermined block unit. In order to control the writing of data to the flash memory, a flash controller FLASHHC is provided near the ROM.
[0017]
Furthermore, a clock generation circuit CPG for generating a clock required for internal operation is provided. In this clock generation circuit CPG, a crystal oscillator XTAL having a predetermined natural vibration number is connected via an external terminal EXTAL. Combined. The clock generation circuit CPG, together with the external crystal oscillator XTAL, forms a clock signal having a predetermined frequency and phase corresponding to its natural frequency, and is multiplied by a PLL circuit to divide the clock by 80 MHz and φc. Then, a clock φp such as 20 MHz is formed and supplied to each part of the microcomputer.
[0018]
In this embodiment, the CPU is supplied with an 80 MHz reference clock φc, and the peripheral module PRM is supplied with a 20 MHz peripheral clock φp having a frequency lower than that of the reference clock φc. The peripheral module PRM is slower than the CPU. It is configured to work with.
[0019]
FIG. 2 shows a basic configuration of the peripheral module PRM.
[0020]
The peripheral circuit module PRM includes a control register for control, a status register having a flag reflecting the internal state of the module, registers 11a to 11c such as a data register for holding data, and the inside of the module to which these registers 11a to 11c are connected. On the bus 12, an internal interface circuit 13 for inputting / outputting signals between the module internal bus 12 and the peripheral data bus PDB, a module body circuit 14 for executing the original function of the module, and the peripheral address bus PAB And a decoder circuit 15 that decodes the read strobe signal RS and the write strobe signal WS supplied from the bus state controller BSC to select one of the registers 11a to 11c.
[0021]
The module body circuit 14 has various configurations depending on the function to be executed by the module, and includes, for example, an arithmetic unit and a control circuit (decoder that decodes the value of the control register) that controls the arithmetic unit. When the peripheral module is a serial communication interface, for example, the module body circuit 14 is provided with a serial / parallel conversion circuit or the like. When the peripheral module is a timer, for example, the module body circuit 14 is provided with a timer counter for counting clocks. The module body circuit 14 and the internal interface circuit 13 operate upon receiving the peripheral clock φp.
[0022]
Although not particularly limited, the module internal bus 12 and the peripheral data bus PDB have a data width of 8 bits, 16 bits, 32 bits, for example. Each peripheral module PRM is configured to start operation when the controller register is set to a predetermined value by the CPU. In a peripheral module that transmits and receives signals to and from an external device such as a serial communication interface or an A / D converter circuit, the module body circuit 14 is connected to a predetermined external terminal via the input / output port PORT. The
[0023]
FIG. 3 shows an embodiment of the bus state controller BSC provided between the CPU buses IAB and IDB and the peripheral buses PAB and PDB.
[0024]
The bus state controller BSC of this embodiment decodes the bus command code CMD and the address signal IAB supplied from the CPU to form the peripheral module selection signal MSL, the read strobe signal RS, and the write strobe signal WS to the peripheral module PRM. Based on a signal from the decode circuit 21, an I / O interface circuit 22 for adjusting the timing of a data signal between the CPU data bus IDB and the peripheral data bus PDB, and the signal from the decode circuit 21, the inside of the bus state controller BSC is controlled. And a control circuit (sometimes called a state machine) 23 for returning a bus cycle end signal BUSRDY to the CPU.
[0025]
The bus state controller BSC is supplied with the same reference clock φc as the clock supplied to the CPU, and is operated by the reference clock φc. Although the time (number of cycles) from the access to the peripheral module PRM from the CPU to the end of the bus cycle differs depending on the peripheral module, the control circuit 23 in the bus state controller BSC can select any of the peripherals depending on the signal from the decode circuit 21. Since it is possible to know whether the module is accessed, the conventional microcomputer returns the bus cycle end signal BUSRDY to the CPU at the timing corresponding to the accessed module.
[0026]
On the other hand, in the bus state controller BSC of this embodiment, data is taken into the address buffer 24, the write buffer 25, and the write buffer 25 that take in and hold the address signals and data signals on the CPU address bus IAB and the CPU data bus IDB. And a valid bit 26 indicating whether or not the When the address signal and data signal on the CPU buses IAB and IDB are taken into the address buffer 24 and the write buffer 25, the control circuit 23 immediately sets the valid bit to “1” and sets the bus cycle end signal BUSRDY to the CPU. Is configured to return to In this embodiment, a data signal returned from the peripheral module PRM via the peripheral data bus PDB in response to a read request from the CPU is output to the CPU data bus IDB via the I / O interface circuit 22. It is configured.
[0027]
Next, the operation of the bus state controller BSC of the embodiment of FIG. 3 will be described. During the write operation, the CPU instructs the bus state controller BSC to perform a write operation on the peripheral module with the bus command CMD, and outputs the address of the peripheral module to the CPU address bus IAB and the write data to the CPU data bus IDB. At this time, if the valid bit 26 of the write buffer 25 in the bus state controller BSC is “0” and the data is not held, the data is stored in the write buffer 25 and the address is stored in the address buffer 24 in one cycle of the reference clock φc. , Each written. Then, the valid bit 26 in the bus state controller BSC is set to “1”. The effective bit 26 indicates that data is stored when “1” and is not stored when “0”.
[0028]
Next, the bus state controller BSC asserts the bus cycle end instruction signal BUSRDY to a high level, and the CPU detects this and ends the write cycle to the peripheral module in one cycle based on φc. On the other hand, if the valid bit 26 is “1”, the bus state controller BSC immediately asserts the module select signal MSL and the write strobe WR to the peripheral module PRM corresponding to the address, and sets the address held in the address buffer 24 to the peripheral. Write data held in the address bus PAB and in the write buffer 25 is output to the peripheral data bus PDB. The write cycle from the bus state controller BSC to the peripheral module PRM is performed in two cycles of the peripheral clock φp (eight cycles of the reference clock φc). At the end of the cycle, the valid bit 26 is cleared to “0”, and the address buffer 24 and the write The buffer 25 can accept new data.
[0029]
When the valid bit 26 is “1” during the write operation by the CPU, the bus state controller BSC completes the write operation to the peripheral module PRM until the valid bit 26 is cleared to “0”. The bus cycle end instruction signal BUSRDY for is negated, and the CPU bus cycle is waited. As soon as the valid bit 26 is cleared to “0”, data is written to the write buffer 25, the bus cycle end instruction signal BUSRDY is asserted, and the CPU write cycle ends.
[0030]
If the valid bit 26 is “0” during the read operation, the bus state controller BSC has not performed a write operation to the peripheral module PRM, and immediately receives the module select signal MSL, read from the peripheral module PRM corresponding to the address. The strobe RS is asserted, an address is output to the peripheral address bus PAB, and a read operation to the peripheral module PRM is started. The read cycle is performed in two cycles of the peripheral clock φp (eight cycles of the reference clock φc). The bus state controller BSC outputs the data output from the peripheral module PRM to the peripheral data bus PDB onto the CPU data bus IDB via the I / O interface circuit 22, and asserts the bus cycle end signal BUSRDY at the end of the read cycle. The CPU recognizes the assertion of the bus cycle end signal BUSRDY, captures the value of the CPU data bus IDB, and ends the read cycle. Therefore, in this embodiment, the read cycle of the peripheral module PRM by the CPU requires 8 cycles or more with the reference clock φc.
[0031]
On the other hand, if the valid bit 26 is “1” at the start of the read operation for the peripheral module, the bus state controller BSC is in the write operation to the peripheral module PRM, so the write operation is completed and the valid bit 26 is cleared to “0”. Until the bus cycle end signal BUSRDY is negated, the CPU bus cycle is waited. When the valid bit 26 is cleared to “0” and the write cycle is completed, the module select signal MSL and the read strobe RS are immediately asserted to the peripheral module PRM corresponding to the address, and the address is transferred to the peripheral address bus IAB. Output and start a read operation to the peripheral module PRM.
[0032]
FIG. 4 shows the timing of each address bus and data bus and the bus cycle end signal BUSRDY in the write cycle when the valid bit is “0” in this embodiment.
[0033]
In the conventional method, the bus cycle end signal BUSRDY is returned after the start of the write cycle by the CPU, for example, after 3 cycles of the reference clock. According to this embodiment, as shown in FIG. ), The bus cycle end signal BUSRDY is returned. Therefore, the CPU outputs an address signal and a data signal onto the CPU buses IAB and IDB for a write operation to the peripheral module, and then receives the bus cycle end signal BUSRDY from the bus state controller BSC and promptly performs other processing. The CPU throughput can be improved.
[0034]
FIG. 5 is a block diagram of a bus state controller showing a second embodiment of the present invention. In the bus state controller of this embodiment, the one-stage address buffer 24 and write buffer 25 in the first embodiment are replaced with a FIFO (first-in first-out) type multi-stage buffer 27. In this embodiment, an empty bit 32 indicating whether or not the FIFO buffer 27 is empty, a fill bit 31 indicating whether or not the FIFO buffer 27 is full, and the next data in the FIFO buffer 27 are stored. A write pointer 33 indicating a position (address) to be written and a read pointer 34 indicating a position where data is read next in the FIFO buffer 27 are provided.
[0035]
During the write operation, the CPU instructs the bus state controller BSC to perform a write operation on the peripheral module PRM with the bus command CMD, outputs the address of the peripheral module to the CPU address bus IAB, and outputs the write data to the CPU data bus IDB. To do. At this time, if the FIFO type write buffer 27 in the bus state controller BSC is not completely filled with valid data (if the fill bit 31 is “0”), the FIFO buffer 27 in one cycle of the reference clock φc. Data and address are respectively written to the write pointer 33 and the write pointer 33 is incremented. Then, the bus state controller BSC asserts the bus cycle end instruction signal BUSRDY, and the CPU ends the write cycle to the peripheral module PRM.
[0036]
The empty bit 32 is set to “1” when there is no valid data in the FIFO buffer 27, and is set to “0” otherwise. The fill bit 31 is set to “1” when the FIFO buffer 27 is full of valid data, and is set to “0” otherwise. If the capacity of the FIFO buffer 27 is m, the value of the write pointer 33 is WP, and the value of the read pointer 34 is RP,
1) When WP> RP
Empty bit = 0,
Fill bit = 1 when WP = m, RP = 0
Otherwise, fill bit = 0
2) When WP <RP
Empty bit = 0,
Fill bit = 1 when RP = WP + 1
Otherwise, fill bit = 0
3) When WP = RP
Empty bit = 1, Fill bit = 0
It becomes.
[0037]
If the empty bit 32 is “0”, the bus state controller BSC immediately outputs the address and data at the head of the FIFO buffer 27 to the peripheral address bus PAB and the peripheral data bus PDB. At this time, the bus state controller BSC also asserts the peripheral module selection signal MSL and the write strobe signal RS. The write cycle from the bus state controller BSC to the peripheral module PRM is performed in two cycles of φp, and the read pointer 34 is incremented (+1) at the end of the cycle.
[0038]
When the fill bit 31 is “1” during the write operation, that is, when the FIFO buffer 27 is filled with data, the bus state controller BSC performs a write operation to the peripheral module PRM, the write pointer 33 is incremented, and the fill bit 31 is “0”. Until the bus cycle end instruction signal BUSRDY is asserted to the CPU, the CPU bus cycle is waited. As soon as the fill bit 31 becomes “0”, the bus cycle end instruction signal BUSRDY is negated to write the data from the CPU to the FIFO buffer 27, and after the write, the bus cycle end instruction signal BUSRDY is asserted to execute the CPU bus cycle. Terminate.
[0039]
If the empty bit 32 is “1” during the read operation and the bus state controller BSC is not performing a write operation to the peripheral module PRM, the module select signal MSL and the read strobe RS for the peripheral module corresponding to the address are immediately displayed. Assert, output the address to the peripheral address bus PAB, and start a read operation to the peripheral module. The read cycle is performed in two cycles of the peripheral clock φp. Therefore, the bus state controller BSC negates the bus cycle end instruction signal BUSRDY to the CPU, and the data output from the peripheral module PRM to the peripheral data bus PDB is transferred to the CPU data bus IDB via the I / O interface circuit 22 in the BSC. The bus cycle end signal BUSRDY is asserted at the end of the read cycle. When the CPU recognizes the assertion of the bus cycle end signal BUSRDY, the CPU reads the value of the CPU data bus IDB and the read cycle ends.
[0040]
If the empty bit 32 is “0” during the read operation and the bus state controller BSC is writing to the peripheral module, the write operation of all the data in the FIFO buffer 27 is completed and the empty bit 32 is set to “1”. Until the bus cycle end signal BUSRDY is negated, the CPU bus cycle is waited. When the write operation is completed, the module select signal MSL and the read strobe RS are immediately asserted to the peripheral module corresponding to the address, the address is output to the peripheral address bus PAB, and the read operation to the peripheral module is started. .
[0041]
By providing the FIFO buffer 27 in this way, the write access from the CPU to the peripheral module can be effectively performed in one cycle per data even during continuous writing.
[0042]
FIG. 6 is a block diagram of a bus state controller showing a third embodiment of the present invention. As shown in FIG. 6, in this embodiment, a register change detection circuit 16 for detecting a change in the value of the internal register 11 is provided in the peripheral module PRM. On the other hand, in the bus state controller BSC, a read buffer 28 having a copy of the value of the register 11 in the peripheral module PRM and a detection signal Drc output from the register change detection circuit 16 provided in the peripheral module PRM are provided. In response, a register copy control circuit 29 is provided for reading the value of the changed register in the peripheral module.
[0043]
The register change detection circuit 16 includes a logic gate that takes a logical sum of a register reset signal, a write signal, a flag set signal, a flag clear signal, a data capture signal, and the like, and a flag ( Flip-flop) or the like. The read buffer 28 is composed of a memory circuit such as a register or a RAM, and is controlled so as to always have a copy of the corresponding register in the peripheral module. In order to reduce the storage capacity of the read buffer 28, the registers to be copied may be limited to flag-type and data-type registers that are frequently read-accessed by the user. Since the register copy control circuit 29 always keeps a copy of the register in the read buffer 28, the module selection signal MSL and the read strobe signal RS for the peripheral modules are asserted immediately after the reset is released or when the register change detection signal Drc is input. Then, the address of the register to be copied is generated and output from the peripheral address bus PAB to the peripheral module PSM to read the register, and the read value is held in the read buffer 28.
[0044]
When the register copy control circuit 29 starts the read operation of the corresponding register, if the bus state controller BSC is performing a write operation to the peripheral module, the register copy control circuit 29 suspends the read operation until the end of the write operation. When the register change detection signal Drc is asserted simultaneously from a plurality of modules, a read operation is performed according to the priority set internally. The read cycle is performed in two cycles of the peripheral clock φp. When the read operation is completed, the register change detection circuit 16 in the corresponding peripheral module is cleared, and the detection signal Drc for the bus state controller BSC is negated. In this way, the register value is automatically read from the read buffer 28 by the register copy control circuit 29.
[0045]
In the write operation of the peripheral module PRM from the CPU, the CPU instructs the bus state controller BSC to perform a write operation, outputs the address of the peripheral module to the CPU address bus IAB, and outputs the write data to the CPU data bus IDB. Is done. The bus state controller BSC immediately waits for the end of the operation if it is not in operation to load the read buffer 28, if it is in operation, asserts the module select signal MSL and write strobe WS for the peripheral module, and sends the address to the peripheral address bus PAB This is done by outputting to The write cycle is performed in two cycles of the peripheral clock φp. The bus state controller BSC negates the bus cycle end instruction signal BUSRDY to the CPU until the write operation ends, and puts the CPU into a wait state. When the write operation ends, the bus cycle end instruction signal BUSRDY is asserted, and the CPU ends the write operation.
[0046]
The read operation of the peripheral module PRM by the CPU is performed in the same manner as the write operation. The read operation is performed by the CPU instructing the bus state controller BSC to perform a read operation with the bus command CMD and outputting the address of the peripheral module to the internal address bus IAB. In the bus state controller BSC, the CPU read at this time is a read to the register in which the read buffer 28 in the bus state controller BSC has a copy, and the register change detection signal Drc for the read buffer 28 of the corresponding register is negated. If so, the data of the corresponding register in the read buffer 28 is immediately output to the CPU data bus IDB, and the bus cycle end instruction signal BUSRDY is asserted. The CPU takes in the data output to the CPU data bus IDB and ends the read operation. Such a read operation is completed in one cycle of the reference clock φc.
[0047]
On the other hand, when the peripheral module PRM is read by the CPU, if the register change detection signal Drc of the corresponding read request is asserted, the bus state controller BSC negates the bus cycle end instruction signal BUSRDY. The CPU is put into a wait state. Then, the bus state controller BSC loads the value of the register in the peripheral module corresponding to the read buffer 28, and the bus state controller BSC receives the negation of the register change detection signal Drc, and the bus state controller BSC receives the corresponding register in the read buffer 28. Is output to the CPU data bus IDB, and the bus cycle end instruction signal BUSRDY is asserted. Then, the CPU takes in the data output to the CPU data bus IDB and ends the read operation. Such a read operation is completed in two cycles of the peripheral clock φp (eight cycles of the reference clock φc).
[0048]
As described above, by providing the read buffer in the bus state controller BSC, it is possible to effectively perform the read operation of the peripheral module from the CPU in one cycle of the reference clock φc.
[0049]
The third embodiment can be applied in combination with the address buffer 24 and write buffer 25 of the first embodiment or the FIFO buffer 27 of the second embodiment. That is, the read buffer 28, the address buffer 24, the write buffer 25, or the FIFO buffer 27 corresponding to the peripheral module registers are provided in the bus state controller BSC. The operations of the write buffer 25, the FIFO type write buffer 27, and the read buffer 28 are as described in the above embodiment. With this configuration, the timing of the bus cycle end signal returned to the CPU for the read operation and write operation on the peripheral module by the CPU can be advanced, and the throughput of the CPU is greatly improved.
[0050]
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
[0051]
Further, in the above description, the case where the invention made mainly by the present inventor is applied to a microcomputer having a CPU and peripheral modules, which are the fields of use behind the invention, has been described. In addition, the present invention can also be applied to a multi-chip microcomputer in which the CPU and the peripheral module are constituted by separate semiconductor chips.
[0052]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0053]
That is, in a data processing device such as a microcomputer or a microcontroller including a CPU and a peripheral module that operates at an operation clock having a frequency lower than that of the CPU, the CPU outputs an access command, an address, and data of the peripheral module. Then, other processing can be performed immediately, thereby improving the CPU throughput.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a microcomputer including a CPU and peripheral modules to which the present invention is applied.
FIG. 2 is a block diagram showing a basic configuration of a peripheral module.
FIG. 3 is a block diagram showing an embodiment of a bus state controller.
FIG. 4 is a timing chart showing timings of address buses, data buses, and bus cycle end signals in a write cycle in the microcomputer of the embodiment.
FIG. 5 is a block diagram showing a second embodiment of the bus state controller.
FIG. 6 is a block diagram showing a third embodiment of the bus state controller.
[Explanation of symbols]
CPU Central processing unit
BSC bus state controller
PRM peripheral module
CMD bus command
IAB CPU address bus
IDB CPU data bus
PAB peripheral address bus
PDB peripheral data bus
MSL peripheral module select signal
RS Read strobe signal
WS Light strobe signal
BUSRDY Bus cycle end signal
φc Reference clock (CPU clock)
φp peripheral clock
11a, 11b, 11c registers
12 module internal bus
13 I / O interface
14 Module body circuit
15, 21 Decoder
16 Register change detection circuit
22 I / O interface
23 Control circuit (state machine)
24 Write buffer (data buffer)
25 Write buffer (address buffer)
26 Effective bits
27 FIFO buffer
28 Read buffer
29 Register copy control circuit
31 Philbit
32 empty bits
33 Light pointer
34 Read pointer

Claims (6)

At least with the central processing unit,
A first bus connected to the central processing unit;
A second bus connected to the peripheral module;
A control circuit that is provided between the first bus and the second bus and bridges signals of the two buses;
A peripheral module connected to the second bus, accessed by the central processing unit via the control circuit, and having a plurality of registers;
A data processing device having a memory circuit connected to the second bus,
The peripheral module operates with an operation clock having a lower frequency than the operation clock of the central processing unit.
The control circuit can perform control to read the value of the register of the peripheral module and hold it in the memory circuit,
The peripheral module outputs a detection signal indicating that the value of at least one of the plurality of registers has been changed to the control circuit,
The control circuit executes a read operation of a value changed in the at least one register in response to the detection signal,
When the central processing unit performs a write access to the peripheral module, the control circuit suspends the read operation of the value changed in the at least one register in response to the detection signal until the end of the write access operation. A data processing device.   In response to the detection signal from the peripheral module, the control circuit generates an address of the at least one register whose value has been changed, executes the read operation, and is read by the read operation. The data processing apparatus according to claim 1, wherein the memory circuit holds the stored value. The peripheral modules include first and second peripheral modules,
The control circuit according to claim 2, wherein when the detection signal is simultaneously generated from the first and second peripheral modules, the control circuit performs a read operation of a register whose value is changed according to a predetermined priority. Data processing device.   The data processing apparatus according to claim 3, wherein the plurality of registers are data registers that hold data.   2. The data processing apparatus according to claim 1, wherein at least the central processing unit, the peripheral module, the memory circuit, and the control circuit are formed on one semiconductor chip.   6. The data processing apparatus according to claim 5, wherein the peripheral module includes a serial interface and an analog / digital conversion circuit.

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