JPS59201124A - Clock generating system - Google Patents

Abstract

PURPOSE:To utilize the performance of a memory connected to a microprocessor to the full by extending the cycle of clocks supplied to the microprocessor only in a specific timing mode. CONSTITUTION:The result obtained by inverting an MREQ signal by an inverter 56 is supplied to a D input terminal of an FF53, and an FF54 is cascaded to the FF53. Then the Q output of an FF54 is used as a signal FFW1. This signal is supplied to an NOR gate 57 together with the Q output of an FF52, and the output of the gate 57 is fed back to the D input terminal of the FF52. The Q output of the FF52 is connected to a clock terminal of a microprocessor. In this case, a fixed cycle is delayed by 1/2 clock cycle for the access time of the memory. Thus the read data set-up time of the microprocessor is satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a lock generation method suitable for use in a microprocessor.

[Technical background of the invention and intermediate points]

The recent development of microelectronic computers is remarkable, and the market is rapidly expanding, especially in the field represented by personal computers. Generally, these computer converters use a world standard microprocessor.

By the way, these microprocessors are generally synchronous type. This synchronous microprocessor is supplied with a constant cycle clock from the outside, and performs various controls or calculations in synchronization with the clock. Therefore, the higher the frequency of the clock supplied to the microprocessor, the faster the microprocessor will be able to perform control or calculations, but the clock frequency is determined by the maximum frequency allowed by the microprocessor itself. There is a limit, and furthermore, there is a limit by the frequency that the peripheral circuit of the micro sensor can follow. Therefore, the performance of peripheral devices including memory was not fully demonstrated, and even if a high-performance microprocessor was used,
Since the operating frequency is limited by the memory performance or the operating speed of peripheral devices, the performance of the device itself deteriorates.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and has been made by adopting a configuration in which the clock cycle supplied to the microprocessor is lengthened only at specific timings. Our goal is to provide a clock generation method that maximizes the operating speed of the system.

[Summary of the invention]

In the present invention, the cycle of the clock supplied to the microprocessor or controller is lengthened only at specific timings.

If a clock generation circuit is designed to accomplish this, and the peripheral device, including memory, is unable to keep up with the maximum operating frequency allowable to the microprocessor or controller, the peripheral device The frequency is set to a low value only for the clock cycles at locations that cannot be followed, and the clock cycles at other locations are set to the maximum allowable frequency and output.

This allows the performance of the microprocessor, memory and peripheral devices connected to it to be maximized.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail in comparison with conventional examples.

Conventionally, the frequency of the clock supplied to a microprocessor has been constant over time.

For example, using the 8-bit microprocessor Z8O supplied by ZILOG Corporation in the United States as an example, a conventional method for generating black lines will be described as follows.

FIG. 1 is a diagram showing the timing when the microprocessor reads the memory.

A microprocessor has a constant cycle clock signal CL.
K” is supplied, T1 * 'r, l T3's 3
The READ kb operation of the memory is completed in one clock period. Here, TH and T2 #T3 have the same period. The following signals are output from the micro log processor between TI+21T3.

A, %A, 11...Memory address signal MREQ
....When the microprocessor accesses the memory with the memory request signal, RD becomes 'LOW' .....The microprocessor goes 'LOW' with the READ strobe signal, and the microprocessor performs a READ operation on the memory. It becomes "LOW" when requesting.

The memory starts operating when MREQ becomes "LOW" and transfers the read data to the data bus D.

~ Send to D7. This time is called memory access time and is indicated by tACC in the figure.

The microprocessor accepts this Do% at the beginning of the T3 cycle.
D. To import the above READ data, use READ 7
” - If the set-up time (VAI, ID) exceeds a certain level from when the evening becomes valid (VAI, ID) until the Ts psi starts.
t,) is required. Here, if the access time of one memory is slow and a set-up time of a certain amount cannot be secured, the following two-part countermeasure is used.

(1) Clock (C
Lengthen the period (lower the frequency) of LK).

(2) Insert a WAIT cycle.

The method (2) is shown as a timing chart in FIG. That is, by setting the WAIT signal to 'LOW' during the T2 cycle, a unit cycle T is inserted between the T2 cycle and the T3 cycle, and the microprocessor takes in the READ 7"-time for that amount. It slows down time.

The WAIT signal is a signal generated by a circuit external to the microprocessor and supplied to the microprocessor. In FIG. 1, during the T2 cycle, WA I T is ``I(I
GH'', no wait cycle (T cycle) is inserted.

(-However, the conventional method described above has the following drawbacks. Namely, the method of increasing the clock cycle shown in (1) reduces the time required not only when the microprocessor accesses the memory but also when other calculations are performed. In the method of inserting wait cycles shown in (2), there is a delay only when the microprocessor accesses the memory, and other calculation times are not slowed down. In the method shown in Figure 1, even if the timing is slightly delayed, the method shown in Figure 2 will delay the clock by one cycle.In other words, in the method of inserting a wait cycle, the clock A or
It is impossible to delay by 4, so it will necessarily be delayed by 1 clock. As a result, the performance of the memory may not be fully demonstrated.

The above discussion has only been about the inconveniences related to the access time when the microprocessor accesses the memory, but the same can be said for other timings as well.

For example, the microprocessor Z80 has a built-in control circuit that refreshes the dynamic RAM.
This function is often used.

As shown in the timing chart in Figure 3, z80 is the operation code, fetch (OP FETCH)
After that, a refresh cycle is executed on the dynamic RAM at T3 and T4 (period for decoding the fetched instructions).

The MREQ signal is generally the timing for generating the RAS signal (Row Addre+u+5trobe) of the dynamic RAM, but at this time, the MR
Period when EQ is “HIGH” and @MREQ is “LO”
The timing of the W'' period is very critical for the dynamic RAM. Therefore, even with a high speed 280, the dynamic RAM cannot run at full speed due to refresh cycle timing limitations.

In the refresh cycle (T3 r Ta ) after the operation code 7 is etched, a wait cycle as shown in Figure 2 cannot be inserted, so there is no choice but to adjust the clock period to the timing control of the refresh cycle.

FIG. 4 shows a clock generation circuit that generates the above timing. In this example, an oscillator 41 generates an A-synchronous (double frequency) clock to be supplied to the microprocessor, and a flip-flop 42 divides the frequency to generate the clock to be supplied.

FIG. 5 is a circuit diagram showing an embodiment of a clock generation circuit to which the present invention is adopted. In the figure, 51 is an oscillator, 52
．． 53.54 indicates flip float, 55 r 56 indicates innoguita, and 57 indicates NOR dart. In the embodiment of the present invention, the American TI as Fritunoflora f52.53.54
(Texas Instrument) 74LS74,
The company's 74LSO4 is used as the inverter 55.56.

N0Rr-)57 is the company's Noah 41. Figure 6 is a circuit diagram showing another embodiment of the clock generation circuit to which the present invention is applied. In the figure, 61 is an oscillator;
62.63 is a flip-flop, 64 is an inverter, 6
5 is a NOR gate. It is assumed that each element used in this embodiment is the same as the embodiment shown in FIG.

FIG. 7 shows the memory READ timing of the microprocessor Z80 that operates frequently in the circuit shown in FIG. 5, and FIG.
80 is a diagram showing the timing of memory READ of 80. FIG.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail.
This is the timing when the microprocessor z80 reads the memory, and the operation is as described above (FIGS. 1 and 2). However, in this case, it is assumed that the timing shown in FIG. 1 (without inserting a wait cycle) is insufficient for accessing the memory, and the timing shown in FIG. 2 (with inserting a wait cycle) has too much margin. The difference between the timing chart shown in FIG. 7 and the prior art is that in the embodiment of the present invention, a signal FFW is generated by the clip float counters 53 and 54, thereby dedicating the T2 cycle to the clock period (CI of T2, K
Double the width of ``LOW''). The logic for generating this FFW signal is shown in FIG.

That is, the result of inverting the MREQ signal by impark 56 is supplied to the D input terminal of 7 flip-flop 53, and further, flip-flops 54 are connected in cascade, and the Q output of flip-flop f54 is FFW.

It is used as a signal. The Q output of the fritsunoflop 52 is supplied to the clock input terminal of the flipflop 53, and the output of the oscillator 51 via the inverter 55 is supplied to the clock input terminal of the fritsunoflora f54. The FFW signal is provided to a NOR dart 52 along with the Q output of flip-flop 52, and the NOR dart 57 output is fed back to the D input terminal of flip-flop 52. It goes without saying that the Q output of flip-flop 52 is connected to the clock terminal of microprocessor Z80.

Naturally, the memory access time can be sufficiently reduced by delaying the T2 cycle by the remaining clock period.
It is assumed that the READ data set up time (t,) of 80 can be satisfied.

Furthermore, even with the method shown in Figure 7, if there is too much margin for the memory access time by 6D (however, the timing shown in Figure 1 is not enough), as shown in Figure 8, the cycle is changed to 1/4 clock period. It is also possible to make it longer.

The method shown in FIG. 8 can be achieved by inputting the signal FFW2 to the clock generation circuit shown in FIG. 6 at the timing shown in FIG. In the embodiment shown in FIG. 6, the circuit FFW2 for generating the signal is omitted.

As can be seen from the above explanation, in the method of the present invention, by changing (lengthening) the period of the clock supplied to the microprocessor z80 only at some timings, the performance of the microprocessor 280 and the performance of the memory can be utilized without wasting it. I can do it. Furthermore, the method of the present invention can be implemented not only for the T2 cycle but also for other cycles. For example, in the case where the fc refresh cycle timing limits the clock frequency of 280 as described in the prior art, in the conventional system, the entire clock frequency is adjusted to the refresh cycle timing limit. As a result, timing other than the refresh cycle is also unnecessarily slow, detracting from high-speed performance. According to the method of the present invention, it is possible to lengthen only the clock during the refresh cycle (T3 or T4) and operate at the highest speed in other cycles. In addition to the “LOW” time, C
It is also possible to lengthen the time of I, K"f (IGH").It is also possible to make the time longer than the clock cycle and 1/4 clock cycle. Although other signals are also required, they are omitted here because they are not related to the gist of the present invention.

Furthermore, in the embodiments of the present invention, the Z80 is used as an example of a microprocessor, but the present invention can be applied to any microprocessor that receives a clock from an external source and operates in cycles with the clock. According to the above, by lengthening the clock period supplied to the microprocessor only at certain timings, the performance of the memory connected to the microprocessor can be effectively utilized. Also, the operating frequency of the microprocessor is no longer limited by the operating speed of memory or peripheral devices.

It should be noted that the present invention is applicable not only to microprocessors but also to various controllers that receive a clock supply and operate in cycles with the clock.

[Brief explanation of drawings]

Figures 1 and 2 are traditional notes! 3 is a diagram showing the timing of conventional memory IJ fresh, FIG. 4 is a diagram showing a configuration example of a conventional clock generation circuit, and FIG. 5 is a diagram showing a configuration example of a conventional clock generation circuit. 6 is a diagram showing another circuit embodiment of the present invention, and FIGS. 7 and 8 are circuit embodiments of the present invention, respectively, of the memory READ according to FIGS. 5 and 8g6. FIG. 51.61...Oscillator, 52.53. s4゜62.6
3...Noritsubu flop, 55,56°64...1
converter, 57, 6.5...NOR dirt.

Claims (1)

[Claims] In a device consisting of a microprocessor or controller that receives a clock from an external source and performs calculations or controls in synchronization with the clock, and peripheral devices connected to the microprocessor or controller, the clock supplied to the microprocessor or controller is If a clock generation circuit that generates and outputs a variable period only at specific timing is added, and the peripheral device cannot follow the maximum operating frequency allowable to the microprocessor or controller, the output of the clock generation circuit may be A clock generation method characterized in that, in the clock cycle, the frequency is set to a low value only for the clock cycles at locations that the peripheral device cannot follow, and the clock cycles at other locations are set and output at the maximum allowable frequency.