JPH01260690A - Memory access control system - Google Patents

Abstract

PURPOSE:To attain an optimum access control according to the using frequency of a memory by setting a control input according to a stand-by mode or an active mode to the setting state of a mode setting flag to a memory when the access control is received from a host device. CONSTITUTION:A memory access control part 14 has a function for setting the control input of the stand-by mode having a first access time to the memory 12 at the time of receiving the access control from the host device 10 and a function for setting the control input of the active mode having a shorter access time than the first access time to the memory 12. The mode setting flag FL for switching and setting both the modes is provided. To the memory 12 high in the using frequency, a high speed access can be attained by setting the active mode, and to the memory 12 low in the using frequency, the stand-by mode is set. Thereby, a consuming power is lowered to execute the optimum memory access control designed to establish a compatibility for improving the performance of a processor and lowering the power consumption.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory access control method in which a processor reads or writes memory, the aim is to achieve optimal access control according to the frequency of use of the memory. Equipped with a function to set control inputs in memory for standby mode, which consumes less power, and a function to set control inputs in active mode, which consumes more power but has a shorter access time, and also allows switching between standby mode and active mode. A mode setting flag is provided, and when receiving access control from a host device, a control input for standby mode or active mode is set in the memory depending on the setting state of the mode setting flag.

"Field of Industrial Application" The present invention relates to a memory access control method for reading or writing memory by a processor.

Memories such as ROM and RAM have control input terminals such as chip select C81 write enable (output enable) 0'' and write enable WE for read or write access, and when the processor accesses the memory, the memory access controller Then, the control input of chip select O8 and write enable OE or write enable RE is turned on to read or write data.

[Prior Art] There are two types of control modes in conventional memory access control systems: standby mode and active mode.

That is, the standby mode is a mode in which the chip select C8 and read enable OE control inputs for the memory are turned on when receiving access control from the processor using memory access As and read command RD, for example, and normal memory access is performed in this mode. It is in standby mode.

On the other hand, active mode means that the control input of the chip select O8 for the memory is always in the ON state, and for example, when receiving access control by the memory access AS and read command RD from the processor for read access, the read enable OE for the memory is set. Alternatively, only the control input of the write enable WF is turned on.

[Problems to be Solved by the Invention] However, in the conventional memory access control using standby mode, the chip select C
Since the access time from when 8 is issued until the start of a read or write operation is long, it may be necessary to increase the number of waits for the processor to wait until the start of the access. There is a problem in that it causes performance deterioration.

On the other hand, in active mode in which chip select C8 is always on, memory control is performed by turning on only read enable OE or write enable WE, which reduces access time and has the advantage of reducing the number of processor waits. Has chip select O8
Since it is always on, there is a problem that the power consumption of the memory increases.

That is, when access control is performed in standby mode or active mode, the performance of the processor decreases when it comes to song titles, and the power consumption increases when it comes to the latter.

In particular, a plurality of memories such as ROM and RAM are usually connected to a processor, and the frequency of use of the memories varies, and the frequency of use of a particular memory may be higher than that of other memories.

Therefore, if active mode is set for all memories to enable high-speed access to frequently used memories, chip selects 1~ are always on even for memories that do not require high-speed access, so the memory unit as a whole power consumption increases significantly.

On the other hand, if the standby mode is set with emphasis on reducing power consumption, the number of waits for the processor increases due to frequently used memory accesses, resulting in a problem in which the performance of the processor deteriorates significantly.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a memory access control method that enables optimal access control depending on the frequency of memory use. .

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1(a), a host device 10, a memory 12 accessed by the host device 10, and a memory access control unit 14 are provided.

The memory access control unit 14 has a function of setting a control input in the memory 12 for a standby mode (see FIG. 1(b)) having a first access time T1 when receiving access control from the host device 10, and Active mode (see Fig. 1 (
It has a function of setting the control input (see C) in the memory 12.

Furthermore, the memory access control unit 14 has a mode setting flag F for switching between standby mode and active mode.
L is set.

If the mode setting flag [L is set to FL=O, for example, the mode becomes standby mode, and if it is set to "L-1", the mode becomes active mode.

In standby mode where FL=O, as shown in Figure 1 (
As shown in b), memory access A from the host device 10
When receiving the access control of s and the read command RD, the memory access control unit 14 turns on the chip select C8 and read enable OE for the memory 12, and as a result, read data is output after 1 when the upper clock is accessed. 1. Since the access time T1 is long, the host device 10 performs a wait operation.

On the other hand, in the active mode where FL=1, as shown in FIG. 1(C), the chip select C8 for the memory 12 is always on.

In this state, when receiving access control by the memory access AS and read command RD from the host device 10, the memory access control unit 14 turns on only the read enable OE for the memory 12, and accesses the subordinate 1 for a short time when accessing in standby mode. Since the read data is outputted by the timer 2 and the access time is within the upper clock, the wait operation of the host device 10 is not necessary.

[Function] In the memory access control method of the present invention, high-speed access is possible by setting the active mode to the frequently used memory by setting the mode setting flag; For memory with low power consumption, power consumption can be reduced by setting the standby mode by resetting the mode setting flag, and optimal memory access control can be performed to achieve both improved processor performance and lower power consumption.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, 10a is a processor as a host device, and in this embodiment, the processor 10a is connected to three
memories 12a, 12b.

12C is connected. The memories 12a to 12c include, for example, the memory 12a is a ROM in which the control program for the processor 10a is fixedly stored (in this case, the large WE input of 12a is unnecessary), and the memory 12b.

12c is a RAM that temporarily stores processing data.

Memory 1 under access control by processor 10a
A memory access control unit 14 is provided to perform read access or write access to 2a to 12G.

The memory access control unit 14 of the present invention has a function of setting a control input in the memory in a standby mode having a first access time T1, and a function in an active mode having a second access time T2 shorter than that of the subordinate 1 at the time of the first access. It has a function to set control input in memory.

That is, the memory access control unit 14 includes an input/output unit 16 that performs input/output connections with the processor 10a, and the memories 12a to 12a.
Control units 20a, 20b, 20 designed in accordance with 12G
It has G. For the input/output unit 16, a processor 10a
A memory access AS, a read command RD, and a write command WR are input from the input/output unit 16 to the processor 10a.
A READY signal is output for causing a wait operation to be performed. On the other hand, the control units 20a to 20c are provided corresponding to the memory 12a, for example. Taking the control unit 20a as an example, the control units 20a to 20c control chip select O8, read enable (output enable) OE, and write enable WE for the memory 12a. It has a function to set input.

A flag F for switching between standby mode and active mode is provided for each of the control units 20a to 20G.
Flag setting unit 18a that sets each of L1 to FL3
, 18b, and 18C are provided.

In this embodiment, mode setting flags FL1 to FL3 set in flag setting units 188 to 18C are FL1 to FL3.
The active mode is set in the flag set state of FL3=1, and the standby mode is set in the flag reset state of FL1 to FL3=0.

Setting flags for flag setting units 188 to 18C/
The reset is fixedly set in advance based on the frequency of use of the memories 12a to 12C. For example, memories 12a to 12
Of C, the memory 12a (ROM) that stores the control program for the processor 10a is frequently used, so it is
An active mode with a short access time is set by setting L1=1, and a standby mode is set by setting FL2=FL3-○ for the memories 12b and 12c made of RAM.

The mode setting flags FL1 to FL3 for the flag setting units 188 to 18G may be set in a fixed manner in advance, or may be set by, for example, monitoring the usage frequency of the memories 12a to 12c in the processor 10a, and using them under control from the processor 10a. An active mode may be set for frequently used memory, and a standby mode may be set for less frequently used memory.

Furthermore, the decoded output decoded by the address decoder 22 is given to the control units 20a to 20C provided in the memory access control unit 14.

Therefore, the control units 20a to 20C receive access control inputs from the processor 10a, that is, memory access AS, read command RD or write command WR, and address decoder 22.
Control inputs for the memory based on the standby or active mode set by the mode setting flag, ie, chip select C8 and read enable OE or write enable WE, are determined based on the decoder output.

The control inputs set from the memory access control unit 14 to the memories 12a to 12G will be explained separately in standby mode and active mode as follows.

[Standby mode; FL=1] The chip select C81 read enable OE and write enable WE are all off when no access control input is received from the processor 10a. For example, when receiving control inputs of memory access AS and read command RD for read access from the processor 10a, chip select O8 and read enable O for the memory are received.
Turn on E at the same time. Of course, for write access, chip select C8 and write enable WE are turned on at the same time.

[Active mode; FL-1] Regardless of the presence or absence of access control input from the processor 10a, the chip select C8 for the memory is always turned on. For example, when a control input of memory access AS and read command RD is received from the processor 10a for read access, read enable O for the memory is received.
Turn on only E. Of course, if it is a write access, only the write enable WE is turned on.

FIG. 3 is a circuit configuration diagram showing one embodiment of the memory access control section 14 in the embodiment of FIG. 2, with a control section for one memory taken out.

In FIG. 3, the memory access control unit 14 outputs the decode output DEC of the address decoder 22 and the processor 10a.
AND gate 28 which inputs the memory access AS from
The output of the AND gate 28 is input to one side of the OR gate 30.

The output of these ORGs 1 to 30 becomes the chip select C8 for the memory.

On the other hand, a flip-flop 18 is provided as a flag setting section, and in a standby mode state where FL=O, the flip-flop 18 is placed in a reset state and produces an output rOJ, and on the other hand, in an active mode state where FL=0. In the set state, it is in the set state and produces an output "1". The output of the flip 70 block 1B serving as a flag setting section is input to the other of the OR gates 30.

Therefore, the ON or OFF state of chip select C8 for the memory is determined by AND gate 28, OR gate 30, and flip-flop 18.

Here, the output states of the chip select C8 by the AND gate 28, OR gate 30, and flip-flop 18 are summarized as shown in the following table-1 in active mode, and as shown in the following table-1 in standby mode. It will be like 2.

Incidentally, the timings ① to ② in Tables 1 and 2 above correspond to the operation timing explanatory diagram of FIG. 4, which will be explained later.

Furthermore, the memory access control unit 14 is provided with an AND gate 32 that outputs a read enable OE and an AND gate 34 that outputs a write enable WE. The output of AND gate 28 is input.

Further, the write command WR from the processor 10a and the output of the AND gate 28 are input to the AND gate 34.

The READY signal to processor 10a is provided by AND gates 36, 38, OR gates 40 . It is created by a circuit section consisting of an inverter 42 and a play circuit 44.

That is, one input of the AND gate 36 is connected to the output of the AND gate 28, and the other input is connected to the output of the flip-flop 18. For this reason, AND gate 36
is in an allowable state in the active mode setting state by setting the flip-flop 18, and in response to the output "1" of the AND gate 28 when memory access AS is received from the processor 10a, the output of the AND gate 36 becomes "1".
is output to the processor 10a as a READY signal via the OR gate 40, and the READ signal becomes "1".
The processor 10a that receives the Y signal no longer performs a wait operation.

The output of the AND gate 28 delayed by the play circuit 44 is connected to one input of the AND gate 38, and the output of the flip-flop 18 inverted by the inverter 42 is connected to the other input of the AND gate 3B. For this reason A
The ND gate 38 is placed in a disabled state in an active mode with the flip-flop 1B set, and enabled in a standby mode with the flip-flop 18 reset. In this permissive state, the processor 10
AND gate 28 receives memory access AS from a
When the output "1" is generated, after being delayed for a predetermined time by the delay circuit 44, it is applied to the AND gate 38 which is in the permissive state.
“1” to the processor 10a via the OR gate 40
A READY signal is output. This “1” is R
Since the EADY signal is delayed by the play circuit 44, the processor 10a performs a wait operation until the READY signal rises to 1j.

In the embodiment shown in FIG. 3, a flag set/reset signal is externally applied to the flip-flop 18 for setting the mode setting flag FL, but as described above, it can also be set or reset in advance. Alternatively, the setting and resetting of the flip-flop 18 may be controlled by a signal from the processor 10a based on the memory use frequency in the processor 10a.

Next, referring to the operation timing explanatory diagram of FIG.
The operation of the embodiment shown in FIG. 3 will be explained.

Now, in the active mode of FL=1 in which the knob 70 knob 18 in FIG.
) is performed.

In FIG. 4(a), first, since the flip-flop 1B shown in FIG. 3 is in the set state due to the active mode where FL=1, the OR
The output for goo 1 to 30 is "1", and OR
Chip select O8, which is applied to, for example, the memory 12a in FIG. 2 as an output of the gate 30, is always kept on at "1".

When the processor 10a issues a read access to the memory 12a while the chip select O8 is on, address data is output to the memory 12a via the address bus 24 following the fall of the processor clock, and this address data is address decoder 2
2 and DE to AND gate 28 in FIG.
C output rises to "1".

Subsequently, the processor 10a issues a memory access As and a read command RD to the memory access control unit 14 in synchronization with the rise of the processor clock.

Read access AS from processor 10a is input to AND gate 28 in FIG. 3, and the output of AND gate 28 becomes rlJ. At this time, the input for ORgu 1 to 30 is (
1, 1>, the chip select C8 is kept in the on state. At the same time, the output "1" of the AND gate 28 causes the AND gates 32 and 34 to enter the allowable state. The processor 10a issues a read command R at the same time as the memory access AS.
Since D is issued, the output of the AND gate 28 is "1".
The output of the AND gate 32, which is now in the permissible state, is 11.
”, and the read enable OE for the memory 12a is
turns on.

When the read enable OE is turned on with the chip select C8 always on, the memory 12a starts outputting read data after access time 2 = 80 ns, which is within the rising cycle of the processor clock, for example, 200 ns. Direct data is sent to the processor 10a via the data bus 26.

After the rise of memory access ΔS, the processor 10a requests a set-up time of, for example, 80 ns to read data at the fall of the next processor clock, so read data must be input from memory access AS before 120 ns. Must be. As a result, in the active mode shown in FIG. 4(a), since the read data is output = 21 - 80 ns after the rise of the memory access, the processor 10a receives the fall of the processor clock. Set up time from 80
Lead data was entered before ns, and as a result,
The processor 10a can latch read data at the falling edge of the processor clock after turning on memory access As.

On the other hand, the READY signal to the processor 10a is output by the output "1" of the flip-flop 18.
36 is in the allowable state, while AND gate 38 is in the inhibited state, so AND gate 28 accesses memory access A.
When the output "1" is generated by S, the READY signal is turned on, and as a result, the processor 10a latches the read data at the falling edge of the next clock without performing a wait operation.

Next, the operation in standby mode will be explained with reference to FIG. 4(b).

In FIG. 4(b), the processor 10a is, for example, 12
When a read access is issued to a, address data is output following the fall of the processor clock, and memory access As and read command RD are sent to the memory access control unit 14 in synchronization with the rise of the next processor clock. Output.

At this time, since it is in standby mode, the flip-flop 18 in FIG. 3 is placed in a reset state and the output rO
J, and until memory access AS is issued, the output of OR gate 3o becomes rOJ, turning off chip select O8 for memory 12a.

When the processor 10a issues the memory access ΔS, the output of the AND gate 28 becomes 11'', the output of the OR gate 30 also becomes 1, and the chip select C8 for the memory 12a is turned on. AND gate 32 at the same time
The output becomes "1" due to the rise of the read command RD from the processor 10a, and the read enable OE for the memo 1 12a is turned on.

In this way, chip select for memory 12a = 23
- When 1-C8 and read enable OF are turned on, the memory 12a begins to output read data after an access time of T1-20Qns. That is, as the performance of the memory 12a, the access time T1 from chip select CS on
is 150 nS at the minimum, and FIG. 4(b) shows a state in which the REET access is started with T1=200 nS.

On the other hand, the READY signal output to the processor 10a is output from the flip-flop 18 in FIG. The output [1] of the AND gate 28 is delayed by the play circuit 44, for example, by a time exceeding 20 ounces of the rising cycle of the processor clock, and the READY- signal that becomes "1" at the falling timing of the processor clock is not obtained. Processor 10a enters a wait operation.

Chip select 1 is selected in the wait state of this processor 10a.
The output of read data from the memory 12a is started when 1-200 ns has elapsed during access from the ON of -0S, and the processor 10a starts to latch the read data at the fall of the processor clock after waiting.

It should be noted that although the above description of the operation took read access as an example, access control can be similarly performed for write access using active mode or standby mode depending on the state of the mode setting flag FL.

[Effects of the Invention] As explained above, according to the present invention, by setting the mode setting flag for frequently used memory, an active mode with high power consumption but short access time is set, and memory that is used less frequently For memory, by resetting the mode setting flag, a standby mode with long access time but low power consumption can be set, allowing optimal access to improve processor performance and reduce power consumption depending on the frequency of memory use. Achieving control-25
＝ Can be done.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is an embodiment configuration diagram showing one embodiment of the present invention; Fig. 3
The figure is a circuit configuration diagram of a memory access control section; FIG. 4 is an explanatory diagram of memory access operation timing. In the figure, 10: Host device 10a: Processor 12.12a to 12c: Memory 14: Memory access control section 16: Input/output section 18a to 18c: Flag setting section 18: Flip-flop 20a to 20b: Control section 22 Near address decoder 24 Near address bus 26: data bus 28.32.34, 36.38 two △ND gates 30.4
0: OR gate 42: Inverter 44: Delay circuit i-, ---rl-i /f-45 day/month. No. (cl Daughter 1 The 1st figure drying lead QE i-12---]------
-''-m-: : '': l 11 FL=1;Active drying (a) Me drying access d th FL=O;Staff high drying fb) ?Katai 乍 Thai three blowfish eL mouth moon m 4th figure

Claims (2)

[Claims] (1) A host device (10), a memory (12) accessed by the host device (10), and a standby mode control input having a first access time (T1) are set in the memory (12). Function and first access time (T1
), the memory access control unit (14) having a function of setting an active mode control input having a shorter second access time (T2) in the memory (12); ) is provided with a mode setting flag (FL) for switching between the standby mode and the active mode, and when receiving access control from the host device (10), the standby mode is set according to the setting state of the mode setting flag (FL). Alternatively, a memory access control method characterized in that a control input according to an active mode is set in the memory (12). (2) In the standby mode setting state, the memory access control unit (14) performs chip select (CS) and read enable (OE) for the memory (12) when receiving access control from the host device (10). The write enable (WE) is turned on, while in the active mode setting state, the memory access input (CS) for the memory (12) is always turned on, and the host device (
10. The memory access control system according to claim 1, wherein a read enable (OE) or a write enable (WE) is turned on when receiving access control from the memory access control system 10).