JPS61242397A - Refresh control system for volatile memory - Google Patents

Abstract

PURPOSE:To shorten the access time and to stabilize the circuit operation together with reduction of the number of circuits, by performing a refresh processing after the refresh request signal synchronizing with an access instruction has an interruption into the idle time of the access instruction. CONSTITUTION:A generation means 2 produces the access instructions (write and read instructions) and a refresh request signal in response to the clock given from a clock source 1. The idle time equal to a desired clock cycle, e.g., a clock cycle is given to the access instruction. This idle time is utilized to switch the address of the access instruction. An interruption means 3 gives the interruption of a refresh request signal approximately at the middle time point of the idle time. A refresh processing means 4 performs the refresh processing in response to the interruption of the refresh request signal. A waiting means 5 keeps the execution of the access instructions produced during the refresh processing of the means 4 until this refresh processing is through.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a volatile memory flow system, an access command to the volatile memory and its refresh request signal are generated from a single clock source, and the generated access command is The volatile memory is refreshed by providing a necessary free time and generating an interrupt of a refresh request signal during the free time. Furthermore, if an access command is given during the refresh operation, the access command is executed after the refresh operation.

[Industrial application field]

The present invention relates to a volatile memory refresh control method,
More specifically, a free time is set for the access command and refresh request signal access command generated from a single clock source, and the volatile memory is refreshed by interrupting the refresh request signal during the free time. Various types of storage devices may be used in digital processing devices such as electronic computers that employ a refresh control method for volatile memory in which when an access command is given in the memory, the execution of the access command is delayed until the completion of refresh. Among these storage devices is volatile memory. Since this volatile memory cannot retain its contents for a long time, it must be refreshed at predetermined intervals within the time that its contents can be retained.

A circuit that performs such refreshing is required to contribute to shortening the access time of a volatile memory, to have stable operation, and to be able to meet these requirements with a reduced number of circuits.

[Conventional technology]

An example of a conventional refresh control method is a format in which a refresh request signal is sent from a refresh control section to a memory control section, and in response to the request signal, a refresh permission signal is given from the memory control section to the refresh control section to perform refresh. There is something like that. In this type of system, a clock system for normal memory access commands and a clock system for refresh request signals are constructed as separate systems.

[Problem that the invention seeks to solve]

Therefore, there are problems in that the circuit size increases, and even if factors that make the circuit unstable in operation are removed, it may malfunction. Moreover, these factors act synergistically to become a factor that prevents shortening of access time.

The present invention was created in view of the above-mentioned technical problems, and an object of the present invention is to provide a volatile memory refresh control method that can shorten access time, stabilize circuit operation, and reduce the number of circuits. is its purpose.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In this figure, 1 is a single clock source for the generating means 2. The generating means 2 generates access commands (write commands, read commands) in response to the clock from the clock source 1.
and generates a refresh request signal. The access command is given a free time corresponding to a required clock cycle, for example, one clock cycle. This free time is also used for address switching of access commands. Reference numeral 3 denotes an interrupt means that interrupts the refresh request signal at approximately the middle of the above-mentioned free time. Reference numeral 4 denotes refresh processing means for performing refresh processing in response to an interrupt of a refresh request signal. Reference numeral 5 denotes a standby means that, if the refresh processing means 4 is in the middle of a refresh process, causes the execution of an access command generated during that time to wait until the end of the refresh process. Reference numeral 6 denotes an access instruction execution means for starting execution of the access instruction when the execution of the access instruction is not put on standby, and for executing the access instruction after waiting for the completion of the refresh processing when the execution of the access instruction is put on standby. It is.

[Effect]

The refresh process according to the present invention is performed when a refresh request signal synchronized with the access command is interrupted during the idle time of the access command. If an access command is issued during this refresh process, the access command is executed after the refresh process in progress is completed.

Therefore, it is possible to contribute to shortening the memory access time, stabilize the refresh operation, and reduce the number of circuits.

〔Example〕

FIG. 2 shows an embodiment of the present invention, and FIG. 3 is a timing chart used to explain the embodiment of FIG. In Figure 2, 10 is a microprocessor unit (MPU)
, 11 is a refresh control section (RFC),
12 is a memory control unit (MEMC), and 13 is a volatile memory.

MPLIIO responds to the MPU clock *MPUCL (see (3-1) in Figure 3) from a single clock source (not shown) and issues a memory write command *MWTC or a memory read command *MRDC ((3-1) in Figure 3). -2)
, (3-3)) is generated, the RAM command RAMCM (see (3-3) in Figure 3) is generated via a Noah gate (not shown).
5)) is supplied to the Nantes gate 20 and the signal *RA
MCK (see (3-13) in Figure 3) is Nantes Gate 2
It is output from 0 (assuming that it is not in a refresh cycle and the signal *RFQCY is at 1'').

). Further, the differential circuit 21. or gate 2
2 via the signal *RESET ((3-15) in Figure 3)
) is generated and supplied to the reset input of the flip-flop 23 at J-, which is reset to generate the signals R and A.
MC1 (see (3-14) in FIG. 3) is generated. Generation of this signal RAMCl, that is, an inverted signal of that signal *R
When AMC1 occurs, data memory (MEM)
1. For writing to '3, the signal RAS (Ro-Address Set) is supplied to the memory 13 via the OR gate 24, and the memory address Fa (M
EMC) I 2, signal CA S via OR gate 25
(Column Address Set) is supplied to the memory 13, and the memory control unit 12
．． Write enable signal WE via AND gate 26
is supplied to the memory 13, and a memory address signal *MA is output from the memory control unit 12 in response to address signals *AOI to *A18 from MPU10.
O to *MA8 and write data signals WDOO to WD
15. WDPL and WDPU are supplied to the memory 13 to write data into the memory 13 [Here, examples of the memory address signal and write data signal, ie *
MAO to *MA8 and WDOO to WDI 5. W.D.
PL and WDPU have the content structure of memory 13 as 512KB.
(256KW x 18b)]
. Moreover, for reading data from the memory 13,
Signals RAS, CAS and *MAO to *MA as described above
8 is applied to the memory 13 and read data signals DOOO to DO15,D from the memory 13.

PL, Do) PU is output. The example of this read signal is also the same as described above.

At an appropriate time when such a successful write or read is performed, the timing control section 27 sends a signal to the MPU.
A response signal *MXACK is sent to l0. Upon receiving this response signal, the MPU stops sending the accessed command, such as the write command *MWTC, at the MPU clock time after the elapse of the required time determined by the command (see (3-2) in FIG. 3).

If there is a next command, it is sent at the time when the 1MPU clock has elapsed from the above-mentioned command sending stop time, and the command is processed in the same manner as described above.

While such a command is being processed, the signal R
AMCM lMPU clock free time (RAMCM
Upon entering a refresh cycle that is previously set to occur during the low level period of counter 28. ANDGATE 29. Inverter 30. By the action of the free knob flop 31, the signal RFRQTI ((3
-7) Reference, dotted lines represent refresh operations, and the same applies to dotted lines in other timing waveforms. ) is output from the flip-flop 31 to J-. This signal is delayed by a delay circuit 32 and first a signal *RFRQT2 appears at the output of an inverter 33. Then, the signal *RFQ from the OR gate 34
CY is output at a low level. At this time, the refresh cycle signal *RFCY is at a high level because the refresh cycle has not yet started. Therefore, signal *RAMCM is at high level.

After a predetermined time has elapsed, the signal *RFRQT1 being delayed by the delay circuit 32 becomes the refresh request signal REFRQ and is supplied to the AND gate 35 after a predetermined time elapses.

At this time, since the signal *RAMCl is at a high level, the AND gate 35 outputs the signal RFGO ((3-
10)) is output and supplied to the delay circuit 36, and low level signals *R, FCY, *RFRAS, and *RFCAS are output. Thus, the low level signal RFQCY prohibits reception of the subsequently generated signal RAMCM, and maintains the output signal *RAM'CK of the Nant gate 20 at a high level ((3-13 in FIG. 3)). (see dotted line).

In other words, the process of starting a refresh cycle and waiting for the next RAM command (RAMCM) is prepared.

Therefore, as described above, the signal *RFRAS (RAS signal during refresh) output from the delay circuit 32,
*RFCAS (CAS signal at refresh time) is connected to signals RA and S via corresponding OR gates 24 and 25, respectively.
, are supplied to the memory 13 as CAS and used for refreshing the memory.

After the time required for this refresh has elapsed, the refresh cycle signal RFCY, therefore the signal RFQCY
Transition time to high level ((3-11), (3
-12)) (at the time indicated by the dotted downward arrow in (3-13) in FIG. 3), the signals RA and MC1 become high level.

After a predetermined period of time has elapsed from the transition time of the signals R and AMC1 to the high level, that is, a reasonable period of time for successfully performing refresh, the timing control section Response signal *MXAC from 27 to MPUl0
K is sent.

As a result, MPU10 starts processing the next command, such as a memory write command (see (3-2) in Figure 3).
. That is, commands awaited by refresh are executed in response to completion of the refresh.

〔Effect of the invention〕

As explained above, according to the present invention, the volatile memory access command and the refresh request signal are synchronized and generated using a single clock source, and the refresh request signal is given to the access command. Refreshing is performed by interrupting during idle time, and the instructions that are awaited by the refresh are executed after the refresh is completed, which contributes to shortening the access time, enhancing stable operation, and reducing the number of circuits. .

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention; FIG. 3 is a timing chart of the embodiment shown in FIG. In Figures 1 and 2, 1 is a single clock source, 2 is a generation means, 3 is an interrupt means, 4 is refresh processing means 5 is a standby means; Reference numeral 6 represents access command execution means.

Claims (2)

[Claims] (1) In a volatile memory refresh control method,
means (2) for generating an access command and a refresh request signal from a single clock (1) by giving an empty time for a required clock cycle at the beginning of an access command for the volatile memory; and the refresh request signal. A volatile memory device characterized by comprising: means (3) for causing an interrupt at an appropriate time during the free time; and means (4) for causing a refresh process of the volatile memory to be performed in response to the interrupt. A refresh control method for sexual memory. (2) In a volatile memory refresh control method,
means (2) for generating an access command and a refresh request signal from a single clock (1) by giving an empty time for a required clock cycle at the beginning of an access command for the volatile memory; and the refresh request signal. means (3) for causing an interrupt at an appropriate time during the free time; means (4) for executing a refresh process of the volatile memory in response to the interrupt; and an access command generated during the refresh process. 1. A volatile memory refresh control system comprising: means (5, 6) for causing the refresh process to be executed after completion of the refresh process.