JPS6118190A - 半導体レ−ザ装置 - Google Patents

半導体レ−ザ装置

Info

Publication number
JPS6118190A
JPS6118190A JP59137931A JP13793184A JPS6118190A JP S6118190 A JPS6118190 A JP S6118190A JP 59137931 A JP59137931 A JP 59137931A JP 13793184 A JP13793184 A JP 13793184A JP S6118190 A JPS6118190 A JP S6118190A
Authority
JP
Japan
Prior art keywords
semiconductor laser
laser chip
mount
bonding
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59137931A
Other languages
English (en)
Inventor
Noriyuki Yoshikawa
則之 吉川
Yuichi Shimizu
裕一 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59137931A priority Critical patent/JPS6118190A/ja
Publication of JPS6118190A publication Critical patent/JPS6118190A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/023Mount members, e.g. sub-mount members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0233Mounting configuration of laser chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0235Method for mounting laser chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0235Method for mounting laser chips
    • H01S5/02355Fixing laser chips on mounts
    • H01S5/0237Fixing laser chips on mounts by soldering

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Semiconductor Lasers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は光通信・光情報処理等で用いられる半導体レー
ザ装置に関するものである。
(従来例の構成とその問題点) 近年、半導体レーザは、小型、軽量、高効率。
高集光性といった特徴のため、大きな注目を浴び応用分
野も拡大しつつある。
ところで、半導体レーザは第1図に示すように半導体レ
ーザチップ1 、 Siサブマウン) 3 * Cuヒ
ートシンク4で構成されている。ここでSiサブマウン
ト3は、量産性の向上やヒートシンクであるCu 4と
、半導体レーザチップである。GaAsとの熱膨張係数
の差を緩和するという働きをしている。
ここで問題となるのは、半導体レーザチップ1とSiサ
ブマウント3の密着性である。従来は半導体レーザチッ
プ1の密着性にばらつきが多く、接着強度が低く、熱抵
抗が大きいものも数多く見られた。そして接着された半
導体レーザチップ1と、Siサブマウント3をはがすと
、その接着面は第2図のような接着面6の実際に接着さ
れている部分である周辺部7のみの接着や部分的な接着
であった。5は活性層を示す。高性能化のために、半導
体レーザチップ1の端面をコーティングした場合、コー
ト剤が接着面の周辺部にまわシ込むことが十分に考えら
れるが、このような半導体レーザチップでは、十分な接
着強度は得られない。
また従来は第3図に示すように、半導体レーザチップ1
の周囲に、接着半田剤である金属蒸着層Sn 2の盛シ
上がシ8を生じる場合がある。半導体レーザチッゾの活
性層5は、Siサブマウント3に非常に接近しているた
め、この金属蒸着層Sn2の盛シ上がシによって、しば
しば短絡の症状が起こる。
(発明の目的) 本発明は上記欠点に鑑み、端面をコートした半導体レー
ザチッゾにも十分々る接着強度が得られ接着半田剤であ
るSnの盛υ上がシによる短絡の症状も生じにくい半導
体レーザ装置を提供するものである。
(発明の構成) この目的を達成するために本発明の半導体レーザ装置は
、半導体レーザチップとの接着面全面に溝列を有するS
iサシマウントを用いることを特徴としている。この溝
は、半導体レーザチッゾの光軸と同一方向に形成され、
溝の間隔はほぼ等間隔で、形成さ、れている。
(実施例の説明) 以下本発明の一実施例について図面を参照しながら説明
する。
第4図は、本発明で提供するS1サブマウントの一例を
示す。S】ウェハーに、1回のエツチングを行なって、
図のような溝を形成し、その上に、Ni ドライメッキ
を行ない、さらにCr+ Ni−Cr+ Ni+Snの
蒸着を行々う。次にダイシング加工を行なって、図のよ
うな形状のSiサシマウント9を得る。
半導体レーザチップ1のボンディングは、H2とN2雰
囲気中で300〜320℃に加熱することにより、従来
と同様に行なう。このSiサシマウント9は、半導体レ
ーザチッゾ1より小さな間隔の溝列を持つため、接着後
は第5図に示すような状態になる。このように、コート
剤がまわり込む半導体レーザチップ1に対しても、面密
着性が良く、確実な接着ができる。また金属蒸着層Sn
 2は、接着時、高温にすると、溝を埋める方向に流動
するので、Sn 2の盛り上がシは生じにくい。
(発明の効果) 以上のように本発明は、溝列を持ったSlサブマウント
を用いることにより、半導体レーザチッグとサブマウン
トの接着を確実にし、熱血抗を減少させると同時に、短
絡による不良を著しく減少させるために、その実用的効
果は大なるものがある。さらに、Stウェハーに1回の
エツチングを行なう以外に、従来の工程を変更する必要
はない。
【図面の簡単な説明】
第1図は従来の半導体レーザー装置の構成を示す正面図
、第2図は第1図の半導体レーザチップとSiサシマウ
ントの接着を、応力を加えることによってはがした時の
接着面の様子を示す斜視図、第3図は半導体レーデチッ
ゾとSiサシマウントの接着部を示す正面図、第4図は
本発明によるSiサシマウントを示す斜視図、第5図は
第4図のSiサシマウントを用いたときの接着部を示す
正面図、である。 1・・・半導体レーザチップ、2・・・金属蒸着層(主
にSn)、3・・・Siサブマウント、4・・・Cuヒ
ートシンク、5・・・活性層、6・・・接着面、7・・
・周辺部、8・・・盛シ上がシ部、9・・・本発明によ
るSiサシマウント。 第1図

Claims (1)

    【特許請求の範囲】
  1.  サブマウントの表面にレーザチップの寸法より十分小
    さな間隔で溝列が形成され、前記溝列が形成された面に
    接着用金属を介してレーザチップが付着されていること
    を特徴とする半導体レーザ装置。
JP59137931A 1984-07-05 1984-07-05 半導体レ−ザ装置 Pending JPS6118190A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59137931A JPS6118190A (ja) 1984-07-05 1984-07-05 半導体レ−ザ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59137931A JPS6118190A (ja) 1984-07-05 1984-07-05 半導体レ−ザ装置

Publications (1)

Publication Number Publication Date
JPS6118190A true JPS6118190A (ja) 1986-01-27

Family

ID=15210031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59137931A Pending JPS6118190A (ja) 1984-07-05 1984-07-05 半導体レ−ザ装置

Country Status (1)

Country Link
JP (1) JPS6118190A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101118802B1 (ko) 2005-09-28 2012-03-20 엘지전자 주식회사 반도체 레이저 다이오드 패키지

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101118802B1 (ko) 2005-09-28 2012-03-20 엘지전자 주식회사 반도체 레이저 다이오드 패키지

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