JPS61180454A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61180454A JPS61180454A JP2032685A JP2032685A JPS61180454A JP S61180454 A JPS61180454 A JP S61180454A JP 2032685 A JP2032685 A JP 2032685A JP 2032685 A JP2032685 A JP 2032685A JP S61180454 A JPS61180454 A JP S61180454A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- insulating
- semiconductor substrate
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高密度、胃集積に配線層が形成できる半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a semiconductor device in which wiring layers can be formed in a high-density, integrated manner.
従来の技術
従来の半導体装置の配線層には半導体基板内に半導体基
板と反対導電型の不純物を拡散して形成した拡散層ある
いは、半導体基板上に絶縁膜を介して形成した多結晶硅
素膜あるいは金属配線層が用いられている。BACKGROUND OF THE INVENTION Conventional wiring layers in semiconductor devices include diffusion layers formed by diffusing impurities of the opposite conductivity type to the semiconductor substrate, or polycrystalline silicon films formed on the semiconductor substrate with an insulating film interposed therebetween. A metal wiring layer is used.
しかし、拡散層の場合には他の素子の拡散層との分離の
ための絶縁層が必要である。また多結晶硅素膜あるいは
金属配線層の場合には、半導体基板上に絶縁膜を介して
形成するため、素子との接続部に接続のための絶縁膜の
開孔部が必要であり、素子の接続部と開孔パターンおよ
び開孔パターンと配線層に対して、位置合せ余裕が必要
であった。However, in the case of a diffusion layer, an insulating layer is required to separate it from the diffusion layers of other elements. In addition, in the case of a polycrystalline silicon film or a metal wiring layer, since it is formed on a semiconductor substrate via an insulating film, an opening in the insulating film is required for connection to the element, and the Alignment margins were required for the connection portion and the aperture pattern, and for the aperture pattern and the wiring layer.
発明が解決しようとする問題点
このような従来の配線層では占有面積が大きく、高密度
、高集積の半導体装置を得ることが困難であった。Problems to be Solved by the Invention These conventional wiring layers occupy a large area, making it difficult to obtain a high-density, highly integrated semiconductor device.
本発明はかかる点に鑑みてなされたもので、高密度、高
集積化が可能な配線層を有する半導体装置を提供するこ
とを目的としている。The present invention has been made in view of this point, and an object of the present invention is to provide a semiconductor device having a wiring layer capable of achieving high density and high integration.
問題点を解決するだめの手段
本発明は上記問題点を解決するため、半導体基板中に形
成した半導体素子間の絶縁分離領域の絶縁分離膜の膜厚
を変化させ、中央部の膜厚の厚い部分に配線層を形成し
たものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention changes the thickness of the insulation isolation film in the isolation region between the semiconductor elements formed in the semiconductor substrate, so that the film thickness is thicker in the central part. A wiring layer is formed in a portion.
作用
本発明は上記した構成により、従来から必要であった素
子間分離領域に配線層を形成することにより、半導体基
板中深くまで配線層が形成できるため、表面での占有面
積が減少し、かつ絶縁分離領域の一方の素子側に偏よら
せて、配線層を形成し、絶縁分離領域下部の半導体基板
と配線層の接続部を形成することにより高密度、高集積
な半導体装置が形成できる。Effect of the present invention With the above-described structure, the wiring layer can be formed deep into the semiconductor substrate by forming the wiring layer in the isolation region between elements, which has conventionally been necessary, so that the area occupied on the surface is reduced. A high-density, highly integrated semiconductor device can be formed by forming a wiring layer biased toward one element side of the insulation isolation region and forming a connecting portion between the semiconductor substrate and the wiring layer under the insulation isolation region.
実施例
第1図は本発明の配線層の一実施例を示す構造断面図で
ある。第1図において、1は半導体基板、2は絶縁分離
領域、3は薄い絶縁分離膜、4は厚い絶縁分離膜、6は
絶縁分離膜中に形成した配線層である。配線層5の厚さ
は、薄い絶縁分離膜3の膜厚より薄くてもよいが、第1
図に示すように前記薄い絶縁分離膜3の膜厚より厚く形
成した方が、同一パターン幅に対して、電流容量が大き
くとれる。Embodiment FIG. 1 is a structural sectional view showing an embodiment of the wiring layer of the present invention. In FIG. 1, 1 is a semiconductor substrate, 2 is an insulating isolation region, 3 is a thin insulating isolation film, 4 is a thick insulating isolation film, and 6 is a wiring layer formed in the insulating isolation film. The thickness of the wiring layer 5 may be thinner than the thickness of the thin insulating isolation film 3, but the thickness of the first
As shown in the figure, if the film is formed thicker than the thin insulating isolation film 3, the current capacity can be increased for the same pattern width.
第2図、第3図は本発明の他の実施例であって、配線層
5を絶縁分離領域2内で左右どちらかに偏らせて形成し
、かつ前記絶縁分離領域2の下部の半導体基板1もしく
は半導体基板内に拡散した不純物層と接続部11で電気
的接続部を形成したものである。FIGS. 2 and 3 show other embodiments of the present invention, in which the wiring layer 5 is formed biased to either the left or right within the insulation isolation region 2, and the semiconductor substrate under the insulation isolation region 2 is 1 or an impurity layer diffused into a semiconductor substrate and a connection portion 11 to form an electrical connection portion.
第4図は相補型半導体装置に本発明の一実施例を適用し
た例であり、−導電型たとえばp型半導体基板1上にn
型不純物層6を形成して作ったn型電界効果素子9と、
前記基板上にn型不純物層を深く拡散して形成したnウ
ェル8上にp型不純物層7を形成して作ったp型電界効
果素子1oとの絶縁分離領域2に偏在して作成した配線
層6と、前記nウェルとの接続部11を形成した半導体
装置である。FIG. 4 shows an example in which an embodiment of the present invention is applied to a complementary semiconductor device.
An n-type field effect element 9 made by forming a type impurity layer 6;
Wiring formed unevenly in an insulating isolation region 2 with a p-type field effect element 1o made by forming a p-type impurity layer 7 on an n-well 8 formed by deeply diffusing an n-type impurity layer on the substrate. This is a semiconductor device in which a layer 6 and a connection portion 11 with the n-well are formed.
発明の効果
以上述べてきたように本発明によれば、配線層のための
面積を大きく増加することなく、また、配線層と半導体
基板あるいは半導体基板に形成した不純物層との接続部
を容易に形成することができ、高密度、高集積の半導体
装置が得られる。Effects of the Invention As described above, according to the present invention, it is possible to easily connect the wiring layer and the semiconductor substrate or the impurity layer formed on the semiconductor substrate without significantly increasing the area for the wiring layer. A high-density, highly integrated semiconductor device can be obtained.
第1図は本発明の一実施例における半導体装置の断面図
、第2図および第3図は本発明の他の実施例の配線層を
有する半導体装置の断面図、第4図は相補型半導体装置
に本発明の実施例構造を適用した場合の断面図である。
1・・・・・・半導体基板、3,4・・・・・・絶縁分
離膜、5・・・・・・配線層。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
?
ニーし)
3454.3
第4図
J・・オ・・絶襲め樋巣
4・・4い紺)桜滴体凍
5・・・貿番、東層
/1・・接続部
!
ノう−41フz1iノ↓キカス九
6・・・71〒4、機力し1
7 Pを7r、託@漕
8、 hウエルFIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views of a semiconductor device having wiring layers according to another embodiment of the present invention, and FIG. 4 is a complementary semiconductor device. FIG. 3 is a cross-sectional view of a device in which an embodiment structure of the present invention is applied. 1... Semiconductor substrate, 3, 4... Insulating separation film, 5... Wiring layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure? Knee) 3454.3 Figure 4 J... O... Zetsume Hinosu 4... 4 dark blue) Sakura Droplet Body Freeze 5... Trade number, East layer/1... Connecting part! Nou-41fuz1iノ↓Kikasu 96...71 〒4, machine power 1 7 P 7r, trust @row 8, h well
Claims (2)
厚く形成し、前記中央部の厚い絶縁膜の一部に配線層を
形成したことを特徴とする半導体装置。(1) A semiconductor device characterized in that an insulating film formed in a semiconductor substrate has a thick central portion, and a wiring layer is formed in a part of the thick central insulating film.
下部の半導体基板と接続したことを特徴とする特許請求
の範囲第1項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the wiring layer is formed at the end of the thick insulating film and is connected to the semiconductor substrate below the insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2032685A JPH0670998B2 (en) | 1985-02-05 | 1985-02-05 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2032685A JPH0670998B2 (en) | 1985-02-05 | 1985-02-05 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61180454A true JPS61180454A (en) | 1986-08-13 |
JPH0670998B2 JPH0670998B2 (en) | 1994-09-07 |
Family
ID=12024006
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2032685A Expired - Lifetime JPH0670998B2 (en) | 1985-02-05 | 1985-02-05 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0670998B2 (en) |
-
1985
- 1985-02-05 JP JP2032685A patent/JPH0670998B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0670998B2 (en) | 1994-09-07 |
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