JPS6037743A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make small the occupied area of a common contact hole for connecting polycrystalline Si film and diffused region provided on an oxide film, on the occasion of forming a thick field oxide film at the periphery of semiconductor substrate, by protruding an internal end part thereof like forming an acute angle, providing the diffused regions such as soruce and drain at the end part and generating offset between this region and oxide film. CONSTITUTION:In the case of forming a thich field oxide film 2 at the periphery of a P type Si substrate 1, the internal end part thereof is protruded like forming an acute angle. A thin gate oxide film 3 is deposited on the surface of substrate 1 surrounded by the film 2, and impurity is then supplied through such gate oxide film in order to form the source or drain region 5. Thereafter, a polycrystalline Si layer 4 which is given conductivity is formed on the film 2 while the offset is generated between this layer and the region 5 by making use of the acute angle part of film 3, an interlayer insulating film 6 is deposited on the entire part, a common contact hole is bored at the offset position and an Al electrode 11 is attached therein.

Description

[Detailed description of the invention] The present invention relates to improvements in semiconductor devices.

In recent semiconductor devices, in order to integrate a large number of elements at high density, it is necessary to reduce the area occupied by each element. In order to make electrical contact between the source/drain diffusion layer region on a conventional semiconductor device and the polycrystalline silicon that is the gate and wiring material, a cross-sectional view is shown in Fig. 1, and a plan view is shown in Fig. 3. As shown in FIG.
6 and polycrystalline silicon regions 104 scattered on the field oxide film 102 on the semiconductor substrate 101 are overlapped to form a region 10 in which the polycrystalline silicon 104 covers the gate wiring film 103.
8 and extends over the north drain diffusion layer region 106 and the polycrystalline silicon region 104.
After opening a contact hole 109 in 05, a metal 107 is deposited, and the source/drain diffusion layer region 106 and the polycrystalline silicon region 104 are electrically connected via the metal 10, thereby reducing the area occupied by the element. (Hereinafter, this contact hole will be referred to as a common contact.) With a common contact, a contact hole is opened in each area and the contact hole is connected to the metal in an air-tight manner. However, as shown in the cross-sectional view of FIG.
In order to open a contact hole on the polycrystalline silicon 104, a part of the gate oxide film 103 is etched from the polycrystalline silicon pinhole, and aluminum gold PA107 is etched from the polycrystalline silicon pinhole and the gate oxide! A short circuit L was formed with the substrate 101 through the pinhole 103, resulting in a defect, and the reliability of the product could not be improved.

An object of the present invention is to realize a highly reliable semiconductor device without increasing the area occupied by a common contact that electrically connects a source/drain diffusion layer region and polycrystalline silicon compared to the conventional one. .

In order to achieve this object, the present invention includes a polycrystalline silicon wiring layer provided on a semiconductor substrate via a thick field oxide film, and at least a portion of the periphery of the semiconductor substrate f'Lfc is surrounded by the field oxide film. In a semiconductor device having an impurity region on a substrate and an interlayer insulating film provided on the polycrystalline silicon wiring layer and on the field oxide film, an end of the impurity region and the polycrystalline silicon wiring layer opposing thereto. The end portion of the field oxide film is located on this spaced region, including the end of the impurity region and the end of the polycrystalline silicon wiring layer. A semiconductor device characterized in that an opening is provided in an interlayer insulating film, and the polycrystalline silicon wiring layer and the impurity region are connected through the opening through a metal wiring layer.

Hereinafter, the present invention will be explained in detail with reference to Examples.

In addition, in the following, MO8 using silicon as a semiconductor will be described.
This will be explained by taking a type semiconductor device as an example.

FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 4 is a plan view. Thick field oxide film 20 for separating diffusion layer regions formed on Pfi silicon substrate 201
Polycrystalline silicon region 204 on 2 and N-type diffusion layer region 2
As shown in the plan view of FIG. 4, there is no overlapping part with 06, and there is an offset 209 from each other, and since a part of the taper of the field oxide film is located on the region that can be separated, the gate Contact holes are not opened on the polycrystalline silicon on the oxide film. Furthermore, by covering the contact hole with aluminum, the N-type diffusion layer region 206 and the polycrystalline silicon region 204 are electrically connected. In the above structure, unlike the conventional structure, the contact is not opened on the polycrystalline silicon on the gate oxide film, and therefore no defects occur.

Next, a manufacturing method of an example of the present invention will be explained.

FIGS. 5(a) to 5(g) are diagrams showing the manufacturing process of the embodiment shown in FIGS. 2 and 4. First, P-type silicate oxidation,
A field oxide film Z is formed (FIG. 5(a)). Next, a thin gate oxide film 3 is formed (FIG. 5(b)), and polycrystalline silicon 4, which is a gate electrode, is deposited thereon. After buttering polycrystalline silicone, there are no chemicals such as carbon or arsenic.
Type impurities are added at a high concentration to form the source/drain diffusion layer 5 of the N-channel transistor (FIG. 5(C)).
. After forming the oxide film 6 (FIG. 5(d)), using the photoresist 7 as a mask, a common contact hole 8 for taking out the groove is opened (FIG. 5(e)). Field oxide film inside the contact or contact etching h”tt)rt
If c also decreases and there is a risk of junction leakage, ions such as phosphorus may be implanted over the entire diameter of the contact hole (FIG. 5(f)).

Finally, the aluminum electrode 11 is formed as shown in FIG. 5(g).
An MO8O8 type semiconductor device having the structure of the embodiment of the present invention shown in FIGS. 1 and 3 can be formed.

In the above embodiment, N3J uses a P-type semiconductor substrate.

It is clear that the same implementation can be carried out in the P-type semiconductor device using N road &amiMw-ztheikomori1zumeζ h1saya■chudashi IremoreiJ or in the complementary MO8 semiconductor device.

As described above, the present invention provides a method for connecting the north drain diffusion layer of a semiconductor device and polycrystalline silicon through aluminum using one contact hole without opening a contact on the polycrystalline silicon on the gate oxide film. A high-density, highly reliable semiconductor device can be realized.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional common contact portion, FIG. 3 is a plan view of FIG. 1, FIG. 2 is a sectional view of a common contact portion of an embodiment of the present invention, and FIG. 4 is a plan view of FIG. 2. Figure, Figure 5(a)
- (g) are process cross-sectional views showing handling parts of the manufacturing method of the embodiment according to the present invention. Figures 1 and 3: iol...P-type silicon substrate, 102...Field oxide film, 103...
...Gate oxidation g, 104...Polycrystalline silicon, 105-...Interlayer oxide film, ]06...
・・N type lease drain diffusion layer region, 1o7・old・・
Aluminum. 2 and 4; 201...P-type silicon substrate, 202...Field oxide film, 2o3.
...Gate oxidation K, 204...Polycrystalline silicon, 2o5...Interlayer oxide film, 2o6...
...N-type lease/drain diffusion layer region, 208...
...Aluminum, 2o9...tLfc field oxide film removed by contact etching. Figure 5: 1... P-type silicon substrate, 2...
...Field oxidation power L 3...Gate oxide film, 4...Polycrystalline silicon, 5...N-type lease/drain diffusion layer region, 6... Interlayer oxide film, 7...Photoresist, 8...Common contact, 9. Old...Phosphorus ion implantation, 10...
...N-type diffusion layer, 11...aluminum. Figure 5(e)

Claims (1)

[Claims] A polycrystalline silicon wiring layer provided on a semiconductor substrate via a thick field oxide film, an impurity region of the semiconductor substrate whose periphery is at least partially surrounded by the field oxide film, and the polycrystalline silicon wiring layer. In the semiconductor device having an interlayer insulating film provided on the semiconductor substrate and the field oxide film, an end of the impurity region and an end of the polycrystalline silicon wiring layer opposing thereto are slightly separated from each other. An end portion of the field oxide film is located on this spaced-apart region, and an opening is provided in the interlayer insulating film including the end of the impurity region and the end of the polycrystalline silicon wiring layer. A semiconductor device characterized in that the opening is in contact with the polycrystalline silicon wiring layer by a brocade layer f.