JPH03141646A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability in connection by extending the end side of a diffused layer for wiring in contact with a field insulating film, and using a part which is separated from the field insulating film as a connecting region with a lead-out electrode. CONSTITUTION:A diffused region 6 for wiring and a lead-out electrode 4 are orthogonally intersected at a part which is separated from a field insulating film 7, and a deep embedded contact region 9 is formed. The lead-out electrode 4 is made to pass a part of the region 6 and terminated at an end 4'. A gate electrode 3 and the lead-out electrode 4 are formed of polycrystalline silicon layers 3b and 4b containing impurities and heat resisting metal layers 3a and 4a. In this way, an end side 6' of the region 6 is made to extend in contact with the insulating film 7, and a part which is slightly separated from the insulating film 7 is used as a connecting region with the lead-out electrode 4. Therefore, the connection is highly reliable. Since the lead-out electrode 4 is made to pass a part of the region 6 and terminated at the end 4', the sufficient contact area can be secured even if deviation in alignment and the like occur.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular has a gate electrode that has low resistance and can be directly connected to a diffusion layer wiring region, and has a stable threshold voltage, making it suitable for high speed and high integration. The present invention relates to a semiconductor device in which direct connection is stably performed.

Conventionally, as an old S-type semiconductor device, a silicon gate S-type semiconductor device in which a gate electrode is made of polycrystalline silicon containing impurities has been widely used. In particular, S-type semiconductor devices made of silicon gates containing phosphorus as an impurity have good threshold voltage stability, and most of the old S-type semiconductor devices in practical use contain phosphorus in the polycrystalline silicon gate. There is.

On the other hand, a gate electrode made of polycrystalline silicon has a relatively high layer resistance of several Ω10, which is not preferable for high-speed operation of the circuit. On the other hand, so-called R-MOS (Rer
Although the ractlve-metal MOS structure has a gate electrode layer resistance of 1 ohm or less and is suitable for high-speed operation, it has the following drawbacks.

That is, a gate electrode made of a heat-resistant metal cannot be directly connected to a diffusion layer wiring region.

In a silicon gate body S semiconductor device, the polycrystalline silicon gate electrode and the semiconductor substrate are brought into direct contact, and the source,
At the same time as the drain diffusion layer is formed, an impurity is introduced into the semiconductor substrate that penetrates the silicon gate electrode and is in direct contact with the silicon gate electrode, thereby directly connecting the diffusion layer wiring and the polycrystalline silicon gate electrode using a so-called buried contact method. However, when using a heat-resistant metal as the gate electrode, it is difficult to diffuse impurities through the gate electrode, so it is difficult to diffuse impurities through the gate electrode, so it is difficult to diffuse the impurity through the gate electrode. It was not possible to form a deep buried contact area. Therefore, if a heat-resistant metal is used as the gate electrode, when it is necessary to connect the gate electrode and the diffusion layer region in terms of the circuit configuration, the connection must be made through the second metal wiring layer, which causes problems in the device. This greatly reduced the degree of integration. Another problem is that the stability of the threshold voltage is poor. When a heat-resistant metal such as molybdenum or tungsten is used as a gate electrode, under high-temperature bias treatment, the threshold voltage shifts due to the diffusion of mobile ions such as sodium in the gate insulating film, and polycrystalline silicon containing phosphorus is used as the gate electrode. The stability cannot be obtained as much as in the case of .

On the other hand, in order to eliminate these drawbacks, a two-layer structure of polycrystalline silicon and a heat-resistant metal was used for the gate electrode and extraction electrode. However, in the prior art, this lead-out electrode was connected to element regions such as the source and drain at a location adjacent to a partially buried field insulating film.

Since crystals are thick in the area in contact with such a field insulating film, reliability problems arise due to leakage current and other problems. Moreover, in the prior art, the buried diffusion was performed to a depth shallower than the original depth of the source and drain regions, making the above problem even more serious.

An object of the present invention is to provide an effective semiconductor device that eliminates the above-mentioned drawbacks.

A feature of the present invention is that a thick field insulating film is selectively provided on the main surface of the semiconductor substrate, partially buried in the specimen, and a long and narrow wiring diffusion region whose end side is in contact with the field insulating film is oriented in one direction. The semiconductor substrate has a source region and a drain region that extend and partially extend from the main surface of the semiconductor substrate, and a gate electrode is provided on the region between the source region and the drain region with a gate insulating film interposed therebetween. In the old S-type field effect semiconductor device, the gate electrode and the extraction electrode extending from the gate electrode have a two-layer structure consisting of polycrystalline silicon containing impurities and a heat-resistant metal located thereon. and the extraction electrode extending from the gate electrode has a certain width, extends in a direction perpendicular to the one direction, intersects at right angles with the wiring diffusion region, and passes through the wiring diffusion region. terminating at a location on the main surface near the edge of the wiring diffusion region in contact with the field insulating film and spaced apart from the edge; and near the terminated end of the lead-out electrode. This occurs in a semiconductor device in which a point spaced apart from the end of the chain is in contact with the other end. The portion of the wiring diffusion region contacted here is formed of impurities diffused from the polycrystalline silicon and is formed deeper than the source, drain region and other extending portions of the wiring diffusion region. Preferably, the semiconductor device has a buried contact region, and with such a structure, the deep buried contact region is provided at a location spaced apart from an edge of the wiring diffusion region in contact with the field insulating film. The other portions of the wiring diffusion region except for the buried contact region may be formed at the same depth as the source and drain regions.

Further, an insulating film thinner than the field insulating film can be provided on other parts of the wiring diffusion region except for the part in contact with the extraction electrode and the vicinity thereof.

FIG. 1(a) shows a plan view of the configuration of the embodiment of the present invention.
FIG. 1(b) shows a sectional view taken along line AB in FIG. 1(a).

In these figures, 1 is a semiconductor substrate, 2 is a gate insulating film, 2' is a thin insulating film, 3 is a gate electrode, 4 is an extraction electrode extending from the gate electrode 3, and 5a and 5b are source or drain diffusion layers. , 6 is a wiring diffusion region, 7 is a thick field insulating film, 8 is an aperture region in the thin insulating film at the connection between the extraction electrode 4 and the diffusion region 6, and 9 is a diffusion region from the extraction electrode 4 through the aperture region 8. 3 shows a buried contact region formed by doped impurities. As is clear from the figure, the wiring diffusion region 6 extends in the X direction with the same 111, and this and the part of the extraction electrode 4 extending in the Y direction with the same 111 are separated from the field insulating film 7 to the right in the figure. By the way, they are perpendicular to each other, and a deep buried contact region 9 is formed at this remote location. That is, the wiring diffusion region 6 extends in the X direction with its end side 6' in contact with the field insulating film 7, and is a little farther from the field insulating film 7. Therefore, even if misalignment occurs, a sufficient contact area is ensured. Further, the gate electrode 3 and the extraction electrode 4 are made of polycrystalline material 3b containing impurities in the base,
4b, and heat-resistant metal JW3a and 4a such as molybdenum and tungsten located above it, the resistance is determined by the heat-resistant metal layer with low resistivity, and the layer resistance should be 1Ω10 or less. is easy. Regarding the stability of the threshold voltage, the polycrystal 3b containing impurities at the bottom of the gate electrode 3 is in contact with the gate insulating film 2.
Therefore, characteristics equivalent to those of a silicon gate field effect semiconductor device can be obtained. In the area where the extraction electrode 4 and the semiconductor substrate 1 are in direct contact, impurities diffused from the impurity-containing polycrystalline silicon 4b at the lower part of the extraction electrode 4 through the opening 8 form a buried contact region 9 deeper than other parts 6. Since the polycrystalline silicon 3b is formed, it becomes a highly reliable contact structure.

If the polarity of the impurity contained in 4b is selected to be the same as that of the diffusion layer region 6, the electrical connection between the extraction electrode 4 and the wiring diffusion layer region 6 can be established via the buried contact region 9. Since it can be formed without the aid of a metal wiring layer or the like, the degree of integration can be significantly improved.

Next, referring to FIGS. 2(a) to 2(e), an N-channel type MO3 field effect semiconductor device as an embodiment of the present invention will be described along with a typical manufacturing method thereof.

A thick field oxide film 17, a thin gate oxide film 12, and the same thin oxide film 12' are simultaneously formed on the surface of the P-type silicon substrate 11 by a known oxidation method, and an opening 18 is provided in the buried contact region (a second Figure (a)). Next, a polycrystalline silicon layer 20 doped with phosphorus is formed and heat treated to diffuse phosphorus from the polycrystalline silicon layer 20 into the silicon substrate 11 through the opening 18 to form a deep buried contact region 19 (first step). Figure 2 (b)
). Next, a gate electrode 13a and a wiring lead electrode 14a made of a molybdenum layer are successively formed (FIG. 2(C)). Next, a gate electrode 1 made of a molybdenum layer
By etching and removing unnecessary parts of the polycrystalline silicon layer 20 using the gate electrode 13a and the extraction electrode 14a as a mask, a polycrystalline silicon layer containing phosphorus is formed under the gate electrode 13a made of a molybdenum layer and the extraction electrode 14a. Gate electrode 13b and extraction electrode 14
b, and the gate electrode and the extraction electrode have a two-layer structure of polycrystalline silicon containing molybdenum and phosphorus. Next, gate electrodes 13a, 13b and extraction electrode 14
Using a and 14b as a mask, arsenic ions are implanted to form an activation heat treatment diffusion region 16. This results in both having the same bonding depth. The opening 18 and the extraction electrodes 14a, 14b are positioned so that the wiring diffusion region 16 and the buried contact region 19 are connected (
Figure 2(d)). The stage in Figure 2(d) is the stage in Figure 1(b).
Corresponds to the structure shown in . Generally, after this, the insulating film 21
After forming contact openings 23a and 23b reaching the source and drain diffusion regions 15a and 15b,
Metal wiring layers 22a and 22b are formed to complete the semiconductor device (FIG. 2(e)).

Although this embodiment describes an N-channel type MO3 field effect semiconductor device, the present invention is not limited thereto. For example, if the semiconductor substrate 11 is of N type and the impurities contained in polycrystalline silicon layer 20 and the impurities for forming source and drain diffusion regions 15a and 15b are of P type, a P channel type field effect device can be obtained. Furthermore, the material of the gate insulating film 12 is not limited to silicon oxide, but may also be, for example, silicon nitride or a composite film of silicon nitride and silicon oxide.

Further, although the buried contact diffusion region 19 is formed before forming the gate electrode 13b and the lead electrode 14b made of polycrystalline silicon, the invention is not limited to this.
After forming the extraction electrode 1.4 a as a mask,
That is, it is possible to form a buried contact diffusion region by heat treatment in the step shown in FIG. 2(C). In addition, in FIG. 2, molybdenum is used for the gate electrode 13a and the extraction electrode 14a.
Although the example is shown in which it is used as a metal, a heat-resistant metal such as tungsten can also be used.

As described above, according to the present invention, silicon gate type MO
3. A gate electrode that has a stable threshold voltage equivalent to that of a field effect device and a resistance value that is about 1/10 or less compared to a silicon gate type, and a gate electrode or an extraction electrode from the gate electrode and a wiring diffusion region. Since a means for realizing electrical connections with sufficient reliability without the aid of other metal wiring layers can be obtained, the degree of integration and high speed of semiconductor devices can be improved.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing the configuration of an embodiment of the present invention.
FIG. 1(b) is a sectional view taken along line A-B in FIG. 1(a). FIGS. 2(a) to 2(e) are cross-sectional views showing a typical manufacturing method for realizing an embodiment of the present invention in the order of steps. In the figure, 1... semiconductor substrate, 2... gate insulating film, 2'... thin insulating film, 3... gate electrode, 4... lead-out electrode, 4'... lead-out electrode ends, 5a, 5b... source or drain diffusion layer, 6...
・Diffusion area for wiring, 6′... Edge of diffusion area for wiring,
7゜17... Field insulating film, 8, 18... Opening region, 9.19... Buried contact region, 11.
... P-type silicon substrate, 12 ... Gate oxide film, 12
′... Thin oxide film, 20... Polycrystalline silicon layer,
16... Wiring diffusion region, 21... Insulating film, 23a
, 23b... contact opening portion, 22a, 22b...
・Metal wiring layer. Figure 1 (α) Figure (b)

Claims (4)

[Claims] (1) A thick field insulating film partially buried in the main surface of the semiconductor substrate is selectively provided, and an elongated diffusion region for wiring extends in one direction with its edge in contact with the field insulating film. A semiconductor having a source region and a drain region each extending partially from the main surface of a semiconductor substrate, and having a gate electrode on a region between the source region and the drain region with a gate insulating film interposed therebetween. In the device, the gate electrode and the extraction electrode extending from the gate electrode have a two-layer structure consisting of polycrystalline silicon containing impurities and a heat-resistant metal located thereon, and the extraction electrode extends from the gate electrode. The extraction electrode extends in a direction perpendicular to the one direction, intersects the wiring diffusion region at right angles, and terminates at a point passing through the wiring diffusion region, whereby the field insulating film of the wiring diffusion region A portion of the main surface near the edge that is in contact with and spaced from the edge contacts a portion of the main surface near the terminated end of the extraction electrode and spaced from the end, where the extraction electrode and the wiring diffusion region are connected to each other. (2) The portion of the wiring diffusion region that is in contact with the lead-out electrode is formed of impurities diffused from the polycrystalline silicon, and the source, drain region, and other wiring diffusion regions are formed of impurities diffused from the polycrystalline silicon. The device has a buried contact region formed deeper than the other portion, and with this configuration, the deep buried contact region is provided at a location spaced apart from an edge of the wiring diffusion region in contact with the field insulating film. Claim No. 1 (1)
) The semiconductor device described in item 1. (3) As set forth in claim (2), the other portions of the wiring diffusion region excluding the buried contact region are formed at the same depth as the source and drain regions. semiconductor devices. (4) An insulating film thinner than the field insulating film is provided on other parts of the wiring diffusion region other than the part in contact with the extraction electrode and the vicinity thereof. The semiconductor device according to item (1).