JPS5842252A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a required and fine field region by self- alignment, by a method wherein impurities having the same type of conduction as that of a substrate are doped in a groove part provided on the substrate and an insulating material is filled up to the opening of the groove. CONSTITUTION:A p type silicon substrate 101 where a mask material 102' is formed is etched to form a V-shaped groove 103 having a side with an inclination of angle theta. After impurities having the same type of conduction as that of the substrate 101 are provided on the substrate 101 by the ion implantation, heat treatment is performed to form a p<+> region 104, a channel stopper region, at the bottom of the groove 103. After the mask material 102' is removed, SiO2 is piled to (acot(theta/2))/2 or more in the thickness of its film by the CVD method. Then a CVD SiO2 film 105 is formed in such a way as to fully fill the groove part up to its opening. By etching the whole of this until the silicon substrate part 101 except the groove part 103, a field region 106 that is buried in the substrate 101 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to an IC, L8
The present invention relates to a manufacturing method that improves the inter-element isolation technology such as No. 1.

Conventionally, a selective oxidation method has generally been used as a method for isolating elements in the manufacturing process of semiconductor devices*K MO81, 81. This method will be explained below using the n-channel MO8L81 as an example.

First, a 5SO2 film 2 is grown by thermal oxidation on a p-type 81 substrate 1 having a (10G) crystal plane as shown in FIG. Next, a resist film 4 is formed in the element formation area by photolithography, and using this as a mask, the 511iNJ film other than the element formation area is etched away to form an 815N4 noturn S'. For example, ions of Iron are implanted to form a p''l region 5 as a channel stock/4 region in the field portion (as shown in FIG. 1(b)).
, After removing the resist film 4, wet oxidation is performed using the 813N glossy turn S' as a mask to selectively grow a thick field oxide film 6 (as shown in FIG. 1(, )). ' and 8102 film 2 are removed by etching to form element formation region 1 separated by field oxide film 6 (X shown in FIG. 1(d)).
As shown in FIG. 1 (), the element forming region 1 is made of polycrystalline silicon with a 2-oxide film I interposed therebetween. -) After forming the electrodes, for example, diffuse arsenic to form sources and drains? A region 10°JJ is formed. Finally, CVD-glozl as an interlayer insulation film! Deposit J J? Area 10
．． 11 and r-) electrode jlIfc corresponding CVD-81
After opening contact holes 13... in the 02 film 12 portion, forming the muL interconnections 14... and forming the difficult channel MO
8L8I is manufactured (No. 15!! (f) shown).

However, using the conventional selective oxidation method mentioned above, MO
The method for producing gLllI had various drawbacks as shown below.

Figure 2 shows 8M! shown in Figure 1 (@) above! The field oxide film 6 is formed using the 1N4A turn S' as a mask, and the structure at 9 o'clock is detailed. Generally, in the selective oxidation method, it is known that the field oxide film 6 grows by digging into the region below the 813N4d turn 5' (region ? in FIG. 2). This means that during field oxidation, the oxidizer
13N4-RI-73' The part where the oxide film is formed at the ninth point where it diffuses through the thin 02 film 2, the so-called bird's beak, and the part where the thick part of the field oxide film C has also sunk in laterally. For example, the thickness of another 5N4/Lean 3' is 100OA.

When the field oxide film 6 of the 8102 film 2 of 1 sm thick is grown under IGOOA conditions, the 8102 film 2 reaches approximately 1 trend. Therefore, the width C of the field area is 815N
4) If the distance A between the turns 3' is 2Jea, F is 1411, so 4. LS cannot be made smaller than #11
This is a major hindrance to the integration of I. For this reason, recently, a method has been developed to suppress bird C-driving (portion D in the figure) by increasing the thickness of the 813N pattern S' and thinning the 8102 film 2 underneath, and the growth film of the field oxide film 6. Attempts have been made to reduce the thickness of the field oxide film to suppress the field oxide penetration. However, the former increases the stress at the field edges and is more likely to cause defects, while the latter causes problems such as field inversion voltage drop. The problem is that there is a limit to the high integration achieved by selective oxidation.In addition, the ions implanted for channel stops/holes re-diffuse laterally during field oxidation, as shown in Figure 3. (
As shown in 1), when a part of the element formation region 1 becomes the p0 region 5, the effective element region becomes narrower than the width of G by MOmit.As a result, the current of the transistor decreases and the threshold Naroch channel effects, such as an increase in value voltage, occur, which becomes a problem as devices become smaller.

Moreover, I am happy that the P0 area 5 expands laterally.
g(b) in the element formation region 7 like o? Area 11 (1
0) and p0 region 5 is wide], n0 region 10.
11 and the substrate 1 becomes large. This floating noise cannot be ignored as the device becomes smaller.

The present invention has been made to solve the above-mentioned problems, and aims to provide a method for manufacturing a semiconductor device that achieves high integration and high performance by establishing a new element isolation method. .

The present invention will be explained in detail below.

First, a portion of a semiconductor substrate where a groove is to be formed is removed and a nine-mask material, for example, a four-turn resist, is formed, and then the portion of the substrate exposed from the mask material is selectively etched to a desired depth to form a groove. In this case, the inclination angle O of the side surface of the groove is O'
(Ij (9Q'). Etching may be done by selectively etching a (100) silicon substrate with KOH to give a certain degree of inclination angle 0, or by etching with a method that involves a lot of i-9 side etching. - You may also use reactive ion etching or the like.The number of grooves.

One or more grooves may be provided in the substrate, and the depth and width of the groove may be changed.

Subsequently, after removing the mask material, the insulating material is deposited in the half including the groove, and the insulating material is filled up to the opening of at least one groove. Examples of such insulating materials include 8102 and 81a.
Examples of the method for depositing the ζO1@ edge material include Na or *z2o3, and PVD methods such as the CVN method and the S/Naka-vine method. In addition, during this deposition, if the insulating material is deposited to a thickness smaller than (a cot(#/2))/2, where a is the short width of the opening O of the groove, the insulating material will be deposited in the groove. A concave hole communicating with the opening is formed in the insulating material, which causes the inconvenience that the insulating material within the groove is etched through the concave hole during etching. Note that a channel stopper region may be formed in the substrate by selectively doping an impurity of the same conductivity type as the substrate in the trench before depositing the insulating material.
In addition, prior to the deposition of the insulating material, the entire semiconductor substrate having the groove, or at least a part of the groove, is oxidized or nitrided to an extent that the groove is not blocked, even if a nitride film is grown. By using such a method in combination, the obtained field region-shaped groove substrate Kll is composed of a highly dense nine-oxide film or nitride film and an insulating material formed by deposition. Element isolation performance can be significantly improved compared to OK, which is made only of the following materials. Furthermore, it may be doped with insulating arsenic or the like, heat treated, and subjected to a wrinkle-resistant treatment such as ferrous silica glass (BAG) or phosphorus sulfide glass. By repeatedly using such a method, if the part corresponding to the groove becomes concave due to the deposition conditions of the insulating material, the concave part can be flattened, and as a result, the insulating material remaining in the groove can be removed when the entire surface is etched. This has the effect of preventing the inconvenience of the opening being below the level of the opening.

Next, the insulating film deposited on the semiconductor substrate is removed by etching without using a mask material until the semiconductor substrate parts other than the groove are exposed, leaving the insulating material in the groove 11! Form a field area. As the etching means in this process 11, for example, an etching liquid or! A nine-plane etching method using a laser beam, a reactive ion etching method, etc. can be employed. Thereafter, active elements such as MOS and piezo elements are formed in the element formation regions separated by the field regions to manufacture a semiconductor device.

According to the present invention, a groove having an inclined side surface and an inclination angle 0 in a range of O<#<90' is provided in a semiconductor substrate, and at least one insulating material is applied to the entire surface of the substrate including the groove. Let the short width of the opening of the groove be 1 and 9 (a e
After depositing the insulating film to a thickness of 72 or more, the insulating film is etched until the parts of the substrate other than the groove are exposed. Since an insulating material can be left in the luer alignment and a shift field region can be formed thereby, a semiconductor device having various effects as shown below can be provided.

(1) Area of the feel r area Since it is determined by the area of the groove provided in advance on the substrate, the area of the groove can be reduced.
Therefore, it is possible to easily form the desired fine field region and obtain a highly integrated semiconductor device. Also, since current leakage between elements can be reliably prevented in the field region, a high-performance semiconductor device can be obtained.

(3) Create a groove and create a channel straight horn! After selectively doping the trench with impurities, the impurity region is re-diffused and the element forming region is heated, which eliminates the need for high-temperature, long-term thermal oxidation as in the conventional selective oxidation method. It extends to the surface and can prevent the effective element formation area from being reduced. In this case, if the impurity doping is performed by ion implantation, the concentration of the impurity ions will be higher at the bottom of the groove,
Because it becomes thinner on the sides, the high concentration impurity region in the surface layer (element forming part) Kl of the element forming area does not extend even if it diffuses during the subsequent thermal process. Rounding prevents reduction of the effective element forming area. At the same time, it is possible to prevent the impurity region of the element forming portion from being inhibited.

(4) When the feel r region is formed by leaving the insulating material in all of the groove portions, it is possible to prevent the substrate from being rounded during flattening and from causing breakage during the subsequent formation of electrode wires.

Next, the second invention will be explained in detail.

An insulating material is deposited on a semiconductor substrate using the same steps as in the first aspect of the present invention described above and using the same conditions as in the first aspect of the present invention. Next, at least one of the insulating material region that is filled up to the opening with the insulating material and includes a part of the round groove portion, or the region of the insulating film that is to become the field region other than the groove portion is covered with a masking material, such as a resist. Then, etching is performed until the mask material and parts of the substrate other than the groove are exposed, and the insulating material is left in the groove to form a field area, and a field area is also formed on the substrate other than the groove. Form. In this case, the field regions formed on the substrate other than the trench include those integrated with the field region of the trench, and then the element forming regions Ki[)8, etc., which are separated by the field region, etc. A semiconductor device is manufactured by forming active elements.

According to the second invention of the present application, in addition to having the various effects described above, the field region embedded in the semiconductor substrate and the field region integrated with or separated from the field region on the semiconductor substrate other than the groove portion are provided. A semiconductor device having field regions having different shapes can be obtained.

Next, an example in which the present invention is applied to the manufacture of an n-channel MD8LSI will be described with reference to the drawings.

Example 1 [1] First, a mass young material film XOZ such as an oxide film is deposited on a PWIl silicon substrate 101 having a (10G) crystal plane as shown in FIG. The mask material 102' was formed by /l turning (as shown in FIG. 4(b)), and then the mask material 102'
The silicon substrate 101 was etched with KOH, for example. At this time, as shown in Fig. 4 (@) K, the inclination angle -
A V-shaped groove portion 10B having side surfaces of . Continuing.

The substrate 101 is coated on the substrate 101 using the same mask material 102'.
Although it is an impurity of the same conductivity type, Ron is accelerated at a voltage of 50 k@
After injecting ions in an amount of V%l'-1 of 5X 10"761104, a heat treatment was performed to form a p0 region 104 as a channel stocking region at the bottom of the groove 103 (see FIG. 4) [11] After removing the mask material 102', 8
10! The film was deposited using the G method so that the film thickness was (a@·t(e/2))72 or more, where a is the width of the opening of the groove 103. At this time, 5io2 is gradually deposited on the substrate 101 and inside the groove 101, and is fully buried up to the opening of the groove 101 as shown in Fig.
A film 1015 was formed at -810. This situation will be explained in detail with reference to FIGS. 5(a) and 5(b). -Wo3 (to) -8102 membrane with sides of - inclination angle.

As 105 is deposited, the film thickness becomes 1051°1.
06..., the groove 103 gradually becomes shallower, and the intersection of the bisector LlsL1 of the angle ψ where the surface of the substrate 101 intersects the side surface of the groove 103 also becomes CVD-
8102 film 105 is thickly deposited (cvn-sto2 film 10
15), the groove 103 becomes Jl (as shown in FIG.
The thickness of the film 105 will be determined with reference to FIG. Inclination angle of the groove 108 - 1 If the width of the opening is a, then a simple calculation can be made. Despite the resolution, almost no re-diffusion of the p4 region 104 occurred. However, the mask material 102' does not necessarily have to be removed in this step.

(iii) Next, the entire surface of the -8102 film 105 is etched using ammonium fluoride, plasma etching, reactive ion etching, etc. until the silicon substrate 101 portion other than the groove 108 is exposed. At this time, the -8!02 film portion on the substrate 101 is removed by the O film thickness, and cv'D-8102 remains only in the groove 103 as shown in FIG.
A field region 1011 in which KJI was embedded within 01 was formed. Thereafter, according to a conventional method, the field regions 10C are separated, and nine island-shaped element formation regions Kr-) are formed of polycrystalline silicon via an oxide film 101. -) Form the electrode 108 and perform arsenic diffusion to form the electrode 11 as the source and drain.
° regions 109 and 110 were formed.

Furthermore, a glabellar insulating film 111 made of cvn-sio2 is deposited, and the r-) electrode 1011 and the ? Area 109°110
A contact hole 1 is formed in a portion of the interlayer insulating film 111 corresponding to
12...(?-) Electrode contacts and holes are not shown) After opening a hole, a KAt film is deposited on the electrode, the electrode is separated, and the electrode 113. Drain takeout At
Electrode 114 and r-) are taken out to form an electrode (not shown) to form an n-channel! KJBL81 was manufactured (Fig. 4 (-illustration)).

In the nine MO51L81 obtained in Example 1, when the field area 106 is determined by the width of the groove 103, the width can be made into an extremely narrow area of one width, reducing the area of the field area occupied in the LSI. technology, and by extension, achieved high integration. In addition, if a field oxide film C with a narrow width is formed using the conventional selective oxidation method as shown in FIG. On the other hand, as shown in FIG. 7, the field region 10g of Example 1 had a narrow width of 4 and a sufficiently deep depth, so that K,
The channel length (L') between the elements could be made sufficiently long, and leakage current could be prevented from flowing between the elements.

Furthermore, the silicon substrate 10 after the field region 106 is formed
1 is flat with no step between the field region and the element formation region as shown in Figure (f) of Is4 of the above-mentioned process, so when electrodes 111 and 114 are formed, there is no step between the field region and the element formation region. Since the p0 region 104, which serves as a channel stop horn region, is not subjected to heat treatment such as field oxidation, it diffuses to the element formation region, resulting in deterioration of device characteristics due to the narrow channel effect, etc. and male regions 109, 110 as sources and drains (m0 regions 1011, 1 due to 011 coupling)
It was possible to prevent an increase in stray capacitance of 10. Furthermore, since there is no field oxidation as in the selective oxidation method, it is possible to prevent defects in the silicon substrate due to stress caused when the field oxide film digs under the 811NJ film.

Note that in the first embodiment, after forming the mask material 102' such as an oxide film on the silicon substrate 101, this mask material 102' is formed on the silicon substrate 101.
2′ was used to provide the groove portion 108 in the substrate 101.
As shown in the figure (,), an insulating film 11 is formed on a silicon substrate 101.
5, a resist/mother turn 116 is formed thereon, and using this as a mask, the dielectric film 111 is etched by reactive ion etching to form the opening 11.
1, and further provide a substrate 1011/C groove 103 therebelow, and perform impurity ion implantation using the resist as a mask without removing the resist (as shown in FIG. 8(b)).

Moreover, in this case, as shown in FIG. 9(1), the silicon substrate 101
A groove 103 may be formed by forming a resist I lean I1g directly on the surface and using this as a mask for machining and cindering (as shown in FIG. 9(b)).

Embodiment 2 [1] First, as shown in FIG.
Three types of grooves J 03.10B', J all'' having different sloped side surfaces as 1 e s, * s= were provided.The opening widths are in a relationship of 81<8B<8°. Next, 5to2 was processed using the CVD method) (s,
It was deposited so that it was slightly thicker than cOt(#/ri)/2. At this time, as shown in FIG. 10(b) K, the groove 103°1
03', the CVD-8iOz film 105 is sufficiently weired to the opening, but the CVD-8102 film 106 is deposited on the inner periphery 11fKL of the groove 103'', which is wider than the grooves 108 and 103'. A concave depression 118 was formed.

[i:] Next, (to) -8102 on the substrate 101
After etching with ammonium fluoride to the thickness of the film 105, the width of the opening was 8.9 mm, as shown in FIG. 10 (@)K. ．． 8
．． 0 groove part 10 s, J Os'KBCvD-sio,
was left behind to form a predetermined field area 106°106', and all of the cvn-8101 within the groove 10s'' was removed to form a concave portion.
It can be used as a 7MO8 area, etc., and a photo-etching process 1 can be used to create a recess after forming a field area.

Example 3 First, as shown in FIG. 11, <pml! Silicon substrate 101
A groove 10j" having an inclined side surface whose width at the bottom of the opening intermittently changes from 81 m to 8 s was formed by photoetching using reactive ion etching. The size of the opening width in relation to fl/is the relationship as < B dew < 8.
2 was deposited using the ■ method so that it was slightly thicker than l(81cot(6/2))/2. After thoroughly consolidating and depositing 1 ftK on the inner circumference in the part where the opening width is SI, etching was performed with fluoride annealing by the thickness of the OCVD-8102 film on the substrate 101, resulting in an opening as shown in FIG. 11(b). Part width is si # 81 part CVD -81 (
h II 1 o J was left and the portion #1s1 was removed to obtain an open field region leg''.

Embodiment 4 [1] First, as shown in FIG. 12(a), a plurality of groove portions 1081, 108.108. .

After setting 1011.10:14, 5102 was made by CVD method and the width of the opening of each groove 1031...1034 was a.
A CVD-8102 film 1015 was formed by depositing the film to a thickness of (a not (#/2))/2 or more (as shown in FIG. 12(b)).

(ii) Next, a portion of the CVD-8102 film 105 extending from the substrate 101 to a part of the groove 103g and the groove 10
8.0 CVD-51 warping from a part to a part of the groove part 10S4
10! CVD-110 on the film 106 part and the substrate 101
A resist film 11 is formed on each part of the Z film 105 by photolithography.
#, covered by ~119s (as shown in No. 1211(e)). After that, the resist films 1191 to 119s and the groove portion 1011
When etching was performed using ammonium fluoride, plasma etching, or reactive ion etching at 4t when the parts of the substrate 101 other than 1034 were exposed, the field region 10g where CVD-8102 remained in the groove 1011 as shown in FIG. 12(d). m1i left in groove 103
02 and nine CVD-8102 left on the substrate 101 are integrated into a field region 7011. Groove 10
Leave it on 8j and 1084 & CVD-aio2 and board 1
The remaining position CVD-11102 is integrated on the 0°1 field area J##1 and the substrate 101.
A wide field region 10#1 made of VD-102 is left on top of the silicon substrate x.
8) Field region 1061.10g of the form in which OCVD-8102 $ is left on the substrate 101 when a plurality of transistors are provided according to the orlIC conventional method.

Wiring could be formed using 106''.

Example 5 [1] First, the pH silicon substrate 101VC has a groove portion 1011 having three inclined side surfaces each having the same opening width.
．． 1031. After providing 108 m, groove portion 101. , 1111. A resist/mother turn 119' was formed by removing the portion of the substrate 101 between them (see FIG. 13()).
), the groove portions 103, . 1011@group between @1ot1e
tlI! After etching the surface to form a removed portion 121j, the resist I4 turn 119' is removed (as shown in FIG. 13(b)). When the width of each groove 1011 to 103@ is a, (a
The film was deposited to be slightly thicker than 5et(#/2)/2. At this time, as shown in FIG. 13(), the groove 1031.
...The opening of 101 m is sufficiently gathered up by the (7)-8i02 film 105, and the α corresponding to #central part 1201C>
5j02 membrane J Oj' part was more depressed than other areas.

(tlD) Next, as shown in FIG. 13 (4) K, after covering the depressed G-5toz film 105' portion by the photoetching method with a resist film 121, the resist film 121 and the groove portion 1 are
When etching is performed using ammonium fluoride, plasma etching, or reactive ion etching until the parts of the substrate 101 other than #11...103s are exposed, groove portion 1 is etched.
0B,...1 in 103s (field area 10σl1-1a@ left by CVD-8102 and groove J OI
A wide CVD-m that is integrated with the CVO-stto2 of ss J Ojs and whose top surface is at the substrate 1010 level.
A field region Jag" consisting of 1i02 was formed (as shown in FIG. 13(-)).

1t) Molded silicon substrate according to IK standard method
) When providing multiple transistors, 0CYD- on the board 101
Wide field area 10IIF'' consisting of 111oz
In addition, since the field region 10.l//// is at the same level as the substrate 101, it was possible to prevent the wiring from breaking.

Next, another embodiment of the present invention will be described.

(B) In the above embodiment, a V-shaped groove was used, but the groove is not limited to this, and a groove with a flat bottom may be formed on the substrate 101 as shown in FIG. 14. The thickness of the insulating metal is the same as described above (a e o
* (#/2))/2 or more.

(b) The shape of the groove part does not necessarily have to be flat on the side surfaces, and as shown in FIG. If the inclination angle of the 0III plane at the opening of the groove 303 is 0, the thickness of the
t (#/2))/2 or more.

As shown in FIG. 16(,), a film 122 with a high etching rate such as a phosphorous-doped glass film (PEG film) is deposited on the substrate 101, and a mask material such as a resist I-lean 116 is formed. The coating 1 is applied as a mask.
22. The substrate 101 is coated with, for example, a fluoronitric acid-based etching solution, 7
"?The structural part gos having an inclined side surface may be formed by etching with an etching solution or the like (see Fig. 16(b)).
).

2) As shown in FIG. 17(a) K, an insulating film 115 such as an oxide film is deposited on the substrate 101, and after this is exposed to a gas masking atmosphere, a mask material 1, for example, a resist pattern 11g is deposited.
is formed, and using this as a mask, the insulating film 115 and the substrate 1
01 may be etched to form the groove portion 101 (as shown in FIG. 17(b)).

(e) As shown in FIG. 18(a) K, a groove portion 101 having an inclined groove 101 having a nine-sided shape is formed in the substrate 101, and an insulating film 11 is formed.
When depositing 5 and etching it, it is not necessary to deposit 5 on substrate 1.
It is not necessary to etch until the 01 is exposed, and the 18th
As shown in Figure (b), the insulating film 11g' is etched to remain on the surface of the substrate 101 other than the field region 1011, and this remaining insulating film 115' is etched. -) It may be used for an insulating film, an interlayer insulating film, etc., or as a part thereof.

(to) Figure 19 (a) As shown in K, the pull 0 on the board 101
An insulating film 115 is deposited with the mask material 10 f' left behind, and then the mask material 1
The field region 106 may be formed by etching the insulating film 118 so that 02' remains (as shown in FIG. 19(b)).

(g) As shown in FIG. 20, an insulating film 105' is left in a groove 1011 having an inclined side surface of the substrate 101 so as to extend in the center in an arc shape from the substrate surface, and a field region 105' is formed.
6 may be formed.

As described in detail above, according to the present invention, an arbitrary and fine field region can be formed in the trench by self-line without taking mask alignment margin, thereby achieving high integration, high reliability, and high performance semiconductor devices. It is possible to provide a method for manufacturing

[Brief explanation of drawings]

Figures 1(,) to (f) show 9n using the conventional selective oxidation method.
Cross-sectional view showing the manufacturing process of channel MO8L8I, 2nd
The figure is an enlarged new view showing the state of the semiconductor substrate after selective oxidation of the cage, Figures 3(a) and 3(b) are rounded cross-sectional views illustrating the problems of the conventional selective oxidation method, and Figure 4 Figure (a) ~ ω
6511. is a cutaway diagram of the MO1iiLSI in the IGC according to the embodiment of the present invention. FIG. 7 is a cross-sectional view showing O-LL-5 condensation between nine elements formed by the conventional method and Example 1 and separated by nine field regions; FIGS. 8(a), (b), and 99(a) e
Cb> is the groove formation t showing the honey-shaped example of the present invention 0 @ Example 1
The cross-sectional view of O1 potato, Figure 10 (,) to (,) is the main W1
11(a) and 11(b) are plan views showing field area forming process 1 of MO8L81 in Example 3 of the present invention. 12(,) to (d) are cross-sectional views showing the field region formation 1 of MO8LSI in Embodiment 4 of the present invention, and FIG. Cross-sectional views showing the formation process, FIGS. 14, 15, and 16 (a)
, (b), Fig. 17 (a), (b), Fig. 18 (a), (b), Fig. 19 (a), (b), Fig. 20 Other embodiments of the present invention FIG. 101...p'W1 silicon substrate, 102'...mask material, 103, 103', 10B': 103", 2
63%~x o s4°~106m...Field area, 10g...Dart electrode, 109,110...n
0 region (source, drain), l1g, 11-...A
T electrode, 115...Insulating film, rlr;...Resist-P turn. Applicant's agent Patent attorney Liao Suzu

Claims (1)

[Claims] 1. A step of providing at least one groove portion having an inclined side surface in a desired portion of a semiconductor substrate, the inclination angle of which falls within the range of O<#<900; and a semiconductor substrate including the groove portion. 12) Depositing an insulating material over the entire surface to a thickness of at least 1') 12) Denoting the short width of the opening of the groove as a (a eat (□)) A, and etching this insulating film. 1. A method of manufacturing a semiconductor device, comprising the step of leaving an insulating material in at least one trench to form a field region. 2. After providing a groove in the semiconductor substrate and before depositing an insulating material, oxidize or nitride the entire surface of the semiconductor substrate or at least a portion of the groove to grow an oxide or nitride film to the extent that the groove is not blocked. 2. A method of manufacturing a semiconductor device according to claim 1, further comprising the step of: 1 After forming a groove in a semiconductor substrate and before depositing an insulating material, an impurity having the same conductivity type as that of the substrate is selectively added to the groove.
3. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the semiconductor device is subjected to l peaking. A method for manufacturing a semiconductor device according to any one of claims 1 to 311, characterized in that the doped layer of the scissor-cutting film is melted by heat treatment, and then the insulating film is etched. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that the insulating film is melted and then the insulating film is etched. 6. The step of providing at least one part of the semiconductor substrate having an inclined surface at a desired portion and having an inclination angle of −Q(#(90°); A step of depositing the material to a thickness of at least (a cot (#/2))/2@44 where the short width of the opening part of at least one groove is a; After covering at least one of the areas of the insulating film including a part of the top of the groove that has been dammed up to the groove, or the area of the insulating film that is to become a field area other than the groove with a mask material, the insulating metal is removed. A semiconductor device comprising the steps of: etching the semiconductor substrate other than the mask material and the groove, leaving an insulating material in the groove to form a field region, and forming a field region in addition to the groove. 7. After the grooves are formed in the semiconductor substrate, before depositing the insulating material, the entire surface of the semiconductor substrate or at least a part of the grooves is oxidized or nitrided to an extent that the grooves are not blocked. 8. A method for manufacturing a semiconductor device according to claim 6, characterized in that an oxide film or a nitride film of A method for manufacturing a semiconductor device according to claim 6 or 7, characterized in that the semiconductor device is selectively doped with an impurity of the same conductivity type as the substrate. Claims 6 to 8 are characterized in that the doping layer is melted, and then the mask material is covered and the insulating film is etched.
A method for manufacturing a semiconductor device according to any one of paragraphs. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the meltable insulating film is melted, and then the insulating film is covered with a mask material and etched.