JPH04179239A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor substrate from being etched at the part of a contact hole when an etching operation to form a gate electrode is executed and to prevent a groove from being formed by a method wherein a first conductor film and a second conductor film are patterned and the gate electrode which is overlapped with the end part of a gate insulating film is formed. CONSTITUTION:A resist pattern 8 for electrode formation use is formed, by lithography, on a high-melting-point metal silicide film 7 in such a way that a contact hole C for contact use is covered completely. The high-melting-point metal silicide film 7 and polycrystalline Si films 6, 4 are etched sequentially in a direction perpendicular to the surface of a substrate by an RIE method; after that, the resist pattern 8 is removed. Thereby, gate electrodes G1, G2 of polycide structure are formed. At this etching operation, the contact hole C is covered completely with a part corresponding to the gate electrode G1 in the resist pattern 8, and a semiconductor substrate 1 is not revealed in the part of the contact hole C. As a result, the semiconductor substrate 1 in the part of the contact hole C is not etched and there is no fear that a groove is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a semiconductor device using t).

[Summary of the invention]

This invention provides a method for manufacturing a semiconductor device, in which an element isolation insulating film and a gate insulating film are selectively formed on the surface of the semiconductor device, and a buried contact portion is formed between the element isolation insulating film and the gate insulating film. A first conductor film is formed on the formed semiconductor substrate, at least the first conductor film in the buried contact portion is removed, and oblique ion implantation is performed on the semiconductor substrate in the buried contact portion, and a second conductor film is formed on the semiconductor substrate. form the first
By patterning the conductor film and the second conductor film to form a gate electrode that overlaps the edge of the gate insulating film, even if the junction depth of the diffusion layer becomes shallow, the buried contact area in the semiconductor substrate can be formed. It is possible to improve the conduction between the diffusion layer formed in the semiconductor substrate and the diffusion layer of the transistor formed in the semiconductor substrate in the adjacent portion.

[Conventional technology]

The buried contact is, for example, MOS Scutinok RA.
In M, it is used when a gate electrode is brought into contact with a diffusion layer formed in a semiconductor substrate. Conventionally,
When making a buried contact with a gate electrode formed using a polycrystalline silicon (Si) film, the surface of the gate oxide film in the area other than the contact hole formation area for the buried contact is roughened and covered with a polycrystalline Si film. A known technique is to prevent the gate oxide film from being etched during light etching to remove the native oxide film formed on the substrate surface in the contact hole area for buried contacts (Unexamined Japanese Patent Publication No. Showa 62-37967
Publication No.).

The buried contact technique disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 62-37967 will be described in detail as follows in the case where polycide is used as the gate electrode material.

That is, as shown in FIG. 2A, first the p-type Si substrate 1 is
After forming a field oxide film 102 and a gate oxide film 103 on the surface of 01, a first polycrystalline Si film 10 is formed on the entire surface.
4 is formed, and this polycrystalline Si film 104 is coated with, for example, phosphorus (P).
) to lower the resistance. After this,
A resist pattern 105 is formed on this polycrystalline Si film 104 in which a portion corresponding to a contact hole portion for the Helirad contactor 1- is opened.

Next, using this resist pattern 105 as a mask, the polycrystalline Si film 104 is etched to form the state shown in FIG. 2B.

Next, after removing the resist pattern 105, FIG.
As shown in FIG. 3, the gate oxide film 103 is etched using the first layer polycrystalline Si film 104 patterned by etching as a mask. As a result, a contact hole C' for a buried contact is formed. next,
A second layer of polycrystalline Si film 106 is formed on the entire surface, and after doping the polycrystalline Si film 106 with an n-type impurity such as P to lower the resistance, tungsten silicide is formed on this polycrystalline S1 film 106. (WSIX) film 107 is formed.

Thereafter, a resist pattern 108 having a shape corresponding to the Day 1 electrode to be formed is formed on this WSiX film 107.

Next, using this resist pattern 108 as a mask, W
After sequentially etching the SiX film 107 and the polycrystalline Si films 106 and 104, the resist pattern 108 is removed. As a result, gate electrodes 01' and 62' having a polycide structure are formed as shown in the second diagram.

Next, by performing heat treatment, the n-type impurity such as P in the polycrystalline Si film 106 is diffused into the p-type Si substrate 101 in the portion in contact with the polycrystalline Si film 106. As a result, as shown in Figure 2, the contact hole C
For example, an n-type diffusion layer 109 is formed in the p-type Si substrate 101 at a portion .

Next, an n-type impurity such as P is ion-implanted into the ρ-type Si substrate 101 at a low concentration using the gate electrode 61', Gz'' as a mask.Next, silicon dioxide (S
After forming the SiO□ film, the SiO□ film is etched in a direction perpendicular to the substrate surface using, for example, reactive ion etching (RIE) to form gate electrodes G+′,
A sidewall spacer 110 is formed on the sidewall of G2'.

Next, using the sidewall spacer 110 and gate electrodes G1' and G2' as a mask, the p-type Si substrate 10 is
For example, an n-type impurity such as arsenic (As) is ion-implanted into the 1st layer at a high concentration. After this, heat treatment is performed to electrically activate the implanted impurities. Reference numerals 111 and 112 indicate n-type diffusion layers, which are thus formed in the p-type Si substrate 101 in a self-aligned manner with respect to the gate electrode G2' and are used as source regions or drain regions. In these diffusion layers 111 and 112, for example, n-type low impurity concentration portions 111a and 112a are formed below the sidewall spacer 110.

[Problems to be Solved by the Invention] The conventional edge-throat contact 1 to technique shown in FIGS. 2A to 2E described above have the following problems.

That is, as shown in FIG.
The thickness of the film is smaller than that in other parts by the thickness of the polycrystalline Si film 104.

Therefore, during etching to form the gate electrodes 01' and Gz'', the p-type Si substrate 101 exposed inside the contact pole C' is etched and the second
A groove 101a is formed as shown in Figure L. moreover,
Since the P-type Si substrate 101 is also etched during etching to form the sidewall spacer 110, the groove 101a in the portion immediately adjacent to the sidewall spacer 1.1.0 becomes deeper.

As a result, contact hole C for buried contact
The conduction resistance between the diffusion layer 109 and the diffusion layer 111 in the portion ' is increased. In particular, when the junction depths of the diffusion layers 111, 112 and the low impurity concentration portions 11a and 112a become shallow, this increase in conduction resistance becomes very serious.

Therefore, an object of the present invention is to reduce the diffusion layer formed in the semiconductor substrate of the helirad contact I part and the semiconductor substrate of the adjacent part even if the junction depth of the diffusion layer becomes shallow. An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve conduction between a transistor and a diffusion layer.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, in which an insulating film for isolation between elements (2
) and a gate insulating film (3) are selectively formed, and a semiconductor substrate (1) in which a buried contact portion is formed between an element isolation insulating film (2) and a gate insulating film (3). forming a first conductor film (4) thereon, removing at least the first conductor film (4) in the buried contact part, performing oblique ion implantation into the semiconductor substrate (1) in the buried contact part;
Form a second conductor film (6, 7), and form a first conductor film (4).
By patterning the second conductive film (6, 7), a gate electrode (G
1).

[Effect]

According to the method for manufacturing a semiconductor device of the present invention configured as described above, the first conductor film (4) and the second conductor film (6
, 7) to form a gate insulating film (3).
), the semiconductor substrate (1) is not exposed in the contact hole (C) for buried contact, and therefore the first conductor film (4) and second conductor film (6,
During etching for patterning in step 7), it is possible to prevent grooves from being etched in the semiconductor substrate (1) at the contact holes (C) for edge contact.

On the other hand, a problem arises when the gate electrode (G()) overlaps the edge of the gate insulating film (3) as described above.
A diffusion layer (9) formed in the semiconductor substrate (1) in the contact hole (C) for contact and a transistor diffusion layer (13) formed in the semiconductor substrate (1) in the adjacent part. This continuity is between
The diffusion layer (10) formed by oblique ion implantation into the semiconductor substrate (1) in the contact hole (C) portion for buried contact can be used in a good manner.

As described above, even if the junction depth of the diffusion layer becomes shallow, there is a gap between the diffusion layer formed in the semiconductor substrate in the buried contact part and the diffusion layer of the transistor formed in the semiconductor substrate in the adjacent part. Good conduction can be achieved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A to the first diagram are MO3 according to an embodiment of the present invention.
A method for manufacturing an LSI will be shown.

In this embodiment, as shown in FIG. 1A, first, a field insulating film 2 such as a 5i02 film is selectively formed on the surface of a semiconductor substrate 1 such as a p-type Si substrate by, for example, the LOCO3 method. Performs isolation between elements. Next, a gate insulating film 3 such as a 5i02 film is formed on the surface of the active region surrounded by the field insulating film 2 by thermal oxidation. Next, after forming a polycrystalline Si film 4 on the entire surface by CVD, the polycrystalline Si film 4 is doped with an impurity such as P by thermal diffusion or ion implantation to lower its resistance. Next, on this polycrystalline Si film, a resist pattern 5 having a predetermined shape with an opening corresponding to a contact hole portion for a burried contact is formed by lithography, and then using this resist pattern 5 as a mask, for example, RI
A polycrystalline Si film 4 is formed in the direction perpendicular to the substrate surface using the E method.
The polycrystalline Si film 4 in the contact hole portion for the buried contact is removed by etching.

Next, after removing the resist pattern 5, using the polycrystalline Si film 4 patterned by etching as a mask, an n-type impurity such as P or As is applied onto the semiconductor substrate from a direction inclined at a predetermined angle with respect to the substrate surface. Inject ions diagonally inside. Impurities obliquely ion-implanted into the semiconductor substrate 1 are indicated by "." in FIG. 1B. As shown in FIG. 1B, by this oblique ion implantation, impurity ions are also implanted into the lower part of the gate insulating film 3 around the contact hole C for a buried contact, which will be described later.

Note that this oblique ion implantation may be performed while the resist pattern 5 is formed, depending on the case.

Next, using the patterned polycrystalline Si film 4 as a mask, the gate insulating film 3 is etched by a wet etching method using, for example, a hydrogen fluoride (HF) based etching solution. As a result, a contact hole C for buried contact is formed. Next, a polycrystalline Si film 6 is formed on the entire surface by the CVD method, and after doping the polycrystalline Si film 6 with an impurity such as P to lower the resistance, sputtering is performed on the polycrystalline Si film, for example. For example, a high melting point metal silicide film 7 such as a W Si film is formed by a method or a CVD method.
form.

Next, a resist pattern 8 for forming a gate electrode is formed on this high melting point metal silicide film 7 by lithography. In this case, among this resist pattern 8, a gate electrode G1, which will be described later, needs to have a buried contact.
The part that becomes the mask during etching to form the
It is formed so as to completely cover the contact hole C for buried contact, in other words, so that the contact hole C is located inside this portion.

In order to actually form such a resist pattern 8, a Fuji 1-1 for forming this resist pattern 8 is required.
On the mask, the pattern of the portion corresponding to the gate electrode G1 may overlap the polycrystalline Si film 4 around the contact hole C by a predetermined width l. Examples of the numerical values of l are as follows. That is, now the amount of misalignment between the contact hole C and the gate electrode G1 is set to 0.1μ.
m, the increase in the dimension of the actually formed contact hole C from the pattern dimension on the photomask is 0.1 μm.
, the reduction in the dimension of the actually patterned polycrystalline Si film 4 from the pattern dimension on the photomask is 0.1μ.
m, the total misalignment amount in this case is (0, 1
” +0.12+0゜12) ”” =0.17 g
mT: Since there is, it may be set to 220.2 μm, for example.

Next, using this resist pattern 8 as a mask, the high melting point metal silicide film 7 and the polycrystalline Si films 6, 4 are coated with, for example, RI.
After sequential etching in a direction perpendicular to the substrate surface using the E method, the resist pattern 8 is removed. As a result, gate electrodes G1 and G2 having a polycide structure are formed as shown in FIG. 1C. During this etching, as described above, the portion of the resist pattern 8 corresponding to the gate electrode G completely covers the contact hole C, and the semiconductor substrate 1 is not exposed in this contact hole C portion. There is no fear that the semiconductor substrate 1 in the contact hole C portion will be etched and a groove will be formed.

Next, by performing heat treatment, P in the polycrystalline Si film 6 is
An n-type impurity such as the following is diffused into the semiconductor substrate 1 in the portion in contact with the polycrystalline Si film 6. As a result, as shown in the first diagram, an n-type diffusion layer 9, for example, is formed in the semiconductor substrate 1 at the contact ball C portion. At the same time, the n-type impurity that was previously obliquely ion-implanted into the semiconductor substrate 1 in the ml contact ball C portion is diffused, so that, for example, an n" type diffusion layer 10 forms a gate around the contact hole C. It is formed to extend under the insulating film 3. Note that this diffusion layer 10 may be of n-type or n-type, for example.

Next, an n-type impurity such as P is ion-implanted into the semiconductor substrate 1 at a low concentration using the gate electrodes G, G2, G2 as masks. Next, after forming a SiC2 film on the entire surface, -this 5iO7 film is etched in a direction perpendicular to the substrate surface by, for example, RIE method to form sidewall spacers 11 on the sidewalls of the gate electrodes G, , G, do. In this case, since the semiconductor substrate 1 in the contact hole C portion is not exposed during etching to form the Zydrus vane 11, the semiconductor substrate 1 in the portion adjacent to the sidewall spacer 11 is etched. There is no risk of being etched.

Next, using the sidewall spacer 11 and the gate electrodes G, G2 as a mask, for example, an A.
N-type impurities such as s are ion-implanted at a high concentration. After this, heat treatment is performed to electrically activate the implanted impurities.

Reference numerals 12 and 13 indicate an n-type diffusion layer used as a source region or a drain region, which is thus formed in the semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode G2. In these diffusion layers 12 and 13, for example, n-type low impurity concentration portions 12a and 13a are formed below the sidewall spacer 11.

As described above, according to this embodiment, by etching the high-melting point metal silicide film 7 and the polycrystalline S1 film 6.4 using the resist pattern 8 as a mask, the cage around the contact ball C for the heliode contact is etched. A gate electrode G1 overlapping the end of the insulating film 3 can be formed together with the gate electrode G2. In this case, since the semiconductor substrate 1 is not exposed at the contact hole C during this etching, the semiconductor substrate 1 at the contact pole C is not etched during this etching or during the etching for forming the sidewall spacer 11. This can prevent the formation of grooves. As a result, as shown in the first diagram, the diffusion layer 9 formed in the semiconductor substrate 1 in the contact hole C portion and the diffusion layer 13 of the MOS transistor formed in the semiconductor substrate 1 in the adjacent portion Good conduction can be achieved by the diffusion layer 10 and the low impurity concentration regions 1 and 3a formed by oblique ion implantation. Even if the junction depth of the diffusion layer I2.13. and the low impurity concentration portions 12a and 13a thereof becomes shallow, good conduction can be achieved.

On the other hand, the conventional lift contact technology mentioned above,
By forming the groove 101a as shown in FIG.
01a, and there is a risk that a short circuit will occur between the wiring formed on this interlayer insulating film and the underlying wiring.

However, according to this embodiment, the semiconductor substrate at the contact 1 hole C for herint contact is not etched as described above, so there is no such fear.

The method according to the embodiments described above is applicable to, for example, a MOS static R
It is suitable for application in the case of making a herit contact of the gate electrode of a MOS transistor as an I-Liher transistor in AM.

Although the embodiments of this invention have been specifically described above, the invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of this invention.

For example, in the embodiments described above, the MOS transistor is a lightly doped transistor (LDD).
in) structure, but MO3h
The transistor does not necessarily have to have an LDD structure.

〔Effect of the invention〕

As explained above, according to the present invention, the first conductor film and the second conductor film are patterned to form a gate electrode that overlaps the edge of the gate insulating film, so that a buried contact is formed. The semiconductor substrate is not exposed in the contact hole area for the gate electrode, and therefore, it is possible to prevent the semiconductor substrate in the contact hole area from being etched and grooves are formed during etching to form the gate electrode. . In addition, since oblique ion implantation is performed into the semiconductor substrate Fi of the buried contact part, the diffusion layer formed in the semiconductor substrate of the buried contact part and this Good conduction can be achieved between the diffusion layer formed in the semiconductor substrate in a portion adjacent to the semiconductor substrate. As a result, even if the junction depth of the diffusion layer becomes shallow, there is a gap between the diffusion layer formed in the semiconductor substrate in the buried contact part and the diffusion layer of the transistor formed in the semiconductor substrate in the adjacent part. Good conduction can be achieved.

[Brief explanation of the drawing]

FIG. 1A to the first diagram are MO3 according to an embodiment of the present invention.
2A to 2E are cross-sectional views for explaining a conventional MO8 LSI manufacturing method using buried contacts in a step-by-step manner. The main symbols in the drawings are explained as follows: semiconductor substrate, 2: field insulating film, 3: gate insulating film, 4.6: polycrystalline Si film, 5.8 resist pattern, C: contact hole for buried contact, 7 : High melting point metal silicide film, C,, C2:
Gate electrode, 9.10.12.13: Diffusion layer. Agent Patent Attorney Tadashi Sugiura Tomo ＾ Me N +l7-n U] \Ding (N

Claims (1)

[Claims] An insulating film for element isolation and a gate insulating film are selectively formed on the surface thereof, and a buried contact portion is formed between the insulating film for element isolation and the gate insulating film. forming a first conductor film on the semiconductor substrate; removing at least the first conductor film in the buried contact portion; performing oblique ion implantation into the semiconductor substrate in the buried contact portion; A method for manufacturing a semiconductor device, comprising: forming a film, and patterning the first conductor film and the second conductor film to form a gate electrode overlapping an end of the gate insulating film.