JP2652992B2 - Semiconductor memory integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory integrated circuit, and more particularly to a memory cell structure composed of one capacitor and one transistor.

[0002]

2. Description of the Related Art A conventional memory cell structure of this type will be described with reference to FIG. This cell structure is BSE
Buried Storage Electrod
e)) A so-called structure in which a groove 102 is formed in a P-type Si substrate 101 in which a low-concentration P-type epitaxial layer is formed on a high-concentration P-type substrate, and a capacitive insulating film is formed on an inner wall thereof. A charge storage electrode 104 is buried via 103. The charge storage electrode 104 is separated from the first high-concentration N-type diffusion layer 106 formed in advance on the surface of the semiconductor substrate by another wiring layer (hereinafter referred to as lead wiring) 105 at the position of the capacitor contact hole 107. It is connected.

The first high-concentration N-type diffusion layer 106 is connected to a source / drain region 108 of a MOS transistor formed by a usual self-alignment technique. The other source / drain region 109 is connected to the bit line 110, the gate electrode 111 extends in the direction perpendicular to the plane of the drawing,
Form a word line.

In this conventional memory cell, when a voltage that turns on the transistor is applied to the gate electrode 111, the bit line 110 and the charge storage electrode 104 conduct through the access transistor, and the bit line 110 The electric charge charges or discharges the capacitance formed between the charge storage electrode 104 and the high-concentration P-type region of the P-type Si substrate 101, and holds the bit information by setting the access transistor to the selected state. .

[0005]

In this conventional memory cell structure, the connection between the lead wiring 105 and the first high-concentration N-type diffusion layer 106 is made through a capacitor contact hole 107. A superimposition margin between the patterns is required, and it is difficult to achieve miniaturization and high-density integration due to reproducibility problems in design and manufacturing.

That is, in the plan view of the conventional example shown in FIG. 4, a positive margin 120 is required for the groove 104 in order to form the capacitor contact 107. The lead wiring 107 has a margin 12 covering the capacitance contact.
1, a margin 122 for preventing the lead wiring 105 from overlapping the gate electrode 111, and a margin 1 for preventing the high-concentration N-type diffusion layer 106 from becoming smaller than the lead wiring 107.
23, a margin 124 between the gate electrode 111 and the high concentration N-type diffusion layer 106 for the access transistor to be self-aligned was required.

[0007] Further, there is a problem that the production yield is low due to the structural complexity.

[0008]

Means for Solving the Problems The present invention comprises a MOS transistor, in a semiconductor memory integrated circuit including a memory cell composed of the MOS transistors connected in series with a capacitor in a semiconductor substrate, said capacitor said
A groove dug inward from one main surface of the semiconductor substrate,
Formed on the bottom and side surfaces of the groove away from the one main surface;
A diffusion layer having a different conductivity type from the vicinity of the one main surface of the semiconductor substrate;
And a conductive film that fills the trench with a capacitor insulating film interposed therebetween.
A lead having a storage region and extending from an insulating film selectively covering one main surface of the semiconductor substrate to one main surface of the semiconductor substrate and comprising a semiconductor film connected to a charge storage region of the capacitor; A wiring, a gate insulating film provided on a portion where the semiconductor film is in contact with the semiconductor substrate, and a gate electrode provided on the gate insulating film belong to the MOS transistor.

[0009]

Next, a memory cell structure according to the present invention will be described.
This will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view showing a memory cell structure according to a first embodiment of the present invention.

An N-type well 12 and a P-type well 13 are formed on the main surface of a low-concentration P-type silicon substrate 1 from the substrate side, and the groove 2 is formed so as to reach the N-type well 12. A thick silicon oxide film 1 is formed on the upper side wall of the groove 2.
4 are formed. A charge storage electrode 4 is formed on the inner wall of the groove 2 therebelow via a capacitor insulating film 3.
Are buried up to the vicinity of the substrate surface of the groove 2. On the substrate side, a high-concentration N-type diffusion layer 17 is formed, and an N-well 1 is formed.
It is connected to 2. This charge storage electrode is connected to a lead wire 5 made of a semiconductor film selectively provided on the substrate surface. The lead wiring 5 is directly connected to the substrate at a part near the area where an access transistor is to be formed later. The lead wiring is formed by subjecting a polycrystalline silicon film deposited by an epitaxial growth technique or a CVD method to a heat treatment such as a lamp annealing method or a laser irradiation method so that a silicon substrate to be a seed crystal is exposed and an access transistor is formed at least later. Are almost single-crystallized.

The lead wiring 5 is interposed via the gate insulating film 15.
A gate electrode 11 is provided at a portion which is directly connected to the substrate and is a single crystal, and functions as an access transistor 9. The source region 8 and the drain region 9 are formed in the lead wiring 5 by a self-alignment technique, and are connected to the charge storage electrode 4 and the bit line 10, respectively.

In the present memory cell structure, the gate electrode 1
Reference numeral 1 also serves as a word line, extends in a direction perpendicular to the plane of the drawing, and is arranged in parallel. It is connected to an auxiliary word line 16 made of an aluminum material through a contact hole (not shown) provided at a constant spatial cycle to reduce a delay time. In the cell selected by the word line, the access transistor is turned on, the bit line 10 and the charge storage electrode 4 are conducted through the lead wire 5, and the N well 12 is supplied with a potential of about 1/2 VCC. As a result, the charge and discharge between the high-concentration N-type diffusion layer 17 and the charge storage electrode 4 formed below the groove are performed. When the access transistor is turned off, electric charges are retained, and the function of a one-capacitor, one-transistor DRAM is achieved. According to this structure, since the transistor is formed on the lead wiring, a capacitance contact is unnecessary in principle. Also,
Since a single crystal can be grown by using a substrate crystal as a seed crystal for the lead wiring of the transistor formation portion, the cut-off characteristics and the ON characteristics of the access transistor are not impaired.

In order to realize a groove having this structure, first, a shallow groove is dug in the P well 13 and ion implantation is performed to oxidize the silicon oxide film 14 and a high-concentration P-type diffusion layer 18. Next, the shallow groove may be further dug into a deep groove, ions may be implanted to form the capacitor insulating film 3, and the charge storage electrode 4 may be formed.

FIG. 2 is a longitudinal sectional view showing a memory cell structure according to a second embodiment of the present invention.

The difference from the first embodiment is that the access transistor has a structure in which the access transistor is buried inside the groove, and thus functions as a memory cell having an open digit configuration. A low-concentration P-type Si substrate 1 has a double well structure of an N well 12 and a P well 13. A thick silicon oxide film 14 is formed above the groove 2 formed on the surface of the silicon substrate, and functions as an element isolation region. For more complete separation, a high-concentration P-type diffusion layer 18 is formed locally on the silicon oxide film 14 on the substrate side. Thick silicon oxide film 1 above the trench where the access transistor is to be formed
4 is removed, and the lead wiring 5 is directly connected to the part.

The charge storage electrode 4 is buried in the groove, away from the entrance of the groove by an amount corresponding to burying the access transistor, and is connected to the above-mentioned lead wiring 5. The silicon substrate on the upper side wall of the groove of the lead wiring 5 is used as a seed crystal, and the gate electrode 1
1 to function as an access transistor. One of the lead wires 5 is connected to the charge storage electrode 4 as described above.
The other is connected to the bit line 10.

As described above, the MOS transistor formed on the lead wiring 5 which is partially connected to the substrate and extends on the insulating film is used as an access transistor, and the charge storage electrode 4
A capacitor is formed between the high-concentration N-type diffusion layer region 17 connected to the N-well formed on the substrate side below the trench 2, and functions as a memory cell in the same operation as in the first embodiment. I do.

The second embodiment has a structure in which the access transistor is also formed in the groove, and is suitable for further miniaturization and high-density integration.

[0020]

As described above, according to the present invention, in a dynamic RAM having a one-capacitor, one-transistor structure, an access transistor extends on an insulating film, a part of which is connected to a substrate, and a charge is stored. By adopting a structure formed on the lead wiring 1 made of a semiconductor film connected to the electrode, a capacitance contact, that is, a contact for connecting the charge storage electrode and the source region of the access transistor is not required in principle, and the DRAM is miniaturized. , Has a structure effective for high-density integration.

Further, the lead wiring of the transistor forming portion is
Since it is structurally possible to use a single crystal grown using the substrate as a seed crystal, the characteristics of the access transistor are not degraded.

Furthermore, since the structure is simplified to eliminate the need for a capacitor contact, the yield in manufacturing can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a conventional one transistor, one capacitor, and memory cell.

FIG. 4 is a plan view corresponding to FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 P-type Si substrate 2,102 Groove 3,103 Capacitive insulating film 4,104 Charge storage electrode 5,105 Lead wiring 106 N-type diffusion layer 107 Capacitive contact hole 8,108 Source region 9,109 Drain region 10,110 Bit line 11, 111 Gate electrode 12 N well 13 P well 14 Thick silicon oxide film formed above trench 15 Gate insulating film 16 Auxiliary word line 17 High-concentration N-type diffusion layer 18 High-concentration P-type diffusion layer 19, 119 High-concentration P-type diffusion layer 120 Groove-capacitance contact margin 121 Capacitance contact-lead wiring margin 122 Lead wiring-gate margin 123 Lead wiring-N-type diffusion layer margin 124 N-type diffusion layer-gate margin

Claims (3)

(57) [Claims] 1. A semiconductor memory integrated circuit in which a memory cell including a MOS transistor and a capacitor connected in series with the MOS transistor is integrated on a semiconductor substrate, wherein the capacitor is located on one main surface of the semiconductor substrate.
The groove dug inward, the bottom and side surfaces of the groove
The one main surface of the semiconductor substrate formed apart from the one main surface
A diffusion layer having a different conductivity type from the vicinity and the trench are formed with a capacitive insulating film.
Having a charge storage region made of a conductive film filled through
A lead wire that is provided from an insulating film that selectively covers one main surface of the semiconductor substrate to one main surface of the semiconductor substrate and that is connected to a charge storage region of the capacitor; A semiconductor memory integrated circuit, wherein a gate insulating film provided on a portion in contact with a semiconductor substrate and a gate electrode provided on the gate insulating film belong to the MOS transistor. 2. The semiconductor device according to claim 1, wherein the conductive film is a predetermined distance from one principal surface of the semiconductor substrate.
The trench is provided so as to be spaced apart from the trench, and the semiconductor film is located above the trench.
A side surface directly contacting the semiconductor substrate and the conductor
The gate electrode is provided so as to cover the upper end of the film, and the semiconductor
The semiconductor memory integrated circuit according to claim 1, wherein a portion above the groove provided with the film is provided via a gate insulating film . 3. A semiconductor substrate and the semiconductor film is a semiconductor memory integrated circuit according to claim 1 or 2, wherein a main component of the same element.