JPS61177775A - Transistor - Google Patents

Abstract

PURPOSE:To facilitate the formation of resistors so as to make connection of large tensile strength by a method wherein the base-emitter resistor is formed by using a connection semiconductor region, and emitter lead connection parts are provided outside the emitter region; then, leads are connected on the semiconductor. CONSTITUTION:A connection semiconductor region 15 is isolated by insulation from a base region 13 with a collector high-resistant region 12 at the part other than a joint with a resistor semiconductor region 16. They are therefore connected by resistance with the region 16 which acts as a resistance region because of being narrow. Said region 16 of P-type acts as a bias resistor or a stabilizing resistor. A region 13a is the part where bonding pads for base leads are formed. Said region 15 of P-type for emitter lead bonding and the region 13a for base lead bonding are provided at the corners on a diagonal of the planar square surface of a substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a transistor having an island-shaped, net-shaped or striped emitter region.

[Conventional technology]

For example, in power transistor chips.

Multi-emitter transistors have many small-area emitter regions formed in response to demands for improved characteristics.

The adoption of a fine pattern structure such as a mesh emitter transistor in which the ivy region st is formed in a net shape, that is, a lattice shape, and the base region is relatively formed in the form of an island, is becoming more effective.

Since the emitter region of a transistor with this type of structure is small, it is necessary to provide an emitter lead wire' (emitter bonding pad part for +- connection) so as to make ohmic contact with the emitter region. It is difficult.If you consider +- in the case of multi-emitter transistors,
If one of the emitter regions has a large area, it is necessary to provide a pumping radial portion having an Ohmink contact in this large emitter region. However, in this structure, the large-area emitter portion is less susceptible to secondary damage than other emitter regions, resulting in a transistor with a small amount of damage 11#. From such a JIIvf, in a transistor having a fine bonding layer, a structure is adopted in which a metal layer is formed on the emitter region or base region via an insulating film. There are many things.

[Zhao point that the invention is trying to solve]

However, with this structure, the tensile strength of the emitter bonding pad (strength against breakage of the pad when a lead wire is connected to the RAD and this lead wire is pulled) is ohmic in the cow conductor region. The pumping pads that came into contact with each other (℃ are smaller than the rads. Figure 8 explains the destruction of the pumping pad part.

In this Figure 8, R°C, the mountain is the silicon substrate, (21 is the Si
ng (lower layer) and an insulating layer consisting of Si, N, (upper IWI), (31 is a connecting conductor consisting of an Al layer, a Zn layer, and a Ni layer forming an emitter bonding pad, (4)
is an Ag lead wire.

(5) is solder of Pb-Sn-Ag thread. This structure is.

Connect lead wire +41 and conductor layer (
It has the advantage that the bonding strength between 31 and 31 is very high.

However, when a tensile strength test was performed on the lead wire +41, a fracture occurred at the +61 point, so-called layer cracking of the silicone, and it was found that the tensile strength sufficient to take advantage of the advantages of solder connections could not be obtained. Ta. This phenomenon is.

Connecting conductor +31 and solder (5
It is thought that the stress caused by 1 causes the silicon, which is weak in strength, to break down.

We have just described the case of connecting the lead wires with solder (5), but there are also cases where the leads are bonded using a conductive bonding material other than solder, and the leads are bonded using ultrasonic waves or heat without using a conductive bonding material. When bonding with a pressure layer, etc., the odor may also be lowered by ceramic a! This causes problems such as the inability to obtain sufficient contact force.

- 10,000, to ensure stable operation of transistors.

Or a resistor in general between emitter and base for biasing! ! 2 threads. Providing this type of resistor within a transistor chip simplifies the construction of one circuit.

Therefore, one object of the present invention is to easily form a resistor between the S temperature and the emitter in a transistor having an M-shaped, net-shaped, or striped emitter region, and to provide a resistance to failure of seven degrees. The purpose is to increase the tensile strength of the connection portion of the lead member. [Means for solving the problem] The transistor according to the present invention for achieving the above purpose t-m has a collector region of the first width tm and , a base region of a second width tm opposite to the first conductor tm adjacent to the collector region, and a base region of a second conductor tm opposite to the first conductor tm adjacent to the collector region; an emitter region of conductivity type 1 having a plurality of island-like portions, net-like portions, or stripe-like portions;
a connecting semiconductor region with an m2 conductor of 1 km connected to the connecting semiconductor region; a resistive semiconductor region with an M2 conductor tfJ provided narrowly so as to connect the base region and the connecting semiconductor region with a resistance; a wiring conductor for connecting the emitter region and the semiconductor region for connection or a semiconductor region provided within the semiconductor region for connection; It is characterized in that the upper body region is used as a common connection portion for connecting the emitter region to the outside.

[For production]

The connecting semiconductor region in the above invention is used for common connection of emitters, and also for connecting a resistor between a base and an emitter. This connecting semiconductor region serves as an emitter for a! This shape does not directly affect secondary destruction of the transistor. The emitter lead conductor for external connection is not connected to the emitter region where the transistor operates, but is connected to the 5i continuation cow body region or a portion provided on this region according to the present invention. Therefore, unlike conventional multi-emitter transistors (there is no need to connect lead members on the insulating layer)
-, which allows connection of lead members with large tensile strength. Furthermore, since this transistor uses the entire connecting semiconductor region to provide a resistance between the base and emitter, it is possible to obtain the resistance between the base and emitter without complicating the method and structure.

〔Example〕

Next, the entire outline of a multi-emitter type silicon power transistor according to an embodiment of the present invention will be explained based on FIGS. 1 to 7.

As is clear from No. 11k showing the surface of the base 111J and FIGS. 4 and 5 showing the cross section of the completed transistor, the insulating layer, conductive layer, etc. are removed from the top of the semiconductor substrate uIJ. A high-resistance collector region (121) of one conductor (1) is provided, in which a second conductor (m) is provided.
) is formed by boron diffusion, and a large number of Nm emitter regions 4 are formed in the form of islands in the base region a3 by phosphorus diffusion. Multiple emitter regions 111. The circles have the same size as a rectangular planar shape and are regularly arranged like a base.

r151 is a P-type connecting semiconductor region for forming a bonding pad portion of the emitter lead wire, and the region (
15) and the base region (1:1't) are formed by narrow width (small cross-sectional area) P-type resistor semiconductor regions, which are also formed by boron diffusion at the same time as the base diffusion.
This is because the base region (I51) and the base region (131) are insulated and separated by the collector high-resistance region α force in a region other than the region where they are connected.

Area U that acts as a resistance area due to its narrow width
− will be connected to the ℃ resistance. In addition.

The P-type resistor body region 11bl functions as a bias resistor or stabilizing resistor. The area (13a) is.

The pounding pad for the base lead is shaped like H and is the sagging part. As is clear from Figure 1.

PM connection Ifc for emitter lead bonding
The region (13a) for bonding the i+3 cow body region 115+ and the base lead is provided at the corner on the diagonal line of the surface of the planar rectangle of the substrate (III).Therefore,
In Figure 1? The pattern to be drawn is symmetrical about the diagonal corner connecting the areas α (13a).

As is clear from FIG. 2, which shows the surface of the insulating layer σ7j with the wiring board and lead wires removed, and FIGS. 4 and 5, which show the cross section of the completed transistor.

A raccoon opening (4) exposing each emitter region (141)
is provided for each emitter region mill. However, in the emitter region <14a) located on the diagonal line connecting the corners (lla) and (llb) of the substrate αυ? Then, diagonal + sr
Two openings (2OA) (20B) are provided symmetrically at the center.

Further, in order to expose the base region a3, an opening (7) is provided near the angle of each emitter region α.

(11G! Area for base lead danding (
Opening for exposing 13a), 17! I) is an opening for exposing the area a51t for emitter lead rebonding. In addition, each opening tt81[1w
(21+ is the angle (lla) (llb) t - the connecting diagonal fi
It is arranged symmetrically around the lt-center. Silicon substrate αυ
The insulating layer 1η formed on the silicon region side is
, film S io, film (silicon oxide layer) -Si,
N number i (silicon nitride film). 3i01 is a thermal oxide film with a thickness of about 0.7 μm. 57.N4 is made of C
The layer is formed using the VD method and has a thickness of a little less than 0.1 μm.

As is clear from Figure 3, which shows the chip surface excluding the lead l#1tl, and Figures 4 and 5, which show the entire cross section of the completed device, the base contact @conductor layer that acts as the base electrode, and the emitter electrode. The emitter-connecting conductor layer, which acts as a conductor layer, is removed at ℃. The base connection conductor layer has a portion (22a) in ohmic contact with the base area a4 through the opening shown in FIG. 22a)
(22b) 'x Insulating layer 117 to connect to each other)
It consists of a wiring part (22C) provided on top of the wiring part (22C). The emitter connection conductor layer has a portion (238) that makes ohmic contact with the emitter region I through the opening tAt'' shown in FIG. The base connection conductor layer consists of a portion extending on a diagonal connecting the corners (lla) and (11b), and a portion extending in a branch shape from there. It has an extending portion and is arranged symmetrically about a diagonal line.

The diagonally extending portion is disposed between the divided pair of emitter exposure openings (20a) and (20b) shown in FIG. The emitter connection conductor layer is arranged so as to be inserted between the base connection conductor layers c12.

These conductor layers ■Q3 are not cross-wired, so
A pair of openings (2UaJ (20b)) for exposing the emitter regions ji2 on the diagonal are handled by a conductor layer extending from another direction. It has a three-layer structure of Al-Zn-Ni with AI on the side.

The Al layer has a thickness FJ of 5 μm and is formed on the entire surface of the chip by photoetching using an evaporation layer wave, as shown in the figure, and the Zn layer is extremely thin, about 0.05 to 0.1 μm, and is replaced It is formed on All by plating (a method in which AI is dissolved in plating F8 solution and Zn ions in the plating solution receive electrons generated by the reaction and deposited on All as metal Zn), and the Ni layer is formed using the interspersed Kanigen method. ℃
It is formed on Zn by a conventional electroless plating method.

N: &, after Ni layer formation.

Heat treatment at about 200°C is performed. The @ of this three-layered corridor IIl is made of aluminum, which is said to be able to reduce wiring resistance.
The advantage of the electrode is that it is possible to solder the long FFr of the Ni electrode.
It has both. The Zn layer is interposed for good adhesion between the Al layer and the Ni layer ◎ [V-ff in Figure 3]
As is clear from FIG. 4, which shows the cross section of the completed transistor corresponding to the part corresponding to the line, the emitter lead wire made of Ag is attached to the bonding pad part (23b) on the P-type head area α. They are joined by soldering of Sn-Ag threads. Also.

As is clear from FIG. 5, which shows the cross section of the completed transistor corresponding to the marma line in FIG. They are joined with solder (to) of Pb-Sn-AI thread.R is also provided with a three-layer structure collector electrode (c) made of AI-Zn-Ni on the lower surface of the low-resistance collector region @. There is.

A tensile strength test was conducted on the emitter lead wire □ of the completed transistor chip shown in Figures 4 and 5.
In the conventional structure shown in the figure, silicon layer cracking would occur with a probability of about 1%.

We were able to eliminate any cracking of the silicon layer @ that is, the opening 3υ was 0.7 mm square, and the total diameter of the lead wire @ was 0.25 mm.
mm, and the appropriate electrode formation conditions S and soldering conditions were selected, and Ag with a diameter of 0.25 mm was selected.
Tensile strength of All IJ-do wire (c) 1, 0 to 1
．． When the weight was 5 kg or less, no silicon layer cracking, peeling between electrodes, solder chipping, etc. occurred, and all leads were broken. Since the base lead wire surface also has the same connection structure as the emitter lead wire, it was possible to obtain a very good connection strength.

FIG. 6 shows the equivalent circuit of the completed transistor. The resistance R of this circuit is determined by the narrow PM region αe formed between the base region 0 and the PM region u51 shown in FIG.
can get. The diode D is generated by providing the P region α in the N type collector region (12+), and is connected in antiparallel to the transistor Q. This diode D is connected to protect the transistor Q. Since it is the same as the previous one, it does not affect the transistor operation.

This *m example transistor has the following advantages.

(al) Since a P-type connection semiconductor region α51 was provided for bonding and the emitter lead wire @ was connected manually to the conductor layer (23b) above this, the connection strength of the lead wire (c) was increased by the ultrasonic wave. This is significantly less compared to the case of bonding, etc., and the generation of silicon layer cracking is prevented.Therefore, it is possible to provide a highly reliable power transistor that can be used as an automotive electrical component.

(bl) Since it is not necessary to provide a region for connecting the lead member T to the emitter region α, the distribution of the emitter region I can be made uniform, and a transistor that is resistant to secondary damage can be obtained.

(By connecting the connecting conductor area a of cJPm and the base area α4 with the narrow P-type head σ-, the base
If a resistor is connected between the emitters, the resistance becomes low, so a bias resistor or stabilizing resistor can be easily obtained.

(di for the emitter region I on the diagonal plane, ℃ is il
e Two openings (2oa) in edge layer α71 (20b) t
- 0 double opening (20a) (2
It becomes possible to provide a base connection conductor layer between 0b) and 0b). As a result.

When the pattern is symmetrical about a diagonal line, the emitter region I can be placed on the diagonal line, and the chip area can be used effectively. Also.

As shown in Figure 3, the base and emitter connecting conductor layers can be arranged symmetrically about the diagonal line without cross-distribution.If they are formed symmetrically about the diagonal line, the current and heat distribution will be improved. It becomes possible to achieve uniformity, and it is possible to provide a transistor with high secondary breakdown resistance.

The present invention is not limited to the embodiments described above.

It is possible to transform. For example, as shown in Figure 7,
It is also good to form an N''fJ region □□□ by phosphorus diffusion in the P-type region 115+ at the same time as the emitter region (141), and to provide a bonding pad portion (23b) on the temple. is the base area and does not function.

No problems arise. ! Ta. The present invention is not limited to *- transistors, but can also be applied to composite elements such as Darlington transistors and integrated circuit transistors.

In particular, since Darlington transistors usually have a resistor T-connection between the emitter and base, the transistor of the present invention is suitable as an output stage transistor of the Darlington transistor.

〔Effect of the invention〕

As is clear from the above, according to the present invention, the base-emitter resistance t? Since the conductor area for connection is used to form the resistor at ℃, it is easy to form the resistor. Furthermore, since the emitter lead connection portion is provided outside the emitter region, there is no reduction in secondary blind resistance caused by the lead connection. Furthermore, since the leads are connected on the semiconductor without making any lead connections on the insulating layer, a connection with high tensile strength can be achieved.

[Brief explanation of drawings]

1 (2) is a plan view showing the surface of a semiconductor substrate of a multi-emitter transistor according to an embodiment of the present invention. Figure 2 is a plan view showing the surface of the transistor chip excluding lead wires and wiring conductor gold. Figure 3 is a plan view showing the surface of the transistor chip excluding beams and conductors. 5 is a sectional view showing a portion corresponding to the bar IV line of the completed transistor, FIG. 5 is a sectional view showing a portion corresponding to the mark V@ of FIG. 3 of the completed transistor, and FIG. The seventh factor is a cross-sectional view showing a transistor of a modified example, and the eighth factor is a cross-sectional view showing a conventional lead lead-out portion. aυ...Silicon base, a'a...Frefter region, (131...Base region, (13a)...
Base lead connection area, a... Emitter area, α... Semiconductor area for connection, α (to)... Semiconductor area for resistance, αη... Insulating layer, α8C19CXJ (20a
) (2ob) (Jll...opening, of...base connection conductor layer, (231...emitter connection conductor layer, @...
Emitter lead wire, @...base lead wire. Agent Nori Takano Figure 1 G Figure 2 Figure 5 ■ Eyelid droplet

Claims (2)

[Claims] (1) a collector region of a first conductivity type; a base region of a second conductivity type opposite to the first conductivity type adjacent to the collector region; and on a side of the base region opposite to the collector region; an emitter region of a first conductivity type that is arranged adjacent to each other and has a plurality of island-like parts, net-like parts, or striped parts; and a second conductivity-type emitter region that is arranged adjacent to the collector region. a semiconductor region; a second conductivity type resistor semiconductor region narrowly provided so as to connect the base region and the connection semiconductor region with resistance; and the emitter region and the connection semiconductor region; a wiring conductor for connecting the semiconductor region provided in the connection semiconductor region, and a wiring conductor for connecting the connection semiconductor region or the semiconductor region provided in the connection semiconductor region to the outside of the emitter region. A transistor characterized in that it is a common connection part for connecting to. (2) The transistor according to claim 1, wherein the conductor is formed by laminating an Al layer, a Zn layer, and a Ni layer in this order.