JPH0770539B2 - Transistor - Google Patents
TransistorInfo
- Publication number
- JPH0770539B2 JPH0770539B2 JP60019018A JP1901885A JPH0770539B2 JP H0770539 B2 JPH0770539 B2 JP H0770539B2 JP 60019018 A JP60019018 A JP 60019018A JP 1901885 A JP1901885 A JP 1901885A JP H0770539 B2 JPH0770539 B2 JP H0770539B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- base
- conductor layer
- diagonal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 49
- 239000004020 conductor Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910020836 Sn-Ag Inorganic materials 0.000 description 3
- 229910020988 Sn—Ag Inorganic materials 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000009864 tensile test Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910007567 Zn-Ni Inorganic materials 0.000 description 1
- 229910007614 Zn—Ni Inorganic materials 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
- H01L2224/85801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、島状又は網状又はストライプ状のエミツタ領
域を有するトランジスタに関する。TECHNICAL FIELD The present invention relates to a transistor having an island-shaped, net-shaped, or stripe-shaped emitter region.
例えば、パワートランジスタチツプにおいては、特性向
上の要求に応えるべく、多数の小面積エミツタ領域を形
成したマルチエミツタトランジスタ、エミツタ領域を網
状即ち格子状に形成して相対的にベース領域が島状に形
成されるメツシユエミツタトランジスタといつた微細パ
ターン構造の採用が増加している。For example, in a power transistor chip, in order to meet the demand for improved characteristics, a multi-emitter transistor in which a large number of small area emitter regions are formed, and the emitter regions are formed in a mesh or grid shape so that the base region is relatively island-shaped. The use of formed mesh transistors and fine pattern structures is increasing.
この種の構造のトランジスタにおいては、エミツタ領域
が小面積であるので、エミツタリード線を接続するため
のエミツタボンデイングパツド部分を、エミツタ領域に
オーミツク接触するように設けることが困難である。マ
ルチエミツタトランジスタの場合を考えると、エミツタ
領域の１つを大面積とすれば、この大面積エミツタ領域
にオーミツク接触させたボンデイングパツド部分を設け
ることができる。しかし、この構造では、大面積エミツ
タ部分が他のエミツタ領域に比べて二次破壊し易くな
り、破壊耐量の小さいトランジスタとなつてしまう。こ
のような事情から、微細パターンを有するトランジスタ
においては、エミツタ領域またはベース領域の上に絶縁
膜を介して形成した電極金属をエミツタボンデイングパ
ツドとする構造を採用することが多い。In the transistor of this kind of structure, since the emission region has a small area, it is difficult to provide the emission bonding pad portion for connecting the emission lead wire so as to make ohmic contact with the emission region. Considering the case of a multi-emitter transistor, if one of the emitter regions has a large area, a bonding pad portion in ohmic contact with this large-area emitter region can be provided. However, in this structure, the large area emitter is more likely to undergo secondary breakdown than other emitter regions, resulting in a transistor having a small breakdown resistance. Under such circumstances, a transistor having a fine pattern often employs a structure in which an electrode metal formed on an emitter region or a base region via an insulating film serves as an emitter bonding pad.
しかし、この構造では、エミツタボンデイングパツド部
分の抗張力（エミツタボンデイングパツドにリード線を
接続し、このリード線を引張つたときのパツド部分の破
壊に対する強さ）が、半導体領域にオーミツク接触した
ボンデイングパツドに比べて小さくなる。第８図はボン
デイングパツド部分の破壊を説明するものである。この
第８図において、（１）はシリコン基板、（２）はSiO2
（下層）とSi3N4（上層）とから成る絶縁層、（３）は
エミツタボンデイングパツドを形成するAl層とZn層とNi
層とから成る接続導体、（４）はAg製のリード線、
（５）はPb−Sn−Ag糸の半田である。この構造は、半田
（５）で接続するためにリード線（４）と導体層（３）
の間の接着強度が非常に大きいという長所を有する。と
ころが、リード線（４）の引張り試験を行うと、破線
（６）の部分での破断いわゆるシリコンの層割れが発生
し、半田接続の長所を生かし切るだけの引張り強度が得
られないことが分つた。この現象は、絶縁層（２）によ
りストレスがかかつているシリコン基板（１）の表面部
分に、接続導体（３）と半田（５）によるストレスが加
わり、強度的に弱いシリコンが破壊に至るものと考えら
れる。However, in this structure, the tensile strength of the emission bonding pad part (the strength against the destruction of the pad part when the lead wire is connected to the emission bonding pad and the lead wire is pulled) causes ohmic contact with the semiconductor region. It is smaller than the bonded pad. FIG. 8 illustrates the destruction of the bonding pad portion. In FIG. 8, (1) is a silicon substrate and (2) is SiO 2.
Insulating layer consisting of (lower layer) and Si 3 N 4 (upper layer), (3) is Al layer, Zn layer and Ni which form emission bonding pad.
Connecting conductor consisting of layers, (4) is a lead wire made of Ag,
(5) is a solder of Pb-Sn-Ag thread. This structure includes a lead wire (4) and a conductor layer (3) for connecting with solder (5).
It has the advantage that the adhesive strength between the two is very large. However, when the tensile test of the lead wire (4) is performed, it is found that the so-called silicon layer cracking occurs at the broken line (6), and it is not possible to obtain the tensile strength sufficient to make full use of the advantage of solder connection. Ivy. This phenomenon is caused by the stress due to the connecting conductor (3) and the solder (5) being applied to the surface portion of the silicon substrate (1) which is stressed by the insulating layer (2), resulting in the destruction of silicon having weak strength. it is conceivable that.
今、半田（５）でリード線を接続する場合について述べ
たが、半田以外の導電性接合材を使用してリードをボン
デイングする場合、及び導電性接合材を使用しないでリ
ードを超音波又は熱圧着等でボンデイングする場合にお
いても、同様な問題及び十分な接着力が得られないとい
う問題が生じる。Now, the case of connecting the lead wires with the solder (5) has been described. However, when the leads are bonded using a conductive bonding material other than solder, and when the conductive bonding material is not used, the leads are subjected to ultrasonic waves or heat. Even in the case of bonding by pressure bonding or the like, the same problem and a problem that sufficient adhesive force cannot be obtained occur.
一方、トランジスタを安定的に動作させるため、あるい
はバイアスのために、エミツタ・ベース間に一般に抵抗
を接続する。この種の抵抗をトランジスタチツプ内に設
けると、回路構成が簡単になる。On the other hand, a resistor is generally connected between the emitter and the base for stable operation of the transistor or for biasing. Providing this type of resistor in the transistor chip simplifies the circuit configuration.
抵抗をトランジスタチップ内に設ける場合に、半導体基
板の大型化を招かないようにこの主面を有効に利用する
ことが要求される。また、容易に形成することができ且
つ温度依存性の小さい抵抗が要求される。When the resistor is provided in the transistor chip, it is required to effectively use this main surface so as not to increase the size of the semiconductor substrate. Further, a resistor that can be easily formed and has a small temperature dependence is required.
また、外部導体に対する接続の関係上、ベースボンディ
ングパッド部及びエミッタボンディングパッド部を半導
体チップの四角形の主面の対向する２つの角部に配置し
なければならないことがある。この様な場合であっても
半導体チップの主面の有効利用が望まれる。In addition, due to the connection with the external conductor, the base bonding pad portion and the emitter bonding pad portion may have to be arranged at two opposite corner portions of the rectangular main surface of the semiconductor chip. Even in such a case, effective use of the main surface of the semiconductor chip is desired.
そこで、本発明の目的は、半導体基板の主面を有効に利
用することができ、且つベース・エミッタ間の抵抗を容
易に形成することができ、且つエミッタリード部材のエ
ミッタボンディングパッド部に対する安定的な接続が可
能であるマルチエミッタトランジスタを提供することに
ある。Therefore, an object of the present invention is to effectively use the main surface of the semiconductor substrate, to easily form a resistance between the base and the emitter, and to stabilize the emitter lead member with respect to the emitter bonding pad portion. It is to provide a multi-emitter transistor that can be connected in various ways.
［問題点を解決するための手段］ 上記目的を達成するための本発明は、実施例を示す図面
の符号を参照して説明すると、正方形の主面を有してい
る半導体基板（11）と、前記半導体基板（11）の主面上
に設けられた絶縁層（17）と、ベース接続導体層（22
a）と、エミッタ接続導体層（23a）と、ベースボンディ
ングパッド部（22b）と、エミッタボンディングパッド
部（23b）とを備えたマルチエミッタトランジスタにお
いて、前記半導体基板（11）が、この半導体基板（11）
の主面に一部が露出するように配置されているコレクタ
領域（12）と、不純物拡散によって前記コレクタ領域
（12）に隣接するように形成され且つ前記一方の主面に
露出する部分を有しているベース領域（13）と、前記ベ
ース領域（13）に前記コレクタ領域とは反対側において
隣接し且つ前記主面に露出するように不純物拡散によっ
て島状に形成された多数の島状エミッタ領域（14）と、
前記コレクタ領域（12）に隣接するように不純物拡散に
よって形成され且つ前記主面に露出するように配置され
且つ前記ベース領域（13）と同一の導電型を有している
接続用半導体領域（15）と、前記ベース領域（13）と前
記接続用半導体領域（15）との間を橋渡しするように不
純物拡散によって形成され且つ前記コレクタ領域（12）
に隣接していると共に前記主面に露出しており且つ前記
ベース領域（13）と前記接続用半導体領域（15）との間
を抵抗接続するように平面的に見て前記接続用半導体領
域（15）よりも幅狭に設けられ且つ前記ベース領域（1
3）と同一の導電型を有している抵抗用半導体領域（1
6）とを備えており、前記ベース接続導体層（22a）は前
記絶縁層（17）に形成された多数の第１の開口（18）を
介して前記ベース領域（13）に接続され且つ前記絶縁層
（17）の上に延在しており、前記エミッタ接続導体層
（23a）は前記絶縁層（17）に形成された多数の第２の
開口（20）を介して前記エミッタ領域（14）に接続され
且つ前記絶縁層（17）の上に延在しており、前記ベース
ボンディングパッド部（22b）は前記ベース領域（13）
上にあり且つ前記ベース接続導体層（22a）に接続され
ており、前記エミッタボンディングパッド部（23b）は
前記接続用半導体領域（15）又はこの接続用半導体領域
（15）内に設けられた別の半導体領域（29）の上に設け
られ且つ前記エミッタ接続導体層（23a）に接続されて
おり、前記エミッタボンディングパッド部（23b）は前
記正方形の主面の１つの仮想対角線の一方の端の領域上
に配置され、前記ベースボンディングパッド部（22b）
は前記仮想対角線の他方の端の領域上に配置され、前記
仮想対角線を中心に前記多数の島状エミッタ領域（1
4）、前記ベース領域（13）、前記抵抗用半導体領域（1
6）、前記ベース接続導体層（22a）及びエミッタ接続導
体層（23a）が対称に配置され、前記抵抗用半導体領域
（16）は前記仮想対角線上に配置され、前記ベース接続
導体層（22a）は前記仮想対角線を通り且つ前記仮想対
角線上に配置された前記島状エミッタ領域を平面的に見
て横切るように配置された対角線部分と、この対角線部
分から枝状に分岐した複数の枝状分岐部分とを有してお
り、前記エミッタ接続導体層（23a）は前記ベース接続
導体層（22a）の枝状分岐部分の相互間に入り込むよう
に配置されていることを特徴とするマルチエミッタトラ
ンジスタに係わるものである。[Means for Solving the Problems] The present invention for achieving the above-mentioned object will be described with reference to the reference numerals of the drawings showing the embodiments, and a semiconductor substrate (11) having a square main surface and An insulating layer (17) provided on the main surface of the semiconductor substrate (11) and a base connecting conductor layer (22
a), an emitter connecting conductor layer (23a), a base bonding pad portion (22b), and an emitter bonding pad portion (23b), the semiconductor substrate (11) is the semiconductor substrate (11). 11)
Has a collector region (12) which is arranged so as to be partially exposed on the main surface and a part which is formed adjacent to the collector region (12) by impurity diffusion and is exposed on the one main surface. And a plurality of island-shaped emitters formed adjacent to the base region (13) on the opposite side of the collector region from the collector region and formed in an island shape by impurity diffusion so as to be exposed on the main surface. Area (14),
A connecting semiconductor region (15) formed adjacent to the collector region (12) by impurity diffusion and arranged to be exposed on the main surface and having the same conductivity type as the base region (13). ) And the collector region (12) formed by impurity diffusion so as to bridge between the base region (13) and the connecting semiconductor region (15).
Adjacent to and exposed to the main surface, and the connection semiconductor region (when viewed in plan so as to make a resistance connection between the base region (13) and the connection semiconductor region (15) ( 15) narrower than the base region (1)
Resistor semiconductor region (1) having the same conductivity type as 3)
6), the base connecting conductor layer (22a) is connected to the base region (13) through a large number of first openings (18) formed in the insulating layer (17), and The emitter connecting conductor layer (23a) extends on the insulating layer (17), and the emitter region (14) is formed through a large number of second openings (20) formed in the insulating layer (17). ) And extends over the insulating layer (17), the base bonding pad portion (22b) is provided in the base region (13).
The emitter bonding pad portion (23b), which is above and is connected to the base connecting conductor layer (22a), is provided on the connecting semiconductor region (15) or on the connecting semiconductor region (15). Is provided on the semiconductor region (29) and is connected to the emitter connecting conductor layer (23a), and the emitter bonding pad portion (23b) is at one end of one virtual diagonal line of the main surface of the square. The base bonding pad portion (22b) is disposed on the area.
Is arranged on the other end region of the virtual diagonal line, and the island-shaped emitter regions (1
4), the base region (13), the resistor semiconductor region (1
6), the base connecting conductor layer (22a) and the emitter connecting conductor layer (23a) are arranged symmetrically, the resistance semiconductor region (16) is arranged on the virtual diagonal line, and the base connecting conductor layer (22a) Is a diagonal line portion that is arranged so as to pass through the virtual diagonal line and cross the island-shaped emitter region that is arranged on the virtual diagonal line when seen in a plan view, and a plurality of branch-like branches branched from this diagonal line portion. A multi-emitter transistor characterized in that the emitter-connecting conductor layer (23a) is arranged so as to enter between the branch-like branched portions of the base-connecting conductor layer (22a). It is related.
［発明の作用及び効果］ （イ）半導体基板（11）の正方形の主面の１つの仮想対
角線を中心に多数の島状エミッタ領域（14）、抵抗用半
導体領域（16）及びベース領域（13）が対称に配置され
且つ抵抗用半導体領域（16）が仮想対角線上に配置され
ているので、半導体基板の主面が有効に利用され、且つ
仮想対角線の一方の側と他方の側の熱バランスが良くな
り、熱の集中に起因するトランジスタの破壊を抑制する
ことができる。[Operations and Effects of the Invention] (a) A large number of island-shaped emitter regions (14), resistor semiconductor regions (16) and base regions (13) centered on one virtual diagonal line of the main surface of the square of the semiconductor substrate (11). ) Are arranged symmetrically and the resistance semiconductor regions (16) are arranged on a virtual diagonal line, so that the main surface of the semiconductor substrate is effectively used and the heat balance between one side and the other side of the virtual diagonal line is effective. As a result, the transistor breakdown due to heat concentration can be suppressed.
（ロ）ベース接続導体層（22a）及びエミッタ接続導体
層（23a）が仮想対角線を中心に対称に配置されている
ので、仮想対角線の一方の側と他方の側の熱バランスが
良くなり、熱の集中に起因するトランジスタの破壊を抑
制することができる。(B) Since the base connecting conductor layer (22a) and the emitter connecting conductor layer (23a) are symmetrically arranged about the virtual diagonal line, the heat balance between one side and the other side of the virtual diagonal line is improved. It is possible to suppress the breakdown of the transistor due to the concentration of.
（ハ）抵抗用半導体領域（16）は半導体基板（11）の表
面に露出するように拡散で形成されているので、不純物
濃度を比較的高くすることができ、抵抗の温度依存性を
小さくすることができる。また、ベース・エミッタ間の
抵抗を容易に得ることができる。(C) Since the resistance semiconductor region (16) is formed by diffusion so as to be exposed on the surface of the semiconductor substrate (11), the impurity concentration can be made relatively high and the temperature dependence of the resistance can be reduced. be able to. Further, the resistance between the base and the emitter can be easily obtained.
［実施例］ 次に、第１図〜第７図に基づいて本発明の実施例に係わ
るマルチエミツタ型シリコンパワートランジスタを説明
する。[Embodiment] Next, a multi-emitter type silicon power transistor according to an embodiment of the present invention will be described with reference to FIGS.
半導体基板（11）の上から絶縁層、導体層等を取り除い
て、基体（11）の表面を示す第１図、及び完成したトラ
ンジスタの断面を示す第４図及び第５図から明らかな如
く、Ｎ型（第１の導電型）の高抵抗のコレクタ領域（1
2）が設けられ、この中にＰ型（第２の導電型）のベー
ス領域（13）が硼素拡散によつて形成され、更にベース
領域（13）の中に多数のN+型エミツタ領域（14）が燐拡
散によつて島状に形成されている。多数のエミツタ領域
（14）は、平面形状四角形の同じ大きさを有して碁盤状
に規則正しく配置されている。As shown in FIG. 1 showing the surface of the base body (11) by removing the insulating layer, the conductor layer and the like from the top of the semiconductor substrate (11) and FIGS. 4 and 5 showing the cross section of the completed transistor, N-type (first conductivity type) high resistance collector region (1
2) is provided in which a P-type (second conductivity type) base region (13) is formed by boron diffusion, and a large number of N + -type emitter regions () are formed in the base region (13). 14) is formed in an island shape by phosphorus diffusion. A large number of emitter regions (14) have the same size of a square quadrangle and are regularly arranged in a checkerboard pattern.
（15）はエミツタリード線のボンデイングパツド部分を
形成するためのＰ型の接続用半導体領域、（16）は領域
（15）とベース領域（13）を連結する幅狭の（小断面積
の）Ｐ型の抵抗用半導体領域であり、いずれもベース拡
散と同時に硼素拡散によつて形成されている。領域（1
5）とベース領域（13）は、領域（16）で連結されてい
る部分以外の所においてはコレクタ高抵抗領域（12）に
よつて絶縁分離されることになるため、幅狭であること
によつて抵抗領域として作用する領域（16）によつて抵
抗接続されることになる。なお、Ｐ型の抵抗用半導体領
域（16）は、バイアス抵抗あるいは安定化抵抗として作
用する。領域（13a）は、ベースリード線のためのボン
デイングパツドが形成される部分である。第１図から明
らかな如く、エミツタリードのボンデイングのためのＰ
型の接続用半導体領域（15）とベースリードのボンデイ
ングのための領域（13a）とは基板（11）の平面四角形
の表面の対角線上の角に設けられている。従つて、第１
図におけるパターンは領域（15）（13a）を結ぶ対角線
を中心に対称である。(15) is a P-type connecting semiconductor region for forming a bonding pad portion of the emitter lead wire, and (16) is a narrow (small cross-sectional area) connecting the region (15) and the base region (13). This is a P-type resistance semiconductor region, and both are formed by boron diffusion simultaneously with base diffusion. Area (1
5) and the base region (13) are narrow because they are insulated and separated by the collector high resistance region (12) except the part connected by the region (16). Therefore, the region (16) acting as a resistance region is resistively connected. The P type resistor semiconductor region (16) acts as a bias resistor or a stabilizing resistor. The area (13a) is a portion where a bonding pad for the base lead wire is formed. As is clear from FIG. 1, P for bonding the emitter lead
The semiconductor region (15) for connecting the mold and the region (13a) for bonding the base lead are provided at diagonal corners of the surface of the substrate (11) in the form of a square plane. Therefore, the first
The pattern in the figure is symmetrical about the diagonal line connecting the regions (15) and (13a).
配線導体及びリード線を取り除いて絶縁層（17）の表面
を示す第２図、及び完成したトランジスタの断面を示す
第４図及び第５図から明らかな如く、各エミツタ領域
（14）を露出させるための開口（20）が各エミツタ領域
（14）毎に設けられている。但し、基体（11）の角（11
a）と（11b）とを結ぶ対角線上に位置するエミツタ領域
（14a）においては、対角線を中心に対称に２つの開口
（20a）（20b）が設けられている。また、ベース領域
（13）を露出させるために、各エミツタ領域（14）の角
の近傍に開口（20）が設けられている。（19）はベース
リードのボンデイングのための領域（13a）を露出させ
るための開口、（21）はエミツタリードのボンデイング
のための領域（15）を露出させるための開口である。な
お、各開口（18）（19）（20）（21）は、角（11a）（1
1b）を結ぶ対角線を中心に対称に配置されている。シリ
コン基体（11）上に形成された絶縁層（17）は、シリコ
ン領域側をSiO2膜とするSiO2膜（シリコン酸化膜）−Si
3N4膜（シリコン窒化膜）とから成る。SiO2膜は熱酸化
膜で、厚さ約0.7μｍである。Si3N4膜はCVD法により付
着形成したもので、厚さ0.1μｍ弱である。As shown in FIG. 2 showing the surface of the insulating layer (17) by removing the wiring conductors and lead wires, and in FIGS. 4 and 5 showing the cross section of the completed transistor, each emitter region (14) is exposed. An opening (20) is provided for each emitter area (14). However, the corner (11
In the emitter region (14a) located on the diagonal line connecting a) and (11b), two openings (20a) (20b) are provided symmetrically with respect to the diagonal line. Further, in order to expose the base region (13), an opening (20) is provided near the corner of each emitter region (14). (19) is an opening for exposing a region (13a) for bonding the base lead, and (21) is an opening for exposing a region (15) for bonding the emitter lead. In addition, each opening (18) (19) (20) (21) has a corner (11a) (1
They are arranged symmetrically around the diagonal line connecting 1b). The insulating layer (17) formed on the silicon substrate (11) is a SiO 2 film (silicon oxide film) -Si having a SiO 2 film on the silicon region side.
3 N 4 film (silicon nitride film). The SiO 2 film is a thermal oxide film and has a thickness of about 0.7 μm. The Si 3 N 4 film is deposited by the CVD method and has a thickness of less than 0.1 μm.
リード線を取り除いてチツプ表面を示す第３図及び完成
した素子の断面を示す第４図及び第５図から明らかな如
く、ベース電極として働くベース接続導体層（22）と、
エミツタ電極として働くエミツタ接続導体層（23）とが
設けられている。ベース接続導体層（22）は、第２図に
示す開口（18）を通してベース領域（13）にオーミツク
接触する部分（22a）と、領域（13a）にオーミツク接触
するボンデイングパツド部分（22b）と、部分（22a）
（22b）を相互に接続するために絶縁層（17）の上に設
けられた配線部分（22c）とから成る。エミツタ接続導
体層（23）は、第２図の開口（20）を通してエミツタ領
域（14）にオーミツク接触する部分（23a）と、領域（1
5）にオーミツク接触する部分（23b）と、これ等の相互
間を接続するために絶縁層（17）の上に設けられた配線
部分（23c）とから成る。ベース接続導体層（22）は、
角（11a）（11b）を結ぶ対角線上を延びる部分とここか
ら枝状に延びる部分とを有し、対角線を中心に対称に配
置され、対角線上を延びる部分は第２図に示す分割され
た次のエミツタ露出用開口（20a）（20b）の間に配置さ
れている。エミツタ接続導体層（23）は、ベース接続導
体層（22）の間に入り込むように配置されている。これ
等の導体層（23）（23）はクロス配線されていないの
で、対角線上のエミツタ領域を露出させるための対の開
口（20a）（20b）は別の方向から延びてきた導体層によ
つて覆われている。上述のベース及びエミツタ接続導体
層（22）（23）は、シリコン領域側をAlとするAl−Zn−
Niの三層構造とされている。Al層は、厚さ約５μｍでチ
ツプ上の全面に真空蒸着後にフオトエツチングによつて
図のようなパターンに形成され、Zn層は約0.05〜0.1μ
ｍと極く薄いもので、置換メツキ（メツキ溶液にAlが溶
解し、そのときの反応で生じた電子をメツキ溶液中のZn
イオンがもらつて金属ZnとしてAl上に析出する方法）に
よつてAl上に形成され、Ni層は酸性カニゼン法として公
知の無電解メツキ法によりZn上に形成されている。な
お、Ni層形成後に、200℃程度の熱処理が行われてい
る。この三層構造の導体層（22）（23）は、配線抵抗を
小さくできるというAl電極の利点と半田付け可能という
Ni電極の長所を合わせ持つものである。Zn層はAl層とNi
層の良好な接着のために介在させている。As is apparent from FIG. 3 showing the chip surface by removing the lead wires and FIGS. 4 and 5 showing the cross section of the completed device, a base connecting conductor layer (22) serving as a base electrode,
An emitter connection conductor layer (23) serving as an emitter electrode is provided. The base connecting conductor layer (22) has a portion (22a) which makes ohmic contact with the base region (13) through the opening (18) shown in FIG. 2 and a bonding pad portion (22b) which makes ohmic contact with the region (13a). , Part (22a)
And a wiring portion (22c) provided on the insulating layer (17) for connecting (22b) to each other. The emitter connecting conductor layer (23) has a portion (23a) which makes ohmic contact with the emitter region (14) through the opening (20) in FIG.
It comprises a portion (23b) which makes ohmic contact with 5) and a wiring portion (23c) provided on the insulating layer (17) for connecting these portions to each other. The base connecting conductor layer (22) is
It has a portion extending on a diagonal line connecting the corners (11a) and (11b) and a portion extending in a branch shape from here, and is symmetrically arranged about the diagonal line. The portion extending on the diagonal line is divided as shown in FIG. It is arranged between the openings (20a) and (20b) for exposing the next emitter. The emitter connecting conductor layer (23) is arranged so as to enter between the base connecting conductor layers (22). Since these conductor layers (23) (23) are not cross-wired, the pair of openings (20a) (20b) for exposing the emitter area on the diagonal line are formed by the conductor layers extending from another direction. It is covered. The above-mentioned base and emitter connecting conductor layers (22, 23) are made of Al-Zn- with Al on the silicon region side.
It has a three-layer structure of Ni. The Al layer has a thickness of about 5 μm and is formed on the entire surface of the chip by vacuum etching in a pattern as shown in the figure after vacuum deposition, and the Zn layer has a thickness of about 0.05 to 0.1 μm.
It is very thin as m. It is a substitution metal (Al dissolved in the metal plating solution, and the electrons generated by the reaction at that time are Zn
Ion is formed on Al by a method of receiving ions and depositing as metal Zn on Al), and a Ni layer is formed on Zn by an electroless plating method known as an acidic Kanigen method. Note that heat treatment at about 200 ° C. is performed after forming the Ni layer. The conductor layer (22) (23) of this three-layer structure has the advantage that the wiring resistance can be reduced and that it can be soldered.
It has the advantages of Ni electrodes. Zn layer is Al layer and Ni layer
It is interposed for good adhesion of the layers.
第３図のIV−IV線に相当する部分に対応する完成後のト
ランジスタの断面を示す第４図から明らかな如く、Ｐ型
領域（15）上のボンデイングパツド部分（23b）にAg製
のエミツタリード線（26）がPb−Sn−Ag系の半田（28）
によつて接合されている。また、第３図のＶ−Ｖ線に対
応する完成後のトランジスタの断面を示す第５図から明
らかな如く、領域（13a）上のボンデイングパツド部分
（22b）にはAg製のベースリード線（27）がPb−Sn−Ag
系の半田（28）で接合されている。なお、低抵抗のコレ
クタ領域（24）の下面にはAl−Zn−Niから成る三層構造
のコレクタ電極（25）が設けられている。As is clear from FIG. 4 which shows the cross section of the completed transistor corresponding to the portion corresponding to line IV-IV in FIG. 3, as shown in FIG. 4, Ag is formed in the bonding pad portion (23b) on the P-type region (15). Emitter lead wire (26) is Pb-Sn-Ag based solder (28)
Are joined together. Also, as is clear from FIG. 5 which shows a cross section of the completed transistor corresponding to line VV in FIG. 3, a base lead wire made of Ag is formed in the bonding pad portion (22b) on the region (13a). (27) is Pb-Sn-Ag
It is joined with the system solder (28). A collector electrode (25) of a three-layer structure made of Al-Zn-Ni is provided on the lower surface of the low resistance collector region (24).
第４図及び第５図に示す完成したトランジスタチツプの
エミツタリード線（26）の引張り試験を行つたところ、
第８図の従来構造であればシリコンの層割れが１％程度
の確率で発生していたものを、シリコンの層割れを皆無
とすることができた。即ち、開口（21）を0.7mm角、リ
ード線（26）の直径を0.25mmとしたとき、適切な電極形
成条件および半田付け条件を選択したことと相まつて、
直径0.25mmのAg製リード線（26）の抗張力である。1.0
〜1.5kg以下においてはシリコンの層割れ、電極間剥
れ、及び半田割れ等は起こらず、全数リード線（26）切
れとなつた。一方、ベースリード線（27）に関しても、
エミツタリード線（26）と同じ接続構造としているの
で、同じく良好な接続強度を得ることができた。When a tensile test was performed on the emitter lead wire (26) of the completed transistor chip shown in FIGS. 4 and 5,
In the conventional structure shown in FIG. 8, the layer crack of silicon was generated with a probability of about 1%, but the layer crack of silicon was completely eliminated. That is, when the opening (21) is 0.7 mm square and the diameter of the lead wire (26) is 0.25 mm, appropriate electrode forming conditions and soldering conditions are selected,
This is the tensile strength of the Ag lead wire (26) with a diameter of 0.25 mm. 1.0
At ~ 1.5 kg or less, no cracks in the silicon layer, peeling between electrodes, solder cracks, etc. occurred, and all lead wires (26) were cut. On the other hand, regarding the base lead wire (27),
Since the connection structure is the same as that of the emitter lead wire (26), good connection strength can also be obtained.
第６図は完成したトランジスタの等価回路である。この
回路の抵抗Ｒは、第１図に示すベース領域（13）とＰ型
領域（15）との間に形成された幅狭のＰ型領域（16）に
よつて得られる。ダイオードＤは、Ｐ型領域（15）をＮ
型コレクタ領域（12）に設けることによつて生じるもの
であり、トランジスタＱに逆並列に接続されている。こ
のダイオードＤはトランジスタＱの保護のために接続す
るものと同一であるので、トランジスタ動作には影響し
ない。FIG. 6 is an equivalent circuit of the completed transistor. The resistance R of this circuit is obtained by the narrow P type region (16) formed between the base region (13) and the P type region (15) shown in FIG. The diode D connects the P-type region (15) to N
It is generated by providing it in the mold collector region (12) and is connected in antiparallel to the transistor Q. Since this diode D is the same as that connected for protection of the transistor Q, it does not affect the transistor operation.
この実施例のトランジスタは次の利点を有する。The transistor of this embodiment has the following advantages.
（ａ）ボンディングのためにＰ型の接続用半導体領域
（15）を設け、この上の導体層（23b）にエミツタリー
ド線（26）を半田で接続したので、リード線（26）の接
続強度が超音波ボンデイング等に比較して大幅に大にな
り、且つシリコンの層割れの発生が防止される。従つ
て、自動車電装品として使用可能な信頼性の高いパワー
トランジスタを提供することが出来る。(A) Since the P-type connecting semiconductor region (15) is provided for bonding and the emitter lead wire (26) is connected to the conductor layer (23b) on this by soldering, the connection strength of the lead wire (26) is improved. Compared with ultrasonic bonding and the like, it is significantly larger and silicon layer cracking is prevented. Therefore, it is possible to provide a highly reliable power transistor that can be used as an automobile electrical component.
（ｂ）エミツタ領域（14）にリード部材を接続するため
の領域を設けることが不要であるので、エミツタ領域
（14）の分布が均一化され、二次破壊に強いトランジス
タが得られる。(B) Since it is unnecessary to provide a region for connecting the lead member to the emitter region (14), the distribution of the emitter region (14) is made uniform and a transistor resistant to secondary breakdown can be obtained.
（ｃ）Ｐ型の接続用半導体領域（15）とベース領域（1
3）とを幅狭のＰ型領域（16）で接続することにより、
ベース・エミツタ間に抵抗を接続したこと等価となるの
で、バイアス抵抗又は安定化抵抗を容易に得ることが出
来る。(C) P-type connecting semiconductor region (15) and base region (1
By connecting to 3) with a narrow P-type region (16),
Since it is equivalent to connecting a resistor between the base and the emitter, a bias resistor or a stabilizing resistor can be easily obtained.
（ｄ）対角線上のエミツタ領域（14）に対しては、絶縁
層（17）に２つの開口（20a）（20b）を設けて電極接続
を行うので、両開口（20a）（20b）の間にベース接続導
体層（22）を設けることが可能になる。この結果、対角
線を中心に対称のパターンとする場合において、対角線
上へのエミツタ領域（14）の配置が可能になり、チツプ
面積の有効利用が可能になる。また、クロス配線を伴な
わずに、ベース及びエミツタ接続導体層（22）（23）を
第３図に示す如く対角線を中心に対称配置することが出
来る。対角線を中心に対称に形成すれば、電流及び熱分
布の均一化が可能になり、二次破壊耐量の大きいトラン
ジスタを提供することが出来る。(D) Since two openings (20a) and (20b) are provided in the insulating layer (17) for the emitter area (14) on the diagonal line, the electrodes are connected, so that the space between both openings (20a) and (20b) It is possible to provide the base connection conductor layer (22) on the. As a result, when the pattern is symmetrical with respect to the diagonal line, it is possible to dispose the emitter region (14) on the diagonal line and to effectively use the chip area. Further, the base and the emitter connecting conductor layers (22) and (23) can be symmetrically arranged about the diagonal line as shown in FIG. 3 without the cross wiring. If they are formed symmetrically with respect to the diagonal line, the current and heat distribution can be made uniform, and a transistor having a large secondary breakdown resistance can be provided.
本発明は上述の実施例に限定されるものでなく、変形が
可能なものである。例えば、第７図に示す如く、Ｐ型領
域（15）の中にエミツタ領域（14）と同時に燐拡散でN+
型領域（29）を形成し、この上にボンデイングパツド部
分（23b）を設けてもよい。この場合、領域（15）はベ
ース領域として機能しないので、何んらの問題も生じな
い。また、単一のトランジスタに限ることなく、ダーリ
ントントランジスタのような複合素子や、集積回路のト
ランジスタにも適用可能である。特に、ダーリントント
ランジスタでは、エミツタ・ベース間に抵抗を接続する
のが常とう手段になつているので、本発明のトランジス
タはダーリントントランジスタの出力段トランジスタと
して好適である。The present invention is not limited to the above embodiments, but can be modified. For example, as shown in FIG. 7, N + is formed in the P-type region (15) by phosphorus diffusion simultaneously with the emission region (14).
A mold region (29) may be formed and a bonding pad portion (23b) may be provided thereon. In this case, since the region (15) does not function as the base region, no problem occurs. Further, the invention is not limited to a single transistor, but can be applied to a composite element such as a Darlington transistor or a transistor of an integrated circuit. In particular, in the Darlington transistor, it is always used to connect a resistor between the emitter and the base. Therefore, the transistor of the present invention is suitable as the output stage transistor of the Darlington transistor.
第１図は本発明の実施例に係わるマルチエミツタトラン
ジスタの半導体基体表面を示す平面図、第２図はリード
線及び配線導体を除いてトランジスタチツプの表面を示
す平面図、第３図はリード線を除いてトランジスタチツ
プの表面を示す平面図、第４図は完成したトランジスタ
の第３図のIV−IV線に相当する部分を示す断面図、第５
図は完成したトランジスタの第３図のＶ−Ｖ線に相当す
る部分を示す断面図、第６図は完成したトランジスタの
等価回路図、第７図は変形例のトランジスタを示す断面
図、第８図は従来のリード導出部を示す断面図である。 （11）……シリコン基体、（12）……コレクタ領域、
（13）……ベース領域、（13a）……ベースリード接続
領域、（14）……エミツタ領域、（15）……接続用半導
体領域、（16）……抵抗用半導体領域、（17）……絶縁
層、（18）（19）（20）（20a）（20b）（21）……開
口、（22）……ベース接続導体層、（23）……エミツタ
接続導体層、（26）……エミツタリード線、（27）……
ベースリード線。1 is a plan view showing the surface of a semiconductor substrate of a multi-emitter transistor according to an embodiment of the present invention, FIG. 2 is a plan view showing the surface of a transistor chip excluding lead wires and wiring conductors, and FIG. 3 is a lead. FIG. 4 is a plan view showing the surface of the transistor chip except lines, FIG. 4 is a sectional view showing a portion of the completed transistor corresponding to line IV-IV in FIG.
FIG. 7 is a sectional view showing a portion of the completed transistor corresponding to the line VV in FIG. 3, FIG. 6 is an equivalent circuit diagram of the completed transistor, FIG. 7 is a sectional view showing a transistor of a modified example, and FIG. The figure is a cross-sectional view showing a conventional lead-out portion. (11) …… Silicon substrate, (12) …… Collector region,
(13) ...... Base region, (13a) ...... Base lead connection region, (14) ...... Emitter region, (15) ...... Connection semiconductor region, (16) ...... Resistor semiconductor region, (17) ... ... Insulating layer, (18) (19) (20) (20a) (20b) (21) ... Opening, (22) ... Base connecting conductor layer, (23) ... Emitter connecting conductor layer, (26) ... … Emitter lead wire, (27) ……
Base lead wire.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 福島 豊 埼玉県新座市東北２丁目36番27号 サンケ ン電気株式会社内 (56)参考文献 特開 昭57−106075（ＪＰ，Ａ) 特開 昭58−14565（ＪＰ，Ａ) 特開 昭56−36153（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yutaka Fukushima 2-36-27 Tohoku, Niiza City, Saitama Sanken Electric Co., Ltd. (56) References JP 57-106075 (JP, A) JP Sho 58-14565 (JP, A) JP-A-56-36153 (JP, A)
Claims (1)
1）と、前記半導体基板（11）の主面上に設けられた絶
縁層（17）と、ベース接続導体層（22a）と、エミッタ
接続導体層（23a）と、ベースボンディングパッド部（2
2b）と、エミッタボンディングパッド部（23b）とを備
えたマルチエミッタトランジスタにおいて、 前記半導体基板（11）が、 この半導体基板（11）の主面に一部が露出するように配
置されているコレクタ領域（12）と、 不純物拡散によって前記コレクタ領域（12）に隣接する
ように形成され且つ前記一方の主面に露出する部分を有
しているベース領域（13）と、 前記ベース領域（13）に前記コレクタ領域とは反対側に
おいて隣接し且つ前記主面に露出するように不純物拡散
によって島状に形成された多数の島状エミッタ領域（1
4）と、 前記コレクタ領域（12）に隣接するように不純物拡散に
よって形成され且つ前記主面に露出するように配置され
且つ前記ベース領域（13）と同一の導電型を有している
接続用半導体領域（15）と、 前記ベース領域（13）と前記接続用半導体領域（15）と
の間を橋渡しするように不純物拡散によって形成され且
つ前記コレクタ領域（12）に隣接していると共に前記主
面に露出しており且つ前記ベース領域（13）と前記接続
用半導体領域（15）との間を抵抗接続するように平面的
に見て前記接続用半導体領域（15）よりも幅狭に設けら
れ且つ前記ベース領域（13）と同一の導電型を有してい
る抵抗用半導体領域（16）と を備えており、 前記ベース接続導体層（22a）は前記絶縁層（17）に形
成された多数の第１の開口（18）を介して前記ベース領
域（13）に接続され且つ前記絶縁層（17）の上に延在し
ており、 前記エミッタ接続導体層（23a）は前記絶縁層（17）に
形成された多数の第２の開口（20）を介して前記エミッ
タ領域（14）に接続され且つ前記絶縁層（17）の上に延
在しており、 前記ベースボンディングパッド部（22b）は前記ベース
領域（13）上にあり且つ前記ベース接続導体層（22a）
に接続されており、 前記エミッタボンディングパッド部（23b）は前記接続
用半導体領域（15）又はこの接続用半導体領域（15）内
に設けられた別の半導体領域（29）の上に設けられ且つ
前記エミッタ接続導体層（23a）に接続されており、 前記エミッタボンディングパッド部（23b）は前記正方
形の主面の１つの仮想対角線の一方の端の領域上に配置
され、 前記ベースボンディングパッド部（22b）は前記仮想対
角線の他方の端の領域上に配置され、 前記仮想対角線を中心に前記多数の島状エミッタ領域
（14）、前記ベース領域（13）、前記抵抗用半導体領域
（16）、前記ベース接続導体層（22a）及びエミッタ接
続導体層（23a）が対称に配置され、 前記抵抗用半導体領域（16）は前記仮想対角線上に配置
され、 前記ベース接続導体層（22a）は前記仮想対角線を通り
且つ前記仮想対角線上に配置された前記島状エミッタ領
域を平面的に見て横切るように配置された対角線部分
と、この対角線部分から枝状に分岐した複数の枝状分岐
部分とを有しており、 前記エミッタ接続導体層（23a）は前記ベース接続導体
層（22a）の枝状分岐部分の相互間に入り込むように配
置されいることを特徴とするマルチエミッタトランジス
タ。1. A semiconductor substrate (1) having a square main surface.
1), an insulating layer (17) provided on the main surface of the semiconductor substrate (11), a base connecting conductor layer (22a), an emitter connecting conductor layer (23a), and a base bonding pad section (2).
2b) and an emitter bonding pad section (23b), wherein the semiconductor substrate (11) is arranged so that a part thereof is exposed on the main surface of the semiconductor substrate (11). A region (12), a base region (13) formed by the impurity diffusion so as to be adjacent to the collector region (12) and having a portion exposed to the one main surface, and the base region (13) A plurality of island-shaped emitter regions (1) formed adjacent to each other on the opposite side of the collector region by impurity diffusion and exposed to the main surface.
4) for connection, which is formed by impurity diffusion so as to be adjacent to the collector region (12) and is exposed to the main surface and has the same conductivity type as the base region (13). The semiconductor region (15) is formed by impurity diffusion so as to bridge between the base region (13) and the connection semiconductor region (15), and is adjacent to the collector region (12) and at the same time as the main region. It is exposed on the surface and is narrower than the connecting semiconductor region (15) in plan view so as to make a resistance connection between the base region (13) and the connecting semiconductor region (15). And a resistance semiconductor region (16) having the same conductivity type as that of the base region (13), and the base connection conductor layer (22a) is formed in the insulating layer (17). The base region through a number of first openings (18) A plurality of second openings (20) formed in the insulating layer (17), the emitter connecting conductor layer (23a) being connected to (13) and extending over the insulating layer (17). Is connected to the emitter region (14) via and extends over the insulating layer (17), the base bonding pad portion (22b) is on the base region (13) and the base connection Conductor layer (22a)
And the emitter bonding pad portion (23b) is provided on the connection semiconductor region (15) or another semiconductor region (29) provided in the connection semiconductor region (15) and The emitter bonding pad portion (23b) is connected to the emitter connecting conductor layer (23a), and the emitter bonding pad portion (23b) is arranged on a region of one end of one virtual diagonal line of the main surface of the square. 22b) is arranged on a region at the other end of the virtual diagonal line, and the island-shaped emitter regions (14), the base region (13), the resistance semiconductor region (16), with the virtual diagonal line as the center. The base connecting conductor layer (22a) and the emitter connecting conductor layer (23a) are symmetrically arranged, the resistance semiconductor region (16) is arranged on the virtual diagonal line, and the base connecting conductor layer (22a) is the temporary A diagonal line portion that is arranged so as to cross the island-shaped emitter region that passes through the diagonal line and that is arranged on the virtual diagonal line when viewed in plan, and a plurality of branch-shaped branched portions that branch off from the diagonal line portion. A multi-emitter transistor, wherein the emitter connecting conductor layer (23a) is arranged so as to enter between the branch-like branched portions of the base connecting conductor layer (22a).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60019018A JPH0770539B2 (en) | 1985-02-01 | 1985-02-01 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60019018A JPH0770539B2 (en) | 1985-02-01 | 1985-02-01 | Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61177775A JPS61177775A (en) | 1986-08-09 |
| JPH0770539B2 true JPH0770539B2 (en) | 1995-07-31 |
Family
ID=11987738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60019018A Expired - Fee Related JPH0770539B2 (en) | 1985-02-01 | 1985-02-01 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770539B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0712045B2 (en) * | 1988-03-02 | 1995-02-08 | 株式会社東海理化電機製作所 | Current detection element |
| GB0318146D0 (en) * | 2003-08-02 | 2003-09-03 | Zetex Plc | Bipolar transistor with a low saturation voltage |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636153A (en) * | 1979-08-31 | 1981-04-09 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| NL8005995A (en) * | 1980-11-03 | 1982-06-01 | Philips Nv | SEMICONDUCTOR DEVICE. |
| JPS5814565A (en) * | 1981-07-17 | 1983-01-27 | Nec Corp | Compound type transistor |
-
1985
- 1985-02-01 JP JP60019018A patent/JPH0770539B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61177775A (en) | 1986-08-09 |
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