JPH0438519Y2 - - Google Patents
Info
- Publication number
- JPH0438519Y2 JPH0438519Y2 JP1983030776U JP3077683U JPH0438519Y2 JP H0438519 Y2 JPH0438519 Y2 JP H0438519Y2 JP 1983030776 U JP1983030776 U JP 1983030776U JP 3077683 U JP3077683 U JP 3077683U JP H0438519 Y2 JPH0438519 Y2 JP H0438519Y2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- area
- base
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案はトランジスタ、特に高電流容量化を図
るマルチエミツタ領域を備えたトランジスタに関
する。[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a transistor, and particularly to a transistor having a multi-emitter region for achieving high current capacity.
(ロ) 従来技術
従来よりトランジスタの電流容量の増大を図る
構造としてはエミツタ領域の有効面積を増大させ
ることかが知られている。この構造として著名な
ものにマルチエミツタ構造がある。この構造では
多数の島状エミツタ領域をベース領域表面に設け
ることによりベースエミツタ接合の周辺長を増加
でき、電流容量の増加を達成できる。(b) Prior Art Conventionally, it has been known to increase the effective area of the emitter region as a structure for increasing the current capacity of a transistor. A well-known example of this structure is the multi-emitter structure. In this structure, by providing a large number of island-like emitter regions on the surface of the base region, the peripheral length of the base-emitter junction can be increased, and an increase in current capacity can be achieved.
第1図に従来のマルチエミツタ構造を示す。1
は半導体基板より成るコレクタ領域、2はベース
領域、3…3はマルチエミツタ領域であり、点線
で示す4はマルチエミツタ領域3…3にオーミツ
ク接触したエミツタ電極、5はベース領域2にオ
ーミツク接触したベース領域である。 Figure 1 shows a conventional multi-emitter structure. 1
is a collector region made of a semiconductor substrate, 2 is a base region, 3...3 are multi-emitter regions, 4, indicated by a dotted line, is an emitter electrode in ohmic contact with the multi-emitter regions 3...3, and 5 is a base region in ohmic contact with the base region 2. It is.
なお斯るマルチエミツタ構造のトランジスタは
多層配線技術を用いてボンデイングパツドを多層
化できるが、超音波ボンデイングを採る組立方法
では超音波エネルギーで層間絶縁膜の絶縁が破壊
されることが多い。従つて第1図の如くボンデイ
ングパツドを設けるパツド予定領域6をベース領
域2上に設ける必要があり、この結果マルチエミ
ツタ領域3はパツド予定領域6を除いて形成しな
くてはならず、電流容量の増大の効果が大巾に薄
れてしまう。 Note that such a transistor with a multi-emitter structure can have multiple layers of bonding pads using multilayer wiring technology, but in the assembly method that uses ultrasonic bonding, the insulation of the interlayer insulating film is often destroyed by ultrasonic energy. Therefore, as shown in FIG. 1, it is necessary to provide a pad region 6 on the base region 2 where a bonding pad is to be provided, and as a result, the multi-emitter region 3 must be formed except for the pad region 6, which reduces the current capacity. The effect of the increase will be greatly diminished.
(ハ) 考案の目的
本考案は斯る欠点に鑑みてなされ、従来の欠点
を大巾に改善した電流容量の増大を図れるマルチ
エミツタ領域を有するトランジスタを実現するも
のである。(c) Purpose of the invention The present invention has been devised in view of the above drawbacks, and is intended to realize a transistor having a multi-emitter region that can greatly improve the conventional drawbacks and increase the current capacity.
(ニ) 考案の構成
本考案によるトランジスタは第2図の如く、コ
レクタ領域11、ベース領域12および多数の島
状のマルチエミツタ領域13を備え、マルチエミ
ツタ領域13はボンデイングパツドを設けるパツ
ド予定領域16を除いてベース領域12に一定の
間隔で設けられ、パツド予定領域16上には各領
域にオーミツク接触して延在されたベースおよび
エミツタ電極15,14を設け、パツド予定領域
16間に挟まれたエミツタ領域14と他のエミツ
タ領域14との行列をずらす様に構成されてい
る。(d) Structure of the invention As shown in FIG. 2, the transistor according to the invention comprises a collector region 11, a base region 12, and a number of island-shaped multi-emitter regions 13, and the multi-emitter region 13 has a pad area 16 in which a bonding pad is to be provided. Base and emitter electrodes 15 and 14 are provided at regular intervals in the base area 12 except for the pad area 12, and base and emitter electrodes 15 and 14 are provided on the pad area 16 and extend in ohmic contact with each area, and are sandwiched between the pad area 16. The emitter region 14 is configured to shift the matrix of the other emitter regions 14.
(ホ) 実施例 本実施例を第2図に示す。(e) Examples This embodiment is shown in FIG.
本考案に依るトランジスタは、N型シリコン半
導体基板より成るコレクタ領域11と、P型のベ
ース領域12と、多数の島状のN型マルチエミツ
タ領域13とを備え、マルチエミツタ領域13は
ボンデイングパツドを形成するパツド予定領域1
6を除くベース領域12のほぼ全表面に均一に配
置されている。 The transistor according to the present invention includes a collector region 11 made of an N-type silicon semiconductor substrate, a P-type base region 12, and a number of island-shaped N-type multi-emitter regions 13, and the multi-emitter regions 13 form bonding pads. Area to be padded 1
They are uniformly arranged on almost the entire surface of the base region 12 except for the areas 6 and 6.
本考案の特徴はマルチエミツタ領域13のパタ
ーンにある。即ち対向するパツド予定領域16間
に設けたパターンと他の部分のパターンを第2図
の如く反転させている。更に詳述すれば、従来で
は第1図の如くマルチエミツタ領域13…13を
完全に行列状に一定間隔で配置していたが、本考
案ではパツド予定領域16間のパターンをずらし
て他の部分のエミツタ領域13の行間に位置させ
ている。この結果マルチエミツタ領域13…13
はパツド予定領域16で1行分増加して配置して
もパツド予定領域16の面積はあまり減少せずボ
ンデイングの支障はない。 The feature of the present invention lies in the pattern of the multi-emitter region 13. That is, the pattern provided between the opposing pad areas 16 and the pattern of other parts are reversed as shown in FIG. More specifically, in the past, the multi-emitter regions 13...13 were arranged completely in rows and columns at regular intervals as shown in FIG. It is located between the rows of the emitter region 13. As a result, multi-emitter area 13...13
Even if the padding area 16 is increased by one line in the padding area 16, the area of the padding area 16 does not decrease much and there is no problem with bonding.
そして点線で示す如く基板表面の酸化膜上に蒸
着アルミニウムより成るベース電極15およびエ
ミツタ電極14を形成する。ベース電極15はベ
ース領域12とオーミツク接触し且つパツド予定
領域16まで延在されており、エミツタ電極14
は各マルチエミツタ領域13にオーミツク接触し
てパツド予定領域16まで延在されている。また
両電極14,15は周知の櫛歯形状を採り、パツ
ド予定領域16上に拡張部分に金属細線が超音波
ボンデイングされる。 Then, as shown by dotted lines, a base electrode 15 and an emitter electrode 14 made of vapor-deposited aluminum are formed on the oxide film on the surface of the substrate. The base electrode 15 is in ohmic contact with the base region 12 and extends to the intended pad region 16, and the emitter electrode 14
is extended to the pad area 16 in ohmic contact with each multi-emitter area 13. Further, both electrodes 14 and 15 have a well-known comb shape, and thin metal wires are ultrasonically bonded to the expanded portions on the pad area 16.
具体的には1.26mm角のトランジスタペレツトに
60μ角のマルチエミツタ領域13を形成した場
合、第1図および第2図から明らかな様の従来37
個であつたのが40個に増加でき、電流容量を8〜
10%程度増加できる。 Specifically, on a 1.26mm square transistor pellet.
When a 60μ square multi-emitter region 13 is formed, the conventional 37
It was possible to increase the current capacity from 8 to 40.
It can be increased by about 10%.
(ヘ) 効果
本考案に依ればマルチエミツタ領域13のパタ
ーン改良によりエミツタ周辺長の増加を容易に図
れ、電流容量の増加を達成できる。また超音波ボ
ンデイングを行うに十分な電極パツドも確保でき
る。(f) Effects According to the present invention, by improving the pattern of the multi-emitter region 13, the emitter peripheral length can be easily increased, and the current capacity can be increased. Furthermore, sufficient electrode pads for ultrasonic bonding can be secured.
第1図は従来例を説明する上面図、第2図は本
考案を説明する上面図である。
主な図番の説明、11は半導体基板、12はベ
ース領域、13はエミツタ領域、14はエミツタ
電極、15はベース電極である。
FIG. 1 is a top view illustrating a conventional example, and FIG. 2 is a top view illustrating the present invention. Explanation of main figure numbers: 11 is a semiconductor substrate, 12 is a base region, 13 is an emitter region, 14 is an emitter electrode, and 15 is a base electrode.
Claims (1)
と、 このベース領域内に設けられ、且つ対向するバ
ツド予定領域を除いた領域に格子状に前記ベース
領域が露出するように設けられた多数島状のエミ
ツタ領域と、 前記半導体層上に設けられた絶縁膜と、 前記絶縁膜上に設けられ、前記格子状のベース
領域とオーミツクコンタクトし、前記一方のバツ
ト予定領域上から延在された櫛歯状のベース電極
と、 前記絶縁層上に設けられ、前記多数島状のエミ
ツタ領域とオーミツクコンタクトし、前記他方の
バツド予定領域上から延在された櫛歯状のエミツ
タ電極とを備えたトランジスタにおいて、 前記両バツド予定領域間に設けられた前記多数
島状のエミツタ領域を他のエミツタ領域の間にず
らすことで、このずらす方向と平行な前記バツド
の一側辺を変え、バツド面積を変えることを特徴
としたトランジスタ。[Claims for Utility Model Registration] A semiconductor layer serving as a collector region, a base region formed within this collector region, and a lattice-shaped region provided within this base region excluding the opposing bump area. a multi-island emitter region provided so that the base region is exposed; an insulating film provided on the semiconductor layer; and an emitter region provided on the insulating film and in ohmic contact with the lattice-shaped base region. , a comb-shaped base electrode extending from above the one scheduled batting area; and a comb-shaped base electrode provided on the insulating layer and in ohmic contact with the multi-island emitter area, extending from above the other scheduled batting area. In a transistor equipped with an extended comb-shaped emitter electrode, by shifting the multi-island emitter region provided between the two bump scheduled regions between the other emitter regions, the shifting direction and A transistor characterized in that one side of the parallel butts is changed to change the butt area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3077683U JPS59135651U (en) | 1983-03-02 | 1983-03-02 | transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3077683U JPS59135651U (en) | 1983-03-02 | 1983-03-02 | transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59135651U JPS59135651U (en) | 1984-09-10 |
JPH0438519Y2 true JPH0438519Y2 (en) | 1992-09-09 |
Family
ID=30161648
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3077683U Granted JPS59135651U (en) | 1983-03-02 | 1983-03-02 | transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59135651U (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5596672A (en) * | 1979-01-19 | 1980-07-23 | Nec Corp | Semiconductor device |
JPS55138273A (en) * | 1979-04-11 | 1980-10-28 | Fujitsu Ltd | Transistor |
JPS57141957A (en) * | 1981-02-27 | 1982-09-02 | Toshiba Corp | Bipolar transistor |
-
1983
- 1983-03-02 JP JP3077683U patent/JPS59135651U/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5596672A (en) * | 1979-01-19 | 1980-07-23 | Nec Corp | Semiconductor device |
JPS55138273A (en) * | 1979-04-11 | 1980-10-28 | Fujitsu Ltd | Transistor |
JPS57141957A (en) * | 1981-02-27 | 1982-09-02 | Toshiba Corp | Bipolar transistor |
Also Published As
Publication number | Publication date |
---|---|
JPS59135651U (en) | 1984-09-10 |
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