JPH08756Y2 - Transistor - Google Patents

Transistor

Info

Publication number
JPH08756Y2
JPH08756Y2 JP1989067483U JP6748389U JPH08756Y2 JP H08756 Y2 JPH08756 Y2 JP H08756Y2 JP 1989067483 U JP1989067483 U JP 1989067483U JP 6748389 U JP6748389 U JP 6748389U JP H08756 Y2 JPH08756 Y2 JP H08756Y2
Authority
JP
Japan
Prior art keywords
emitter
shaped
electrode
region
comb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1989067483U
Other languages
Japanese (ja)
Other versions
JPH038435U (en
Inventor
明彦 船越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1989067483U priority Critical patent/JPH08756Y2/en
Publication of JPH038435U publication Critical patent/JPH038435U/ja
Application granted granted Critical
Publication of JPH08756Y2 publication Critical patent/JPH08756Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 （イ） 産業上の利用分野 本考案はトランジスタ、特に高電流容量化を図った網
状エミッタ領域を有するトランジスタの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement of a transistor, particularly a transistor having a reticulated emitter region for high current capacity.

（ロ） 従来の技術 トランジスタの電流容量を増大する構造としてエミッ
タの有効面積を増大させることが知られている（実開昭
58-173252）。そこで第５図および第６図に示す如くメ
ッシュエミッタ構造のトランジスタが提案された。第５
図に於いて、（１）は半導体基板より成るコレクタ領
域、（２）は島状に点在するベース領域、（３）はメッ
シュ状のエミッタ領域、（４）はメッシュ状のエミッタ
電極、（５）は島状のベース電極で、層間絶縁膜（６）
上に櫛歯状のエミッタ電極（７）と櫛歯状ベース電極
（８）を設け、櫛歯状エミッタ電極（７）の一部がエミ
ッタボンディングパッド（９）を構成すると共にパッド
（９）表面にワイヤ（10）がボンディングされる。(B) Conventional technology It is known to increase the effective area of the emitter as a structure for increasing the current capacity of the transistor (Shokaisho)
58-173252). Therefore, a transistor having a mesh emitter structure as shown in FIGS. 5 and 6 has been proposed. Fifth
In the figure, (1) is a collector region made of a semiconductor substrate, (2) is an island-shaped base region, (3) is a mesh-shaped emitter region, (4) is a mesh-shaped emitter electrode, ( 5) is an island-shaped base electrode, which is an interlayer insulating film (6)
A comb-teeth-shaped emitter electrode (7) and a comb-teeth-shaped base electrode (8) are provided on the upper surface of the pad, and a part of the comb-teeth-shaped emitter electrode (7) constitutes an emitter bonding pad (9) and the surface of the pad (9). A wire (10) is bonded to.

斯上したメッシュエミッタ構造ではメッシュ状エミッ
タ領域（３）によりチップ面積を増大することなくエミ
ッタ面積の増大を図ることができる。この結果スイッチ
ング時間の向上および破壊強度の向上を図れる。In the above mesh emitter structure, the mesh-shaped emitter region (3) can increase the emitter area without increasing the chip area. As a result, the switching time and the breaking strength can be improved.

（ハ） 考案が解決しようとする課題 しかしながら、第５図の構造はエミッタボンディング
パッド（９）下部に１層目の島状ベース電極（５）が存
在する為、特に圧着エネルギの高いアルミワイヤの超音
波ボンディングを行うと、層間絶縁膜（６）が破壊して
層間短絡を生じる欠点があった。(C) Problems to be Solved by the Invention However, in the structure shown in FIG. 5, since the first layer of island-shaped base electrode (5) is present under the emitter bonding pad (9), the aluminum wire having a particularly high crimping energy is used. When ultrasonic bonding is performed, there is a defect that the interlayer insulating film (6) is broken and an interlayer short circuit occurs.

そこで本願考案者は第７図及び第８図に示すように、
エミッタボンディングパッド（９）下部の島状ベース電
極（５）を除去した構造を提案した。この構造はワイヤ
ボンドによるＥ−Ｂショートの危惧は少いが、エミッタ
ボンディングパッド（９）下部でピンチ構造となる為部
分的にベース抵抗ＲBが増大し、従ってベース領域の少
数キャリアの蓄積が増大してスイッチング特性、特に下
降時間tfが２〜４倍もの値に達する欠点があった。Therefore, the inventor of the present application, as shown in FIG. 7 and FIG.
A structure was proposed in which the island-shaped base electrode (5) under the emitter bonding pad (9) was removed. This structure is less likely to cause an E-B short circuit due to wire bonding, but since the pinch structure is formed below the emitter bonding pad (9), the base resistance R B is partially increased, and therefore the accumulation of minority carriers in the base region is reduced. However, there is a drawback that the switching characteristics increase, especially the fall time tf reaches a value of 2 to 4 times.

（ニ） 課題を解決するための手段 本考案は上記従来の課題に鑑みて成され、エミッタボ
ンディングパッド（18）下部の島状ベース領域（13a）
を、パッドの端まで拡張してストライプ状とすることに
より、ベース抵抗の増大とＥ−Ｂ短絡を防止し、且つ電
流容量の低下をも防止したトランジスタを提供するもの
である。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems, and the island-shaped base region (13a) below the emitter bonding pad (18).
To extend to the edge of the pad to form a stripe shape, thereby providing a transistor in which an increase in base resistance and an EB short circuit are prevented, and a decrease in current capacity is also prevented.

（ホ） 作用 本考案によれば、パッド（18）下部の島状ベース領域
（13a）がストライプ状を成すことで、ストライプの延
在方向に対してはピンチ構造を無くすことができる。(E) Operation According to the present invention, since the island-shaped base region (13a) below the pad (18) has a stripe shape, the pinch structure can be eliminated in the extending direction of the stripe.

（ヘ） 実施例 以下に本考案の一実施例を図面を参照して詳細に説明
する。(F) Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

第１図において、（11）はＰ型のベース領域、（12）
はベース領域（11）の表面に格子状に形成したＮ+型の
メッシュエミッタ領域、（13）はメンシュエミッタ領域
（12）の網目部分に縦横に点在して露出する島状ベース
領域、（14）はメッシュエミッタ領域（12）の格子形状
にあわせて格子状に延在しエミッタ領域（12）と全面で
コンタクトする第１層目電極層によるメッシュエミッタ
電極、（15）は島状ベース領域（13）の表面にコンタク
トし点在する第１層目電極層による島状ベース電極、
（16）はメッシュエミッタ電極（14）とコンタクトし層
間絶縁膜上を櫛歯状に延在する第２層目電極層による櫛
歯状エミッタ電極、（17）は島状ベース電極（15）とコ
ンタクトし層間絶縁膜上を櫛歯状に延在する第２層目電
極層による櫛歯状ベース電極、（18）は櫛歯状エミッタ
電極（16）の一部を拡張してベース領域（11）の隔部に
設けたエミッタボンディングパッド、（19）はエミッタ
ボンディングパッド（18）に超音波ボンディング等の手
法よりワイヤボンドされたAl等のワイヤである。In FIG. 1, (11) is a P-type base region, (12)
Is an N + type mesh emitter region formed in a lattice pattern on the surface of the base region (11), and (13) is an island-shaped base region that is exposed in the mesh portion of the Mensch emitter region (12) vertically and horizontally. (14) is a mesh emitter electrode formed by the first electrode layer which extends in a lattice shape according to the lattice shape of the mesh emitter region (12) and is in full contact with the emitter region (12), and (15) is an island base An island-shaped base electrode composed of a first electrode layer which is in contact with the surface of the region (13)
(16) is a comb-teeth-shaped emitter electrode formed by the second electrode layer which is in contact with the mesh emitter electrode (14) and extends in a comb-teeth shape on the interlayer insulating film, (17) is an island-shaped base electrode (15) A comb-teeth-shaped base electrode formed by the second electrode layer that contacts and extends in a comb-teeth shape on the interlayer insulating film, and (18) extends a part of the comb-teeth-shaped emitter electrode (16) to form a base region (11). (19) is a wire such as Al wire-bonded to the emitter bonding pad (18) by a method such as ultrasonic bonding.

第２図、及び第３図は夫々第１図のAA線断面とBB線断
面を示し、（20）は裏面にコンタクト用Ｎ+層（図示せ
ず）が設けられたコレクタとなる半導体基板、（21）は
基板（20）表面を覆う酸化膜、（22）はPSG等から成る
層間絶縁膜である。前記第１層目と第２層目電極層は夫
々アルミニウム等の金属材料をパターニングして得られ
たものである。2 and 3 respectively show the AA line cross section and the BB line cross section of FIG. 1, and (20) shows a semiconductor substrate serving as a collector having a contact N + layer (not shown) provided on the back surface, Reference numeral (21) is an oxide film covering the surface of the substrate (20), and reference numeral (22) is an interlayer insulating film made of PSG or the like. The first and second electrode layers are each obtained by patterning a metal material such as aluminum.

斯る構成において、エミッタボンディングパッド（1
8）下部の島状ベース領域（13a）は表面に島状ベース電
極（15）が設けられず、且つエミッタボンディングパッ
ド（18）の端部まで延長してストライプ状形状に形成す
る。そして、エミッタボンディングパッド（18）から突
出しパッド（18）と重ならない部分に島状ベース電極
（15a）を設け、櫛歯状ベース電極（17）によりベース
バイアスを印加する。ストライプ形状の島状ベース領域
（13a）を形成するエミッタ領域（12）の表面には１層
目電極層によりエミッタ電極（14）が設けられ、層間絶
縁膜（22）のスルーホールを介してエミッタボンディン
グパッド（18）と接続する。In such a configuration, the emitter bonding pad (1
8) The lower island-shaped base region (13a) is not provided with the island-shaped base electrode (15) on its surface, and extends to the end of the emitter bonding pad (18) to form a stripe shape. Then, an island-shaped base electrode (15a) is provided in a portion protruding from the emitter bonding pad (18) and not overlapping the pad (18), and a base bias is applied by the comb-teeth-shaped base electrode (17). The emitter electrode (14) is provided on the surface of the emitter region (12) forming the stripe-shaped island-shaped base region (13a) by the first electrode layer, and the emitter electrode (14) is provided through the through hole of the interlayer insulating film (22). Connect with bonding pad (18).

第４図は第２層目電極層の全体的な形状を示し、４角
形半導体基板（20）の一角にエミッタボンディングパッ
ド（18）が設けられ、対角線上の一角にはベースボンデ
ィングパッド（図示せず）が設けられ、櫛歯状ベース電
極（17）と櫛歯状エミッタ電極（16）とが対接する。FIG. 4 shows the overall shape of the second electrode layer. The emitter bonding pad (18) is provided at one corner of the rectangular semiconductor substrate (20), and the base bonding pad (not shown) is provided at one corner on the diagonal line. The comb-shaped base electrode (17) and the comb-shaped emitter electrode (16) are in contact with each other.

以上に説明した本願構成によれば、エミッタボンディ
ングパッド（18）下部の島状ベース領域（13a）がスト
ライプ状を有し、ストライプの延在方向に対してはエミ
ンタ領域（12）によるピンチ構造を除去できるので、エ
ミッタボンディングパッド（18）下部のベース抵抗ＲB
はピンチ構造を有する第７図のベース抵抗ＲBより値を1
/5程度に減少できる。その為、ベース領域（11）のキャ
リアの蓄積によるスイッチング特性を向上できる。ま
た、エミッタボンディングパッド（18）下部にもストラ
イプ形状を作る為のエミッタ領域（12）を形成するの
で、エミッタ周辺長の低下が少く、従って第７図のもの
と同等の電流容量を得ることができる。さらに、エミッ
タボンディングパッド（18）下部には島状ベース電極
（15）が存在しないので、ワイヤボンドによる短絡事故
は無い。According to the above-described configuration of the present application, the island-shaped base region (13a) below the emitter bonding pad (18) has a stripe shape, and the pinch structure is formed by the emitter region (12) in the extending direction of the stripe. Since it can be removed, the base resistance R B below the emitter bonding pad (18)
Is 1 from the base resistance R B of FIG. 7 having a pinch structure.
/ 5 can be reduced. Therefore, the switching characteristics due to the accumulation of carriers in the base region (11) can be improved. In addition, since the emitter region (12) for forming the stripe shape is formed under the emitter bonding pad (18), the peripheral length of the emitter is less reduced, and therefore the current capacity equivalent to that in FIG. 7 can be obtained. it can. Furthermore, since the island-shaped base electrode (15) does not exist below the emitter bonding pad (18), there is no short-circuit accident due to wire bonding.

（ト） 考案の効果 以上に説明した通り、本考案によればエミッタボンデ
ィングパッド（18）下部の島ベース領域（13a）をスト
ライプ状としたので、ベース抵抗ＲBの増大を防ぎスイ
ッチング特性の劣化を防止できる。(G) Effect of the Invention As described above, according to the present invention, the island base region (13a) below the emitter bonding pad (18) has a stripe shape, which prevents the increase of the base resistance R B and deteriorates the switching characteristics. Can be prevented.

また、エミッタ周辺長はそれ程短くならずに済むの
で、電流容量の低下は極く僅かである。Further, since the peripheral length of the emitter does not have to be so short, the decrease in current capacity is extremely small.

さらに、エミッタボンディングパッド（18）部の短絡
事故を防止できるので、アルミワイヤの超音波ボンディ
ングを適用できる。Furthermore, since it is possible to prevent a short circuit accident in the emitter bonding pad (18), ultrasonic bonding of aluminum wire can be applied.

【図面の簡単な説明】[Brief description of drawings]

第１図，第２図および第３図は夫々本考案を説明する為
の平面図、第１図のAA線断面図、および第１図のBB線断
面図、第４図は本考案を説明する為の平面図、第５図と
第６図は従来例を説明する為の平面図と断面図、第７図
と第８図は提案された構造を説明する為の平面図と断面
図である。1, 2 and 3 are plan views for explaining the present invention respectively, a sectional view taken along the line AA of FIG. 1, a sectional view taken along the line BB of FIG. 1, and FIG. 4 are for explaining the present invention. FIGS. 5 and 6 are plan views and cross-sectional views for explaining a conventional example, and FIGS. 7 and 8 are plan views and cross-sectional views for explaining the proposed structure. is there.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項１】コレクタとなる一導電型の半導体領域の表
面に形成した逆導電型のベース領域と、 前記ベース領域の表面に、格子状に形成した一導電型の
エミッタ領域と、 前記格子状エミッタ領域の格子の目の部分に露出する前
記ベース領域の表面にコンタクトする島状ベース電極
と、 前記格子状エミッタ領域の表面にコンタクトする、格子
状のエミッタ電極と、 前記島状ベース電極と前記格子状エミッタ電極を被覆す
る層間絶縁膜と、 前記層間絶縁膜の上を延在し、前記島状ベース電極と層
間接続する櫛歯状ベース電極と、 前記櫛歯状ベース電極の櫛と対向するように層間絶縁膜
上を延在し、前記格子状エミッタ電極と層間接続する櫛
歯状エミッタ電極と、 前記櫛歯状エミッタ電極の櫛歯の根本部分に形成したエ
ミッタボンディングパッドとを具備し、 前記エミッタボンディングパッドの下部においては、前
記ベース領域の露出表面がストライプ状に形成されるよ
うに前記エミッタ領域を形成し、 前記ストライプ状ベース領域の端部に前記櫛歯状ベース
電極の櫛の先端部分が前記島状ベース電極を介してコン
タクトし、 前記ストライプ状ベース領域は前記エミッタボンィング
パッドの端付近まで直線状に延在し、 前記エミッタボンディングパッドの下部には前記島状ベ
ース電極が存在しないことを特徴とするトランジスタ。1. A base region of opposite conductivity type formed on the surface of a semiconductor region of one conductivity type serving as a collector, one emitter region of one conductivity type formed in a grid pattern on the surface of the base region, and the grid pattern. An island-shaped base electrode that contacts the surface of the base region exposed at the grid portion of the emitter region; a lattice-shaped emitter electrode that contacts the surface of the lattice-shaped emitter region; An inter-layer insulation film covering the lattice-shaped emitter electrode, a comb-teeth-shaped base electrode extending over the inter-layer insulation film and inter-layer connected to the island-shaped base electrode, and facing a comb of the comb-teeth-shaped base electrode. The comb-teeth-shaped emitter electrode that extends over the interlayer insulating film and is interlayer-connected to the lattice-shaped emitter electrode, and the emitter-bonding pad formed at the root of the comb-teeth of the comb-teeth-shaped emitter electrode. The emitter region is formed below the emitter bonding pad so that the exposed surface of the base region is formed in a stripe shape, and the comb-teeth shape is formed at an end of the stripe-shaped base region. The tip portion of the comb of the base electrode contacts through the island-shaped base electrode, the stripe-shaped base region extends linearly to the vicinity of the end of the emitter bonding pad, and the lower portion of the emitter bonding pad has the A transistor characterized by the absence of an island-shaped base electrode.
JP1989067483U 1989-06-09 1989-06-09 Transistor Expired - Lifetime JPH08756Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989067483U JPH08756Y2 (en) 1989-06-09 1989-06-09 Transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989067483U JPH08756Y2 (en) 1989-06-09 1989-06-09 Transistor

Publications (2)

Publication Number Publication Date
JPH038435U JPH038435U (en) 1991-01-28
JPH08756Y2 true JPH08756Y2 (en) 1996-01-10

Family

ID=31601096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989067483U Expired - Lifetime JPH08756Y2 (en) 1989-06-09 1989-06-09 Transistor

Country Status (1)

Country Link
JP (1) JPH08756Y2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6422062A (en) * 1987-07-17 1989-01-25 Sanyo Electric Co Transistor

Also Published As

Publication number Publication date
JPH038435U (en) 1991-01-28

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