JPS61177019A - Pulse stretch circuit - Google Patents

Abstract

PURPOSE:To shorten the delay time of pulse rise with simple constitution and to obtain a pulse stretch circuit CONSTITUTION:When a waveform A of an input terminal is turned to the high level in the pulse stretch circuit constituted of.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse stretching circuit suitable for use in a control signal circuit for compensating for missing video signals in, for example, a video disc player.

In a conventional video disk player, when a modulated signal reproduced from a recording medium is demodulated into an original video signal, image quality may deteriorate due to scratches on the recording medium. In that case, a correction control signal is required to detect deterioration in image quality and correct the image quality.

In order to perform sufficient correction on the screen, this correction control signal is used by widening the time width of the signal that detects deterioration in image quality. This operation is performed by a pulse stretch circuit.

FIG. 4 is a circuit diagram showing an example of a conventional pulse stretching circuit. In Figure 4, 1 is an input terminal, 2 and 6 are transistors, 3 and 6 are constant current sources, 4 is a capacitor, 8 is a comparator, 9 is a reference potential, 10 is an output terminal, and 11 is a power supply. .

Now, when the input terminal waveform shown in FIG. 5 (-) is input to the input terminal 1 shown in FIG. 4, the capacitor 4 is charged with current,
The potential at the emitter terminal of transistor 6 increases. Next, when the potential applied to the input terminal changes to Low level,
Transistor 2 is turned off, and the potential at the emitter terminal of transistor 5 decreases at a slope determined by capacitor 4 and constant current source 3. The potential change at the emitter terminal of the transistor 5 is shown in FIG. 5(b). The potential of the emitter terminal of the transistor 5 and the reference potential 9 were compared by a comparator 8, and a signal pulse-stretched by t2 was obtained at the output terminal 1o.

Problems to be Solved by the Invention In such a conventional circuit, it takes time to charge the capacitor 4 in FIG. 4, as in the section t3 in FIG. 5(C). Therefore, it is necessary to shorten the charging time by increasing the current value flowing through the constant current source 3. At this time, since the stretching time is determined by the current value of the capacitor 4 and the constant current source 3, it was necessary to increase the capacitance value of the capacitor 4. Since the capacitance value of the capacitor 4 becomes large in this way, it is not suitable for IC implementation, and there is a problem that the delay time of the rise of the pulse is large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and aims to provide a pulse stretch circuit that has a simple configuration, can minimize the delay time of pulse rise, and is suitable for IC implementation.

Means for Solving the Problems In order to solve the above problems, the present invention adds a signal obtained by stretching the pulse width of an input pulse to an input pulse to obtain a signal obtained by stretching the input pulse.

Effect: With the above configuration, the present invention adds the input pulse and the pulse signal obtained by pulse stretching the input pulse to obtain the pulse stretched pulse. For signals that are not generated and are stretched, a pulse-stretched signal is used, and since they each act independently, the configuration becomes easy.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the pulse stretching circuit of the present invention. In Figure 1, 1 is an input terminal, 2 and 5 are transistors, 3 and 6 are constant current sources, 4 is a capacitor, and 7 is the sum of the input pulse and the stretched pulse output from the emitter terminal of transistor 5. 8 is a comparator, 9 is a reference potential, and 10 is an output terminal.

The operation will be explained below using FIG. 2.

The input terminal waveform shown in Figure 2A is the input terminal 1 shown in Figure 1.
, the signal is applied to the adder 7 and the pace terminal of the transistor 2. In the pulse stretch circuit composed of transistors 2 and 6, constant current sources 3 and 6, and capacitor 4, when input terminal waveform A changes to high level as shown in FIG. 2B, current is charged to capacitor 4, The potential at the emitter terminal of transistor 5 rises. Conversely, when input terminal waveform A changes to Low level, transistor 2
becomes an OFF state, and the potential at the emitter terminal of the transistor 6 decreases with a slope determined by the current value of the capacitor 4 and the constant current source 3. The output of the adder 7 in FIG. 1 is a pulse obtained by adding the pulse applied to the input terminal 1 and the output pulse of the emitter terminal of the transistor 5. The addition in this case is digital addition, that is, an OR circuit. The waveform is shown in FIG. 2C. This is the sum of the input terminal waveform A in FIG. 2 and the emitter terminal output waveform B of the transistor 6.

The output of the adder 7 is compared with a reference potential 9 by a comparator 8, and a signal pulse-stretched by t2 is obtained at the output terminal 1o. This signal is shown in the second diagram.

Note that the same result is obtained when the adder shown in FIG. 1 performs analog addition. FIG. 3 shows the operation in this case. Figures 3A and B are Figure 2A.

Similarly to B, the input terminal waveform and the emitter terminal output waveform of the transistor 6 are shown, respectively. These two signals are processed by an analog adder circuit to obtain an adder output C as shown in FIG. 3C. The output of the adder 7 is compared with a reference potential 9 by a comparator 8, and a signal pulse-stretched by t2 is obtained at the output terminal 1o. This signal is shown in the third diagram.

As described above, since the pulse input to the input terminal 1 and the output pulse of the emitter terminal of the transistor 5 are added, the rise of the output of the emitter terminal of the transistor 6 at the time of the rise of the input pulse can be calculated using an extremely simple circuit configuration. The delay time can be reduced and the configuration is suitable for IC implementation.

Effects of the Invention As described above, the present invention adds a signal obtained by stretching the pulse width of an input pulse to an input signal to obtain a signal obtained by stretching the input signal. With a simple configuration of the pulse stretch circuit, the delay time of the rise of the output pulse can be reduced, and a circuit suitable for integration into an IC can be obtained, which has great effects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a pulse stretching circuit according to an embodiment of the present invention, FIGS. 2 and 3 are operation explanatory diagrams for explaining the present invention in detail, and FIG. 4 is a circuit diagram showing a conventional pulse stretching circuit. The circuit diagram shown in FIG. 6 is an operation explanatory diagram for explaining the same operation. 1... Input terminal, 3, 6... Constant current source, 7... Adder, 1o... Output terminal,
11...Power supply. Name of agent: Patent attorney Toshio Nakao and one other person (see Figure 3, Figure 5)

Claims (3)

[Claims] (1) The device is configured to obtain a pulse-stretched signal of the input pulse using means for stretching the pulse width of the input pulse and means for adding the input pulse and the stretched pulse. Pulse stretch circuit. (2) The pulse stretching circuit according to claim 1, wherein the means for adding the input pulse and the stretched pulse is constituted by an OR circuit. (3) The pulse stretching circuit according to claim 1, wherein the means for adding the input pulse and the stretched pulse is constituted by an analog adding circuit.