JPH04336767A - Automatic video level control circuit - Google Patents

Abstract

PURPOSE:To uniform irregularity in level between video signals and to improve reliability by adjusting the level of each input video signal to a reference level. CONSTITUTION:After a prescribed processing such as amplification, the input video signal is converted from an analog signal into a digital signal. The level of a frame pulse included in the digital signal is detected, and the level is compared with the reference level by a reference level generation part as the level of the input video signal. As a result of comparison, when the level of the input video signal is smaller than the reference level, a control signal increasing the amplification degree of an amplification circuit 2 is supplied to the amplification circuit 2, and when the level of the input video signal is larger than the reference level, the control signal reducing the amplification degree to the amplification circuit 2. Accordingly, the irregularity in level between the input video signals can be uniformed in output by means of the control 1 of amplification degree. Thus, the ratio of the circuit to an analog circuit can be increased, the reliability can be improved and the number of parts can be reduced.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to high-definition display monitors that use not only broadcast signals but also MUSE signals from high-definition VTRs, high-definition DISKs, etc. as input video signals, by adjusting the level of each input video signal to a reference level. The present invention relates to an automatic video level control circuit that equalizes level irregularities between video signals.

0002

2. Description of the Related Art Conventional automatic level control circuits have been composed of digital circuits that perform calculations and analog circuits that include transistors and the like.

0003

[Problems to be Solved by the Invention] Conventional automatic level control circuits, both digital circuits and analog circuits, are large in circuit scale and have a large number of components. SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic level control circuit in which reliability is improved by increasing the ratio of digital circuits to analog circuits in the circuit configuration, and the number of components is reduced as much as possible.

0004

[Means for Solving the Problems] The present invention provides an operational amplifier in which the video signal is input to the positive input terminal, a first resistor is provided between the output terminal and the negative input terminal, and the drain is connected to the operational amplifier. Connect to the negative input end of the
8. A FET with a control voltage applied to its gate, an input end connected to the output end of the operational amplifier, and a low-pass filter.
A video signal processing unit that removes unnecessary components of 15 MHz or higher and performs video signal processing such as DC reproduction, and an A/V converter that converts analog signals from the video signal processing unit into digital signals.
a D conversion unit, detecting frame pulses multiplexed on the first and second horizontal lines in the video signal, generating a first detection pulse signal synchronized with the frame pulses on the first line; A level detection pulse generator generates a second detection pulse signal synchronized with the frame pulse of the second line, and a frame pulse included in the first horizontal line of the digital signal from the A/D converter. a first parallel/serial conversion circuit that detects the level of the first detection pulse signal at the input timing of the first detection pulse signal, converts the data from a parallel signal to serial signal data, and outputs the data;
The level of the frame pulse included in the second horizontal line of the digital signal from the A/D converter is detected at the input timing of the second detection pulse signal, and the data is converted from a parallel signal to serial signal data. A second parallel/serial conversion circuit converts and outputs the signal, and the signal from the first parallel/serial conversion circuit and the signal from the second parallel/serial conversion circuit obtained by taking the two's complement are added together. a first adder, a reference level generation unit that generates a reference level, a second adder that adds the signal from the first adder and the reference level obtained by taking a two's complement; a first integrating circuit that integrates the signal from the second adder; a serial/parallel converter that converts the serial signal from the first integrating circuit into the original parallel signal;
An automatic level control circuit consisting of a pulse width modulator that performs pulse width modulation using a signal from a parallel conversion circuit, and a second integration circuit that integrates the signal from the pulse width modulator and outputs the control voltage. This is what we provide.

[0005]

[Operation] After the input video signal is subjected to predetermined processing such as amplification, it is converted from an analog signal to a digital signal. The level of the frame pulse included in the digital signal is detected, and this level is compared with a reference level as the level of the input video signal. As a result of the comparison, if the signal is smaller than the reference level, a control signal is sent to increase the amplification degree of the amplifier circuit, and if it is larger than the reference level, a control signal is sent to the amplifier circuit to decrease the amplification degree. supply to. With this effect, level variations between input video signals can be suppressed to make the output uniform by controlling the amplification degree.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An automatic video level control circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of an automatic video level control circuit according to the present invention. In the figure, 1 is a high-definition VT in addition to broadcast signals.
2 is an operational amplifier 21 and an FET (field effect transistor) 22;
a first amplification circuit for amplifying the video signal;
is LPF (low pass filter) 23 and second amplifier circuit 2
4, a DC regeneration circuit 25, etc., and the operational amplifier 2
A video signal processing section 4 performs signal processing such as removing unnecessary components of 8.15 MHz or more from the video signal from the video signal processing section 1, amplification, and DC reproduction, and a video signal processing section 4 converts the analog video signal from the video signal processing section 3 into an 8-bit digital signal. An A/D converter that converts into a video signal (hereinafter referred to as a digital output signal), 5 is the digital signal output line, and 6 is a frame pulse multiplexed on the first and second horizontal lines of the video signal. generation of level detection pulses, which generates a first detection pulse signal synchronized with the frame pulse of the first line and a second detection pulse signal synchronized with the frame pulse of the second line. 7 is a first parallel/serial conversion circuit 26 (hereinafter referred to as a first P/S conversion circuit) and a second parallel/serial conversion circuit 27 (hereinafter referred to as a second P/S conversion circuit).
(referred to as a P/S conversion circuit) and a first adder 28, an output level detection section detecting the digital signal output level from the A/D conversion section 4; is a second circuit for detecting the level difference between the reference level from the reference level generating section 8 and the signal from the output level detecting section 7;
The adder 10 includes a first integration circuit 29, a serial/parallel conversion circuit 30 (hereinafter referred to as an S/P conversion circuit), a pulse width modulator 31 (hereinafter referred to as PWM), and a second
This is a control signal generating section that controls the amplification degree of the first amplifier circuit 2 according to the signal from the second adder 9.

Next, the operation of each block and the entire operation will be explained. The present invention compares the output level with a reference level, feeds back a control signal according to the state to the first stage amplifier circuit, and uses this control signal to control the degree of amplification, thereby converting each input video signal with level variations into a reference level. This is to keep the output level constant according to the level. The explanation will be given below in order starting from the output stage. The digital output signal is input to the first P/S conversion circuit 26 and the second P/S conversion circuit 27. Note that a diagonal line and a circled number on each inter-block transmission line represent the number of bits. The first P/S
The conversion circuit 26 detects the level of the frame pulse (representing the video white peak level) included in the first horizontal line of the digital signal at the input timing of the first detection pulse signal, and transfers the data to a shift register. converts the parallel signal into serial signal (1 bit) data and outputs it. The second P/S conversion circuit 27 detects the level of the frame pulse (representing the video black level) included in the second horizontal line from the same signal at the input timing of the second detection pulse signal. , and converts it into 1-bit data and outputs it in the same manner as above. The reason for converting to 1-bit data is that digital circuit operations are performed in series (
This is because the circuit size can be reduced by doing so (serial calculation).

Data (image white peak level) from the first P/S conversion circuit 26 and the second P/S conversion circuit 27
The difference from the data (video black level) represents the level (magnitude) of the frame pulse of the input signal. The level of the frame pulse is constant regardless of the video content. In other words, the level of the frame pulse is determined to be the output level of the digital output signal relative to the input signal. The first adder 28 detects the level of the frame pulse. Specifically, the data from the first P/S conversion circuit 26 and the two's complement data from the second P/S conversion circuit 27 are added. The second adder 9 detects the difference between the frame pulse level obtained by the first adder 28 and the reference level, specifically, the difference between the frame pulse level and the reference level obtained by taking the two's complement. Add the level. The data obtained here is either the same as, larger than, or smaller than the reference level. The signal from the second adder 9 is integrated in the first integration circuit 29 to adjust the response speed, and then converted into the original 8-bit signal in the S/P conversion circuit 30. The PWM 31 performs pulse width modulation with the signal from the S/P conversion circuit 30. The output waveform of the PWM 31 is a rectangular wave as shown in FIG. The period T1 is constant, and the pulse width changes as shown (T2, T3, T4) according to the signal from the S/P conversion circuit 30. The PWM31
The output signal from the second integrating circuit 32 is integrated and converted into a DC voltage. This part becomes an analog circuit. The second
The integrating circuit 32 may be simply composed of a resistor and a capacitor. The DC voltage corresponds to the level of the digital output signal and is a control signal.

On the other hand, as shown in the figure, an FET 22 is provided between the negative input terminal of the operational amplifier 21 constituting the first amplifier circuit 21 and the ground. Therefore, the equivalent resistance between the drain (D) and source (S) of the FET 22 is the operational amplifier 21
form a feedback resistance. Since the equivalent resistance value changes depending on the gate (G) voltage, the amplification degree of the operational amplifier 21 changes due to this resistance change. In other words, the amplification degree of the operational amplifier 21 can be controlled by changing the gate voltage. The above control signal is used as the gate voltage. The reason why FETs are used here is that the voltage-current characteristics of FETs are different from those of transistors, and have linear characteristics close to those of pure resistance. As described above, in the case of the input signal where the level of the digital output signal is higher than the reference level, the operational amplifier 2
As a result of lowering the amplification factor of 1 and increasing the amplification factor when it is small, the digital output signal is brought to the same level as the reference level.

0010

As explained above, according to the present invention, the configuration of the automatic level control circuit provided to obtain a constant output when various video signals with varying video levels are used as an input source is weighted to the digital circuit portion. As a result, the use of serial operations has the effect of reducing the circuit scale and the number of analog components, and these effects greatly contribute to improving reliability and making this circuit an LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of an automatic video level control circuit according to the present invention.

FIG. 2 is an output waveform diagram of a pulse width modulator (PWM).

[Explanation of symbols]

1 Analog video signal input line 2 First amplifier circuit 3 Video signal processing section 4 A/D conversion section 5 Digital signal output line 6 Level detection pulse generation section 7 Output level detection section 8 Reference level generation section 9 Second Adder 10 Control signal generator 21 Operational amplifier 22 FET 23 Low pass filter (LPF) 24 Second amplifier circuit 25 DC regeneration circuit 26 First parallel/serial conversion circuit 27 Second parallel/serial conversion circuit 28 1 adder 29, first integration circuit 30, serial/parallel conversion circuit 31, pulse width modulator 32, second integration circuit

Claims (1)

[Claims] 1. A high-definition display monitor that receives a MUSE signal as an input video signal, comprising: an operational amplifier inputting the video signal to a positive input terminal and having a first resistor provided between the output terminal and the negative input terminal; Connect the drain to the negative input terminal of the operational amplifier, ground the source,
8. A FET with a control voltage applied to its gate, an input end connected to the output end of the operational amplifier, and a low-pass filter.
A video signal processing unit that removes unnecessary components of 15 MHz or higher and performs video signal processing such as DC reproduction, and an A/V converter that converts analog signals from the video signal processing unit into digital signals.
a D conversion unit, detecting frame pulses multiplexed on the first and second horizontal lines in the video signal, generating a first detection pulse signal synchronized with the frame pulses on the first line; A level detection pulse generator generates a second detection pulse signal synchronized with the frame pulse of the second line, and a frame pulse included in the first horizontal line of the digital signal from the A/D converter. a first parallel/serial conversion circuit that detects the level of the first detection pulse signal at the input timing of the first detection pulse signal, converts the data from a parallel signal to serial signal data, and outputs the data;
The level of the frame pulse included in the second horizontal line of the digital signal from the A/D converter is detected at the input timing of the second detection pulse signal, and the data is converted from a parallel signal to serial signal data. A second parallel/serial conversion circuit converts and outputs the signal, and the signal from the first parallel/serial conversion circuit and the signal from the second parallel/serial conversion circuit obtained by taking the two's complement are added together. a first adder, a reference level generation unit that generates a reference level, a second adder that adds the signal from the first adder and the reference level obtained by taking a two's complement; a first integrating circuit that integrates the signal from the second adder; a serial/parallel converter that converts the serial signal from the first integrating circuit into the original parallel signal;
A pulse width modulator that performs pulse width modulation with a signal from a parallel conversion circuit, and a second integration circuit that integrates the signal from the pulse width modulator and outputs the control voltage. Automatic video level control circuit.