JPS61187468A - Clamp circuit - Google Patents

Abstract

PURPOSE:To obtain a stable video image by designing the circuit that a synchronizing tip level of a video signal is clamped in response to the squelch input to apply synchronization even when no horizontal synchronizing pulse is applied at the special reproduction such as fine slow. CONSTITUTION:A video signal is amplified by a PB amplifier 1 and a prescribed DC voltage of a voltage source 31 is amplified by a DC amplifier 26 and fed to a level shift circuit 22. An output of the level shift circuit 22 is amplified by a video line-up 23 and fed to an output terminal 29. The output of the amplifier 23 is compared woth the prescribed DC voltage from a voltage source 30 by a comparator 24. When a squelch signal is fed via a terminal 34 and a squelch circuit 32, the DC amplifier 26 is actuated and when the said signal does not exist, the PB amplifier 21 is actuated. A switch circuit 27 activates the comparator 24 when one of the output of the squelch circuit 32 and the horizontal synchronizing pulse from the terminal 33 is applied and when the squelch signal is fed, the DC level of the amplifier 23 is controlled in the same way as that of the voltage source 30.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing circuit constituted by a transistor circuit, and particularly to a magnetic video recording and reproducing device (hereinafter referred to as a VTR).
This relates to clamp circuits such as (abbreviated as ).

[Conventional technology]

Conventionally, in the video signal sink and clamp circuit in the video signal processing circuit of a VTR+, as shown in FIG. The DC level of the signal is set by a level shift circuit 2.

The output of the level shift circuit 2 is amplified by a video line amplifier 3, and a squelch signal 6 for squelching the output of the video line amplifier 3 is connected.

Furthermore, the output of the video line amplifier 3 is connected to the comparator 4.
is input. The comparator 4 operates when a horizontal synchronizing pulse is input to the control terminal 11, and the line amplifier 3
The output sync tip level is compared with the potential of the DC reference potential source 7, which is set to a predetermined potential in advance, and a voltage proportional to the difference voltage between the DC reference potential and the sync tip level is output. The output voltage of the comparator 4 is smoothed by a smoothing circuit 5, and the output voltage of this smoothing circuit 5 is input to the level shift circuit 2. As a result, when the sink level is higher than the potential of the DCfj quasi-source 7, the DC level of the output of the level shift circuit 2 is lowered, and the sink level is lowered.
When the prelevel is lower than the DC reference level, feedback is applied to increase the output DC level of the level shift circuit 2. In the squelch circuit 6, a squelch drive signal for squelching is inputted to a control terminal 12, and at the time of squelch, the output of the squelch circuit is DC.
level, and when no squelch is applied, the output of the video line amplifier 3 appears at the output of the squelch circuit.

[Problem that the invention seeks to solve]

In the conventional clamp circuit, the operation of the comparator 4 is limited only to the period when the horizontal synchronization pulse is input to the control terminal 11, so the comparator 4 does not operate during squelch, and the sync tip level clamp is not applied. Therefore, a DCC offset occurs in the output DC level of the squelch circuit 6.

During special playback such as fine slow playback, a pseudo vertical synchronization signal is supplied from the servo system to the control terminal 12 of the squelch circuit 6, and the squelch circuit 6 is turned on only for a specific period determined by the pseudo vertical synchronization signal. Therefore, during the period when the squelch circuit 6 is off, the video line amplifier 3
appears at the output of the squelch circuit 6. At this time, since the horizontal synchronizing pulse is not input to the control terminal 11, the comparator 4 does not operate, and the video signal is not clamped at the sync tip level. Therefore, during the period when the squelch circuit is off, an offset occurs in the DC level of the output of the squelch circuit, and level fluctuations tend to occur in the sync tip level. As a result, vertical synchronization is no longer applied, so the image on the screen becomes distorted and noise appears on the screen.

[Means for solving problems]

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that clamps synchronization and prelevels to predetermined DC levels even during special playback such as fine slow playback.
Its feature is that in response to a squelch input such as a pseudo vertical synchronization signal, a predetermined DC potential is supplied to the video line amplifier via a level shift circuit instead of the output of the playback amplifier, and it also operates a comparator. At least the output of the video line amplifier is compared with the DC level and this output is fed back to the level shift circuit.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, the reproduced video signal is supplied to the terminal 28 and amplified by the reproduction (PB) amplifier 1.

Voltage source 31 generates a predetermined DC voltage, which is amplified by DC amplifier 26. The outputs of the amplifiers 21 and 26 are commonly connected and supplied to a level shift circuit 22. The output of the level shift circuit 22 is amplified by a video line-up 23 and supplied to an output terminal 29. The output of amplifier 23 is compared with a predetermined DC voltage from voltage source 30 by comparator 24 . The output of the comparator 24 is smoothed by a smoothing circuit 25, and the smoothed output is fed back to the level shift circuit 22 and becomes a control signal for changing the level shift scene. The squelch signal is supplied to the squelch circuit 32 via the terminal 34, and its output is transmitted to the PB amplifier 21 and the DC amplifier 2.
This is a control signal that turns on and off these operations for each of 6. In particular, when a squelch signal is supplied, the DC
When the amplifier 26 operates and there is no same signal, P B 7.
yp21 operates. A horizontal synchronization pulse is provided to terminal 33. The switch circuit 27 responds to the output of the squelch circuit 32 and the horizontal synchronizing pulse to generate a control signal for activating the comparator 24 during the period when one of the signals is supplied.

Therefore, in this circuit, the DC level of the amplifier 23 is controlled in the same manner as that of the voltage source 30 not only when the horizontal periodic pulse is supplied but also when the squelch circuit is supplied.

FIG. 2 specifically shows the block configuration shown in FIG. 1, and parts corresponding to those in FIG. 1 are designated by the same numbers. The differential amplifier 21 as a regenerative (PB) amplifier includes transistors 110, 111, 113, 114, 11.
6,120,122,123. Resistance 115°310.2
23. A bias voltage 117 is supplied to the transistor 1100 through a resistor 115, and a video signal is input through a terminal 28.

The video signal input to the terminal 28 is amplified by the differential amplifier 21, and its amplified output is taken out from the emitter of the transistor 114 and input to the base of the transistor 1730 at the input section of the level shift circuit 220. The transistor 173 in the level shift circuit 22 is also supplied with the output of the differential amplifier circuit 26 as a DC amplifier. D.C.
The amplifier 26 includes transistors 126, 127, 129,
130, 133, 134, 135, 137° resistance 131
, 224, and generates the voltage of the DC power supply 31 as a voltage follower at its output.

Level shift circuit 22! d,) transistor 173°17
6, resistors 175 and 177.

A signal input to the transistor 1730 (this is a video signal or a DC voltage, hereinafter referred to as signal 1) is taken out from the collector of the transistor 176. Therefore, the output signal of this circuit 22 (hereinafter, signal 2
The DC level of (referred to as ) is changed by changing the pace potential of transistor 176.

The active amplifier 23 as a video line amplifier includes transistors 178, 179, 180, 181, 182, 183.
゜185.186,188,192,194,195.
It is composed of resistors 189° and 190, and bias voltages 191 and 198. The signal 2 input to the pace of the transistor 179 is amplified with a gain determined by the ratio of the resistors 189 and 190, and its output is taken out from the emitter of the transistor 188 and sent to the emitter follower transistor 19.
The output signal of the transistor 188 (hereinafter referred to as signal 3) is input to the base of the transistor 2140 of the comparator 24 via the resistor 213.

The comparator 24 includes transistors 208 and 209
.

210.214,215,216,217,218,2
20, 221° resistance 211, 212, 213. It is configured by a bias voltage 22. The comparator 24 is
When squelch is not applied, it operates only while the horizontal synchronization pulse is input. In other words, switch circuit 2
At 7, a horizontal synchronization pulse is input to terminal 33 -
Then, the transistor 171 becomes conductive and current flows through the resistor 170. As a result, the collector voltage of the transistor 171 increases and the base potential of the transistor 209 becomes higher than the base potential of the transistor 210, so the transistor 209 becomes conductive and the current source transistor 218 becomes conductive, and as a result, the comparator 24 operates. . On the other hand, during the period when the horizontal synchronizing pulse is not input to the terminal 33, the transistor 171 is turned off and no current flows through the resistor 170, so that the transistor 209 is cut off. Also, except during squelch, the transistor 210 is also turned off, so the comparator 105 does not operate.

During squelch, a voltage higher than the bias voltage 163 is supplied to the terminal 34 of the squelch circuit 32, so the transistor 144 becomes conductive and raises the potential of the transistor 2100. Therefore, transistor 210 becomes conductive and current flows to the collectors of transistors 208 and 218, causing comparator 105 to operate.

During the period when the horizontal synchronization pulse is input, comparator 1
05 compares the signal 3 input to the base of the transistor 214 with the bias voltage 30 input to the base of the sink tip level transistor 2170. When the sink level is higher than the bias voltage 30, the transistor 216 becomes conductive and the collector current of the transistor 216 flows, charging the capacitor 225. Therefore, the base potential of transistor 205 rises, and current flows to the collectors of transistors 200, 203, and 205. As a result, the collector potential of the transistor 200 increases,
The base potential of transistor 176 of level shift circuit 22 rises. Therefore, the collector current of transistor 176 increases and the collector potential of transistor 176 decreases. As a result, the DC level of signal 2 decreases.

Conversely, the sync tip level of signal 3 is bias voltage 30
When it is lower, current flows through the collectors of transistors 215 and 220, and the charge stored in capacitor 225 is discharged through the collector of transistor 221.

The base potential of transistor 2050 falls, no current flows through the collector of transistor 205, and the base potential of transistor 176 falls. As a result, D of signal 2
C level goes down. In this way, the signal 3 is clamped so that the signal 3's current value /l/ is equal to the pathless voltage 30, and a clamped output signal is obtained from the terminal 29.

During squelch, the squelch signal is supplied to the force meter 34 and the comparator 102 operates. Further, the transistor 144 becomes conductive, and the transistor 143 is turned off. Therefore, the transistor 1200 pace voltage increases and transistor 120 conducts, while the transistor 1340 pace voltage decreases, causing it to turn off.

As a result, transistors 116 and 123 are turned off, and differential amplifier 21 does not operate, while transistor 130
, 137 are conductive, so the differential amplifier 26 operates.

Since the input signal of the differential amplifier 21 is a DC voltage, the DC voltage is input to the level shift circuit 230 input.

The output of the level shift circuit 23 is input to the differential amplifier 23 and amplified, and then input to the comparator 24.
As previously discussed, the signal extracted from the emitter of transistor 188 is clamped to be equal to bias voltage 222.

〔Effect of the invention〕

As explained above, in the present invention, at the time of squelch,
Since video signal sync and pre-level clamping can be applied, during special playback such as fine slow playback,
If a pseudo vertical sync signal is applied to the squelch input, even if a horizontal sync pulse is not supplied, the clamp will be applied and the sync chip level will be at the specified DC level, so synchronization will be applied and the screen will not be distorted or noise will appear on the screen. A stable image can be obtained without any interference. Further, the present invention is a circuit most suitable for IC implementation, and the circuit shown in FIG. 2 is implemented as an IC except for the capacitor 225.

[Brief explanation of drawings]

FIG. 1 is a professional diagram of one embodiment of the present invention, and the second
This figure is a specific circuit diagram of the configuration shown in FIG. 1, and FIG. 3 is a professional diagram showing a conventional example. 28...Playback video signal input terminal, 29...
−Output terminal

Claims (1)

[Claims] A first amplifier that amplifies the video signal, a second amplifier that amplifies the DC voltage, a level shift circuit that receives the outputs of these first and second amplifiers, and a third amplifier that amplifies the output of this level shift circuit. a comparator for comparing the output of the third amplifier with a predetermined DC voltage in its operating state; and means for changing the amount of level shift in the level shift circuit in response to the output of the comparator. , means for inactivating the first amplifier and activating the second amplifier in response to a squelch signal; means for receiving a horizontal synchronization signal; A clamp circuit comprising: means for activating the comparator.