JP2901371B2 - Noise reduction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reduction circuit installed in a recording / reproducing system such as a video tape recorder and used for reducing noise of an audio signal.

[0002]

2. Description of the Related Art The audio system of a video tape recorder (VTR) for reproducing and recording with high fidelity (Hi-Fi) includes:
As shown in FIG. 7A, a recording system circuit 4 for recording an audio signal on a magnetic tape 2 as a recording medium is installed, and as shown in FIG.
And a reproduction system circuit 6 for reproducing an audio signal from the device. These recording system circuit 4 and reproduction system circuit 6 include:
A noise reduction circuit (NR) 8 is commonly installed to suppress noise generated by the recording medium, secure a dynamic range of a required signal, and prevent deterioration in sound quality. This NR8 is a logarithmic compression / expansion type noise reduction circuit that functions as an inverse circuit between the recording system circuit 4 and the reproduction system circuit 6, and performs logarithmic compression of the audio signal during recording and reproduces during reproduction. Undesired signal components in the audio signal are suppressed by expanding the audio signal in a reverse relationship to that at the time of recording. And
The recording system circuit 4 converts the audio signal VR to NR during recording.
8 and then pass through the FM emphasis circuit (EMPH)
The high frequency band is emphasized by 10 and added to the FM modulator 12, and the carrier signal is frequency-modulated by the audio signal VR. The FM signal obtained by the FM modulator 12 is amplified by a recording amplifier 14 and then recorded on a magnetic tape 2 via a magnetic head 16. In the reproduction system circuit 6, at the time of reproduction, the FM signal detected from the magnetic tape 2 through the magnetic head 16 is amplified by the preamplifier 18 and then added to the FM demodulator 20 to perform FM demodulation. .
The demodulated output of the FM demodulator 20 is supplied to a de-emphasis circuit (D
After the high-frequency reduction by the EEMPH) 22 is performed, the NR
8 and output as a reproduced audio signal VPO.

FIG. 8 shows a specific circuit configuration of NR8. In this NR8, through a switch 24, a compression input signal during recording (REC) and an expansion input during reproduction (PB) are applied to a low-pass filter (LPF) 26 set in a main signal path 25, The LPF 26 applies the amplified signal to the first amplifier 28 for amplification. The amplifier 28 is provided with a first feedback path 30 to be operated at the time of recording and a second feedback path 32 to be operated at the time of reproduction. These feedback paths 30 and 32 are selected by a switch 34. At the time of recording, the feedback path 30 constitutes a decompression circuit for negatively feeding back the output of the amplifier 28 to the negative phase input side and adding a square decompression characteristic to the output, thereby realizing the compression characteristic by the CMP output. At the time of reproduction, the output of the amplifier 28 is fully fed back from the feedback path 32 to its negative-phase input side to configure the amplifier 28 as a full feedback amplifier, that is, a buffer circuit, and the square expansion characteristic is obtained from the EXP output by the circuit.

[0004] The feedback path 30 forms a decompression circuit. A variable gain amplifier (CCA) 36 is provided as a second amplifier for amplifying the output of the amplifier 28, and the output of the CCA 36 is used as a noise reduction emphasis circuit (NRE) 38.
The signal is fed back to the negative-phase input side of the amplifier 28 through the input terminal. The CCA 36 has a CCA corresponding to the input level.
A control circuit 40 for controlling the amplification gain of 36 is added. The control circuit 40 is provided with an LPF 42, a weighting circuit (WTNG) 44, a detection circuit 46 as a signal level detecting means, and a voltage / current conversion circuit 48. The LPF 42 removes unnecessary signal components such as noise,
The TNG 44 frequency-weights the high-frequency component of the output signal of the LPF 42. For example, as shown in FIG. 9, the detection circuit 46 rectifies the output of the WTNG 44 and receives the rectified voltage at the base of the transistor 461, thereby receiving the rectified voltage generated at the emitter of the transistor 461 as the attack time setting resistor 463 and the recovery time setting resistor 46.
2 and a capacitor 465 to provide a specified time constant for smoothing and converting to a DC voltage corresponding to the signal level. Since the detection output of the detection circuit 46 is given as a voltage level, the voltage / current conversion circuit 48 constitutes a control current generation means for converting the voltage output from the detection circuit 46 into a control current for the CCA 36 to be controlled. ing. Therefore, N
In R8, at the time of recording, such an expansion circuit performs logarithmic compression on the audio signal to enter the feedback path of the amplifier 28,
At the time of reproduction, an audio signal having a low noise level can be recorded and reproduced by adding a decompression characteristic to the reproduced audio signal by passing through a decompression circuit from the buffer output of the amplifier 28 through.

[0005]

In an ideal state, such a logarithmic compression type noise reduction circuit has a high precision from a small level to a large level by compression processing during recording and decompression processing during reproduction. Although the original signal can be restored with a high degree of linearity (linear reproducibility), in reality, the linearity is impaired. FIG.
Indicates the operating characteristics of this noise reduction circuit,
Is the compression characteristic during recording (CMP), and B is during reproduction (EXP).
However, it was confirmed that the linearity deteriorated in a minute level region indicated by a hatched portion. That is, problems of the noise reduction circuit are listed as follows. a. Due to the C / N of the recording medium, high-frequency noise increases at the time of reproduction, whereby the linearity of the minute area changes with respect to the single characteristic of the noise reduction circuit. b. Due to compatibility problems with other devices, for example, when a commercially available soft tape or a recording tape of a camcorder is reproduced, the characteristics do not match, and a sense of noise or a sense of discomfort may be felt. c. When high precision is required, such as equipment for professionals, there is a risk that the high precision may be limited.

[0008] Therefore, the expansion operation at the time of reproduction in the noise reduction circuit shown in FIG. 8 will be examined. For simplicity of description, as shown in FIG. 11, a CCA 36, a detection circuit 46 as a signal level detecting means, and a voltage / current converting circuit 4 as a control current generating means for the CCA 36.
It is assumed that a feedback amplifier circuit is configured in FIG. here,
The current (voltage) control sensitivity of the CCA 36 is α, and the control current is i
Assuming that d, the amplification factor Av is as follows: Av = α · id (1) Also,

[Outside 1] Let D be the ideal average value of the input signal V ₁ and D be the detection sensitivity of the detection circuit 46 as signal level detection means.

[0007]

(Equation 1)

[0008] Voltage as control current generating means
The V / I conversion sensitivity T of the current conversion circuit 48 is

[0009]

(Equation 2)

Then, the output signal Vo becomes

[0011]

(Equation 3)

## EQU1 ## Vo is proportional to the square of the input signal V ₁ , whereby a square expansion characteristic is obtained. Here, there is an error in the detection circuit 46 or the voltage-current converting circuit 48, converted to substantially the input signal V _1, when the Ver and the error amount, Vo = α · D · T (V 2 -Ver ) · V ₁ (5) This implies that the error is substantially negligible when V ₁ ≫Ver, but non-linearity occurs in a minute level region where Ver approaches the level of the input signal V ₁ , which causes loss of linearity. Note that even when the CCA 36 has a non-linearity error, it can be approximated by Expression (5).

For this reason, in the conventional noise reduction circuit, the deterioration of the linearity at a low level is not satisfied by the I
It was determined by initial setting by adjusting internal constants such as C, and could not be arbitrarily adjusted.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a noise reduction circuit which realizes high fidelity by arbitrarily adjusting a compression characteristic or an expansion characteristic in such a minute level region.

[0015]

[0016]

A noise reduction circuit according to the present invention includes a first amplifier (28) provided in a main signal path (25), and a signal level detection circuit for detecting a level of a signal in the main signal path. Means (detection circuit 46);
A voltage / current conversion means (voltage / current conversion circuit 48) for converting the level detected by the signal level detection means into a control current; and an output or feedback path (3) of the first amplifier.
0), a second amplifier (variable gain amplifier 36) whose gain is controlled according to the control current obtained by the voltage / current conversion means, and the signal level detection means or the voltage / current conversion and a continuously or intermittently controlled to characteristic control means compression characteristics or elongation properties at the low level area (characteristic control circuit 50) to the second amplifier are added to the means, the characteristic control means , The level detection
Adding a voltage offset or current offset to the output means,
To control these voltage offsets or current offsets
And it said that there was Unishi.

In the noise reduction circuit according to the present invention , the characteristic control means includes a characteristic control input terminal.
The external control input applied to the characteristic control input terminal of
Arbitrary compression or expansion characteristics in the micro level area
It is characterized by being adjustable .

[0018]

The first amplifier provided in the main signal path amplifies an audio signal passing through the main signal path during recording or reproduction. The output signal of this amplifier is applied to a filter, and the pass band and frequency characteristics of the output signal are adjusted. The level of the audio signal that has passed through this filter is detected by level detecting means, and the gain of the second amplifier (CCA 36) is controlled by the level.
Then, the characteristic control means arbitrarily controls the compression characteristic or the expansion characteristic of the low-level region for the second amplifier continuously or intermittently by an external control input. Therefore, in this noise reduction circuit, ideal compression characteristics or expansion characteristics are set by external adjustment.

Further , when the second amplifier is constituted by a variable gain amplifier whose gain can be controlled by a control current,
A voltage / current converting means is provided as the control current generating means. Therefore, a characteristic control means is added to the voltage / current conversion means and the signal level detection means, and the compression characteristic or the expansion characteristic in the low level region is continuously or intermittently applied to the second amplifier by the characteristic control means. Can be controlled.

The characteristic control means includes a characteristic control input terminal.
Is added to this characteristic control input terminal.
Compression characteristics in the minute level region by external control input
Alternatively, the elongation characteristics can be arbitrarily adjusted.

[0021]

FIG. 1 shows an embodiment of a noise reduction circuit according to the present invention. The noise reduction circuit of this embodiment relates to an improvement of the decompression circuit in the noise reduction circuits shown in FIGS. 7 and 10, and the same parts are denoted by the same reference numerals. That is, the variable gain amplifier (CCA) 36 installed in this expansion circuit is installed in the first feedback circuit 30 in the first amplifier 28 of the main signal path 25 in the noise reduction circuit of FIG. Constitute a second amplifier.

[0022] This is the CCA36 are added control circuit 40, the detection circuit 46 as a signal level detecting means for detecting the signal level of the input signal V ₁ of the CCA36 This control circuit 40 is installed, the detection circuit 46 , Ie, a voltage / current conversion circuit 48 as a control current generating means for generating a control current of the CCA 36 by converting a voltage signal into a current. A characteristic control circuit 50 is added to the detection circuit 46 and the voltage / current conversion circuit 48 as a means for controlling the characteristics added to the CCA 36, that is, the linearity of the compression characteristics or the expansion characteristics based on an external control input. .

The characteristic control circuit 50 is provided with two adjustment input terminals 52 and 54.
A switching signal Vs indicating whether or not to perform the linearity adjustment is added to the adjustment input terminal 54. A linearity adjustment voltage Vc for setting the adjustment amount of the linearity is applied to the adjustment input terminal 54.
Has been added. The switching signal Vs is a high / low (H / L) switching voltage indicating whether or not to perform linearity adjustment, and the linearity adjustment voltage Vc is
For example, it is provided by a variable voltage continuously adjusted by a variable resistor 56. The linearity adjustment voltage Vc is
The reference voltage Vcc may be divided into a plurality of stages and set as a step value.

According to such a configuration, the input / output characteristics of the noise reduction circuit, that is, the expansion circuit, in an ideal state in a steady state are as shown in equation (4).
In an actual circuit, the detection circuit 46, the voltage / current conversion circuit 4
8 or CCA 36 has an error, so that equation (5) is obtained. As described above, this causes the linearity to deteriorate, but Vo ≒ α · D · T (V ₁ −Ver)
In V ₁ , α · D · T is a circuit constant, and V ₁ ≫V
er becomes the equation (4), and becomes non-linear when V ₁ → Ver. However, the equation (5) can be approximated to the equation (4), and the error voltage Ver substantially exists for the input signal V ₁ .

Therefore, in this noise reduction circuit, the characteristic control circuit 50 intentionally provides an offset ΔV to the fixed value D · T. As a result, equation (5) becomes Vo と α · D · T (V ₂ −Ver + ΔV) V ₁ (6). That is, the characteristics can be freely set by appropriately setting the offset voltage ΔV in the positive and negative directions, and the error voltage Ver and the offset voltage ΔV are adjusted to Ver = ΔV (7) Then, the error voltage can be canceled. As a result, the linearity is forcibly changed by the offset ΔV, and a desired linearity is obtained. The adjustment of the linearity can be performed by adjusting the arbitrary linearity adjustment voltage Vc by the variable resistor 56.

Next, FIG. 2 shows a specific example of a circuit configuration of the noise reduction circuit of the present invention, and the same reference numerals are given to the same parts as those of the noise reduction circuit shown in FIG. The input signal V ₁ is applied to the input terminal 58, the input signal V ₁ was, added to the rectifier circuit 62 of the detection circuit 46 is rectified. As the rectifier circuit 62, a dual-wave rectifier circuit is used, and the rectified output current i is taken out.

On the output side of the rectifier circuit 62, a buffer circuit 64 for receiving a rectified output current i is provided. That is, a transistor 66 having a common base and collector is provided at the output of the rectifier circuit 62.
6, a transistor 68 having a common base and collector is provided. A resistor 70 and a variable voltage source 72 are connected in series between the emitter of the transistor 66 and the reference potential point, that is, the ground point, and between the emitter of the transistor 68 and the reference potential point, that is, the ground point. , A resistor 74 and a variable voltage source 76 are connected in series. The variable voltage source 72 constitutes a control voltage source whose voltage is controlled by the control output of the characteristic control circuit 50.

The collector of the transistor 68 is connected to the positive power supply line, and the voltage generated by the resistor 70 of the rectified output current i is output to the emitter of the transistor 68. DC voltage representing the signal level of the input signal V ₁ by smoothing time constant the output voltage is defined by the recovery time setting resistor 74 and the attack time setting resistor 78 and a capacitor 82 connected to the external connection terminals 80, That is, a level detection voltage is obtained.

On the output side of the detection circuit 46 provided as the signal level detection means, a voltage / current conversion circuit 48 is provided as control current generation means for generating a control current id for the CCA 36. An amplifier 84 is provided in the voltage / current conversion circuit 48, and the level detection voltage obtained by the detection circuit 46 is applied to the positive phase input side.
On the output side of the amplifier 84, the control current id is supplied to the CCA 36.
A transistor 86 for flowing current is provided. The output of the amplifier 84 is applied to the base of the transistor 86, and a series circuit of a voltage / current conversion resistor 88 and a voltage source 90 is provided between the emitter and the ground. Then, the voltage generated at the resistor 88 in response to the output of the amplifier 84 and the added voltage value of the voltage source 90 are fed back to the negative-phase input side of the amplifier 84 to constitute an all feedback amplifier. The voltage source 90 constitutes a control voltage source whose voltage is controlled by the control output of the characteristic control circuit 50.

According to such a configuration, the characteristic control circuit 5
If 0 is not added, the control voltage sources 72, 76, 9
0 indicates that no voltage is applied and can be omitted.
2 is applied to a capacitor 82 via a current mirror circuit 64 and smoothed.
The level detection voltage representing the level of the input signal V ₁ is obtained. This level detection voltage is a voltage / current conversion resistor 8
8 to a control current id.
Flows to the CCA 36, the required gain is set in the CCA 36, and the elongation characteristic is obtained.

However, when the characteristic control circuit 50 is added, the voltage of the voltage source 72 or the voltage sources 76 and 90 is varied by the output according to the linearity adjustment voltage Vc applied to the adjustment input terminal 54, An offset corresponding to the voltage is set. That is, the positive offset voltage Vof (+) is applied to the voltage source 72 or 76 side and the voltage source 76
Assuming that a positive offset voltage Vof (−) is added to the side, when Vof (+)> Vof (−), the control current id is set to a very small level and a positive offset is set.
The gain Av of A36 increases, and Vof (+) <Vo
At the time of f (-), the control current id is set to a minute level, a negative offset is set, the control current stops flowing at the minute level, and the gain Av of the CCA 36 decreases. FIG. 3 shows this control state.

Although the offset is set by adjusting the voltage of the voltage source 72 in this embodiment, the same operation can be obtained by setting the offset voltage Vof 'using the voltage source 76 as a variable voltage source. Can be

Next, FIG. 4 shows a specific circuit configuration example of the noise reduction circuit of the present invention. This example is
FIG. 4 mainly shows a specific circuit of the characteristic control circuit 50 in the noise reduction circuit shown in FIG.
In this noise reduction circuit, a resistor 75 and a voltage source 90 are formed by a resistor 91 instead of the voltage source 76 of the above embodiment.

A current mirror circuit 92 is provided between the transistor 86 and the CCA 36, and the transistor 8
The control current id obtained in No. 6 is caused to flow to the CCA 36 through the current mirror circuit 92. That is, a transistor 100 having a common base and collector and a resistor 1 are connected between the collector of the transistor 86 and the positive power supply line.
02 and a transistor 104 and a resistor 106 between the positive power supply line and the CCA 36.
Are connected, and the base of the transistor 104 and the base and collector of the transistor 100 are commonly connected.

The voltage / current conversion circuit 48 is provided with a differential circuit 116 in which the emitters of the pair of transistors 108 and 110 are shared. Transistor 10
The linearity adjustment voltage Vc is applied to the base of the transistor 8 through the adjustment input terminal 54, and the reference voltage Vm is applied to the base of the transistor 110 from the voltage source 118. A constant current source 120 for supplying an operation current to the differential circuit 116 is connected via a switch 122 between the connection point between the transistors 108 and 110 and the power supply line. The switch 122 receives the switching output from the comparison circuit 124.
A linearity adjustment voltage Vc applied to the positive phase input side;
The reference voltage Vn applied from the voltage source 126 to the negative phase input side
(<Vm), and when the level of the linearity adjustment voltage Vc exceeds the reference voltage Vn, the comparison circuit 124
Is generated, the switch 122 is closed, and the differential circuit 116 enters an operating state.

A resistor 128 and a transistor 1 are connected between the collector of the transistor 108 of the differential circuit 116 and the ground.
A resistor 130 is connected between the collector of the transistor 10 and the ground point. When the transistor 108 is turned on, the resistor 128 is turned on by the current flowing through the transistor 108. When the transistor 110 is turned on, the resistor 130 is turned on by the current flowing through the transistor 110. Voltage is generated.

The operation of the noise reduction circuit will be described. The magnitude relationship between the power supply voltage Vcc and the reference voltages Vm and Vn is set to 0 <Vn <Vm <Vcc. Here, when the linearity adjustment voltage Vc is 0 <Vc <Vn, the output of the comparison circuit 124 is at a low level, and the switch 124 is turned off. In this case, the linearity is not adjusted. That is, as indicated by the broken line in FIG. 5, there is no adjustment of the linearity, and the device is turned off.

When Vn <Vc <Vm, the comparison circuit 124 generates a high-level output, closes the switch 122, and switches the transistor 108 of the differential circuit 116.
Are conducted, and the level (LEV) rises (up) as shown in FIG.

When Vm <Vc <Vcc, the comparison circuit 124 generates a high-level output and the switch 122
Is closed, and the transistor 11 of the differential circuit 116 is closed.
0 conducts and the level (LEV) falls (down) as shown in FIG.

As described above, three-stage control of no adjustment (L), low-level amplification (M), and low-level attenuation (H) can be performed according to the level of the linearity adjustment voltage Vc. Then, the offset voltages Vof (+), Vof
Since (−) is set to several m to several tens mV, the resistance 75
The resistance value of the resistor 91 is R ₁ , the resistance value of the resistor 91 is R ₂ ,
The resistance value R ₁ of _1, R _{1 2} the resistance value of the resistor 130, the resistance value R _{2 1} resistor 134, the resistance value of the resistor 128 R _{2 2}
If, and _{R 2 1 »R 2, R 1} 1 »R 1, resistor 74
It is possible to change the characteristics by the resistance 75 of the connection point voltages Va, low-level region of the connection point voltage Vb of the resistor 88 and the resistor 91 in R _{1 1,} R ₁ or R _{2 1,} R ₂ divides elongation properties .

FIG. 6 shows a modification of the characteristic control circuit 50 in the noise reduction circuit shown in FIG.
In the above embodiment, the three-stage linearity adjustment voltage Vc is used. However, by appropriately setting the shunt resistors 112 and 114, the linearity adjustment voltage Vc is continuously changed by the variable resistor 136 to operate the constant current source 120. May be switched by the switching signal SW.

[0042]

As described above, according to the present invention, the following effects can be obtained. a. By appropriately adjusting and setting the offset voltage with respect to the error voltage generated in the circuit system, it is possible to realize linearity with much higher accuracy than the conventional companding characteristics. b. For linearity error due to tape C / N and noise, and compatibility with other equipment, for example, by selecting offset voltage stepwise and switching or adjusting by external control signal, the linearity of compression or expansion characteristics can be easily adjusted. Can be improved or intentionally changed. c. Moreover, the adjustment of the linearity can be realized by a simple configuration without using a complicated circuit, and the operation is easy. d. By incorporating the characteristic control means together with the companding circuit in the IC, it is possible to provide a highly accurate noise reduction circuit that can be easily controlled by an external control input.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a noise reduction circuit of the present invention.

FIG. 2 is a circuit diagram illustrating a specific circuit configuration example of a noise reduction circuit according to the present invention.

FIG. 3 is a diagram showing operation characteristics of the noise reduction circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing another specific circuit configuration example of the noise reduction circuit of the present invention.

FIG. 5 is a diagram showing operation characteristics of the noise reduction circuit shown in FIG.

FIG. 6 is a circuit diagram showing a modification of the characteristic control circuit in the noise reduction circuit shown in FIG.

FIG. 7 is a block diagram showing a recording system circuit and a reproduction system circuit in the VTR.

FIG. 8 is a block diagram showing a conventional noise reduction circuit.

9 is a circuit diagram showing a detection circuit of the noise reduction circuit shown in FIG.

FIG. 10 is a diagram showing operating characteristics in a conventional noise reduction circuit.

11 is a block diagram showing a decompression circuit of the noise reduction circuit shown in FIG.

[Explanation of symbols]

 28 first amplifier 36 variable gain amplifier (second amplifier) 42 low-pass filter 46 detection circuit (level detection means) 48 voltage / current conversion circuit (voltage / current conversion means) 50 characteristic control circuit

Claims (2)

(57) [Claims] 1. A first amplifier installed in a main signal path, signal level detecting means for detecting a signal level, and a voltage / current for converting the level detected by the signal level detecting means into a control current. Conversion means; a second amplifier installed in the output or feedback path of the first amplifier, the gain of which is controlled according to the control current obtained by the voltage / current conversion means; and the signal level detection means or provided with a continuous or intermittent control characteristic control means compression characteristics or elongation properties at low level regions with respect to the added said second amplifier to the voltage-current converting means, said characteristic control means Is the signal level detecting means.
Add a voltage or current offset to the stage,
Control the voltage or current offset from
Noise reduction circuit, characterized in that the. 2. The characteristic control means has a characteristic control input terminal.
The external control input that is applied to this characteristic control input terminal
Depending on the force, the compression characteristics or the expansion characteristics
2. The method according to claim 1, wherein the characteristics can be arbitrarily adjusted.
On-board noise reduction circuit.