JPS631501Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a mute circuit for video signal reproduction signals.

FIG. 1 is a circuit diagram showing a conventional example of such a mute circuit, and FIG. 2 is a waveform diagram of signals at various parts in the circuit of FIG.

In these figures, 1 is the video output transistor, 2 is the load resistance of transistor 1, 3 is the coupling capacitor, 4 is the load impedance, 5 is the switch, 6 is the RF modulator, and 7 is the output impedance of the input signal source. Yes, the input signal Vi is a video signal. Please refer to FIGS. 1 and 2. In this circuit, the input Vi is normally transmitted to the output V ₀ through the output transistor 1 and the coupling capacitor 3. In this state, the coupling capacitor 3 is charged to the average value of the output signal of the output transistor 1. In this state, as shown in Figure 2C, T ₁
When the mute signal Vc is input at the time , the switching circuit 5 is closed, the input of the output transistor 1 is fixed at +B, the output _V0 becomes 0V as shown in FIG. 2B, and is muted. However, immediately after time T ₁ when the mute signal Vc is input, the output V ₀
suddenly increases, the negative modulation type RF modulator 6 enters an overmodulated state, and a carrier is lost, causing white noise and audio buzz.

An object of the present invention is to provide a mute circuit that does not generate the above-mentioned unnatural audio buzz or white noise immediately after mute.

In order to achieve the above object, the present invention fixes the output in the mute circuit as it approaches the average value of the signal so that the video output does not change suddenly during mute. Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a waveform diagram of various signals in the circuit of FIG.

In these figures, 8 is a switching transistor for miute, 9 is a charging resistor, and 10 is a charging capacitor. Note that the miute switching transistor 8 is turned off when the miute signal Vc is at a high level, and turned on when the miute signal Vc is at a low level.

In Figure 3, resistor 9 is connected to output impedance 7.
If the input signal Vi is made sufficiently large, since the transistor 8 is OFF in the normal state, the input signal Vi
is transmitted as is to the output V ₀ . In this state, the capacitor 10 is connected to (+B
−V _B ). Note that V _B is an input signal of the output transistor 1. Next, at time _T1 , as shown in FIG. 4D, when the mute signal Vc becomes low level, the switching transistor 8
is turned ON, and if the capacitor 10 is made sufficiently large, the magnitude of the V _B signal will be the magnitude divided by the output impedance 7 and the ON resistance of the transistor 8. Normally, 7 is sufficiently larger than the ON resistance of transistor 8, so the signal component of the divided voltage _VB becomes very small, and the signal component is not transmitted to the output _V0 , resulting in a mute state. At this time capacitor 1
0 is charged by the transistor 8 by (+B-V _B ). i.e. Miyuto timing
Before and after T ₁ , the potential difference across charging capacitor 10 does not change, and the average voltage of V _B does not change.
However, when the mute signal Vc turns ON and OFF, the signal component is bypassed to the power supply line +B by the capacitor 10 and the transistor 8 or not.

Therefore, as shown in Figure 4 B and C, the output
Since V ₀ converges toward its average value during muting, the RF modulator 6 will not be overmodulated.
Therefore, according to this embodiment, the unnatural buzz sound immediately after the mute can be muted without generating white noise.

As described above, according to the present invention, it is possible to provide a mute circuit that does not generate unnatural buzz or white noise immediately after mute.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional mute circuit, Figure 2 is a waveform diagram of various signals in the circuit of Figure 1,
FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a waveform diagram of various signals in the circuit of FIG. 3. Description of symbols, 1...Video output transistor, 2...
...Load resistance of video output transistor, 3...Coupling capacitor, 4...Load impedance, 5...
...Switch, 6... RF modulator, 7... Output impedance of input signal source, 8... Switching transistor for mute, 9... Resistor for charging the capacitor 10, 10... Capacitor for charging.

Claims (1)

[Scope of utility model registration request] In a video signal reproducing device configured to take a reproduced video signal as an input signal and guide the input signal to an output transistor via an output impedance, a connection point between the output impedance and the output transistor is connected to a capacitor and a charging resistor to the capacitor. A switching element is connected in parallel to the charging resistor to a constant potential source, and is controlled to be turned on and off by a mute signal. The input signal of the video signal, which is the input signal, is charged through a charging resistor to approximately the average value, and when the switching element is turned on by application of the mute signal, the input signal of the output transistor is set to the average value. A video signal mute circuit characterized in that it is fixed.