JPS61171327U

JPS61171327U -

Info

Publication number: JPS61171327U
Application number: JP1985053092U
Authority: JP
Priority date: 1985-04-10
Filing date: 1985-04-10
Publication date: 1986-10-24

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は第１図の動作を説明するタイムチヤート
、第３図は第１図の回路を用いた装置の具体例を
示すブロツク図、第４図は従来のプログラムカウ
ンタの一例を示すブロツク図、第５図は従来の動
作を説明するタイムチヤートである。ＦＦ１〜ＦＦ３……フリツプフロツプ、ＣＴＲ
１〜ＣＴＲ４……カウンタ、ＤＬ……遅延回路、
ＡＧ……ゲート。 FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is a time chart explaining the operation of Fig. 1, Fig. 3 is a block diagram showing a specific example of a device using the circuit shown in Fig. 1, and Fig. 4 is a block diagram showing an example of a conventional program counter. , FIG. 5 is a time chart explaining the conventional operation. FF1~FF3...Flip-flop, CTR
1 to CTR4...Counter, DL...Delay circuit,
AG...Gate.

Claims

[Scope of utility model registration request]

In a programmable counter in which a plurality of synchronous counters to which a load signal and a clock are commonly applied are connected in cascade, a delay circuit which branches the load signal applied to the synchronous counters and gives a fixed delay time to the branched load signal; 1. A programmable counter comprising a gate that inhibits the supply of a clock to a synchronous counter for a certain period of time in accordance with a load signal output from a delay circuit.