JPS61171156A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61171156A JPS61171156A JP60011001A JP1100185A JPS61171156A JP S61171156 A JPS61171156 A JP S61171156A JP 60011001 A JP60011001 A JP 60011001A JP 1100185 A JP1100185 A JP 1100185A JP S61171156 A JPS61171156 A JP S61171156A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- guide ring
- semiconductor device
- main surface
- stress load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置Ｋかかるものであり、特にモールド
成形によって半導体素子に加えられる応力負荷に対する
改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly relates to improvements in stress loads applied to semiconductor elements by molding.
半導体素子がモールド成形される半導体装置としては、
例えば第３図に示すものがある。この図において、半導
体素子（１）は、まずフレーム（２）に固着され、次に
、ワイヤ（３）によって各々対応するリード部−に布線
゛されて組立てられる。そして、その後トランス７アモ
ールド法等により、エポキシ樹脂（４）等で成形封止さ
れる。As a semiconductor device in which a semiconductor element is molded,
For example, there is one shown in FIG. In this figure, a semiconductor element (1) is first fixed to a frame (2), and then wired (3) to each corresponding lead part to be assembled. Thereafter, it is molded and sealed with an epoxy resin (4) or the like by a transformer 7 amolding method or the like.
ところで、かかる成形封止において、成形後の樹脂は、
硬化後の冷却とともに通常収縮が生じ、半導体素子（１
）に対して大きな圧力を及ぼす。このため、半導体素子
（１）の周縁部に欠陥が発生し、半導体装置としての機
能に支障が生ずるおそれがある。By the way, in such molding and sealing, the resin after molding is
Shrinkage usually occurs with cooling after curing, and the semiconductor element (1
). Therefore, defects may occur in the peripheral portion of the semiconductor element (1), which may impede the function of the semiconductor device.
また、モールド用の樹脂（４）と半導体素子（すは通常
熱膨張係数が一桁以上異なるため、半導体装置の使用中
すなわち動作中の温度変化により、いわゆる熱応力が生
ずることとなる。これらの応力は、半導体素子（１）の
周縁部が大きく、また、半導体素子（１）の主表面に生
ずる応力は大きくなる。Furthermore, since the thermal expansion coefficients of the molding resin (4) and the semiconductor element (usually differ by more than an order of magnitude), so-called thermal stress occurs due to temperature changes during use of the semiconductor device, that is, during operation. The stress is greater at the peripheral edge of the semiconductor element (1), and the stress generated at the main surface of the semiconductor element (1) is greater.
本発明線、かかる従来技術の欠点に鑑みてなされたもの
でオシ、成形樹脂による半導体素子への応力負荷を低減
することができる半導体装ｔを提供することをその目的
とする。The present invention has been made in view of the drawbacks of the prior art, and an object of the present invention is to provide a semiconductor device t that can reduce stress loads on semiconductor elements due to molded resin.
本発明は、樹脂材によってモールド成形される半導体素
子の主表面の周縁部に軟質材を設けることを特徴とする
ものである。The present invention is characterized in that a soft material is provided at the periphery of the main surface of a semiconductor element molded with a resin material.
本２発明によれば、半導体素子の周縁部に設けられた軟
質材により樹脂材による応力負荷が吸収され、半導体素
子に対する応力負荷が低減される。According to the second aspect of the invention, the stress load caused by the resin material is absorbed by the soft material provided at the peripheral edge of the semiconductor element, and the stress load on the semiconductor element is reduced.
以下、本発明にかかる半導体装置を添付図面に示す実施
例に基づいて詳細に説明する。Hereinafter, a semiconductor device according to the present invention will be described in detail based on embodiments shown in the accompanying drawings.
第１図には本発明にかかる半導体装置の一実施例が示さ
れている。また、第１図の破線部分が拡大して第２図に
示されている。なお、前述した従来技術と同様の構成部
分については同一の符号を用いることとする。FIG. 1 shows an embodiment of a semiconductor device according to the present invention. Further, the broken line portion in FIG. 1 is enlarged and shown in FIG. 2. Note that the same reference numerals are used for the same components as in the prior art described above.
第１図及び第２図において半導体素子（１）には、その
主表面にコート層（５）が形成されている。このコート
層（５）は基本的には半導体素子（１）の主表面の周縁
部のみに形成すればよいが、製造上の容烏さからすれば
主表面の全体に形成してよく、これによって半導体素子
（１）の機能に格別の障害が生ずることはない。In FIGS. 1 and 2, a coating layer (5) is formed on the main surface of a semiconductor element (1). Basically, this coating layer (5) may be formed only on the peripheral edge of the main surface of the semiconductor element (1), but from the viewpoint of manufacturing efficiency, it may be formed on the entire main surface. This does not cause any particular trouble in the function of the semiconductor element (1).
次に半導体素子（１）の主表面の周縁部には、ガイドリ
ング６υが形成されている。このガイドリング６υは、
例えばシリコン樹脂等の軟質材が使用される。Next, a guide ring 6υ is formed at the periphery of the main surface of the semiconductor element (1). This guide ring 6υ is
For example, a soft material such as silicone resin is used.
このガイドリング（５１）は、スピンコート法あるいは
スクリーン印刷法等を用いてコート層と同時に形成され
る。形成後、ウェハ上の多数の半導体素子を分割するダ
イシング工程により切断されて、各半導体素子（１）毎
にガイドリング５１）が形成されることと表る。５３は
ダイシング時に形成されたダイシング面である。This guide ring (51) is formed simultaneously with the coating layer using a spin coating method, a screen printing method, or the like. After formation, a large number of semiconductor elements on the wafer are cut by a dicing process to divide them, and a guide ring 51) is formed for each semiconductor element (1). 53 is a dicing surface formed during dicing.
次に上記実施例の作用について説明すると、ガイドリン
グ６１）は、軟質材によって形成されているため、モー
ルド用の樹脂（４）による応力負荷を吸収することがで
きる。従って半導体素子（１）に対する応力負荷が低減
されることとなる。Next, the operation of the above embodiment will be explained. Since the guide ring 61) is made of a soft material, it can absorb the stress load caused by the molding resin (4). Therefore, the stress load on the semiconductor element (1) is reduced.
なお、半導体素子（１）の大きさは、どのようなも
Ｊのであってもよいが、特ＫＬＳＩなどの比較的大聖の
ものく対しては、特に効果が大きい。Note that the size of the semiconductor element (1) may vary depending on the size.
J's may be used, but it is especially effective against relatively high-class ones such as KLSI.
以上説明したように、本発明による半導体装置によれば
、半導体素子の周縁部に軟質材からなるガイドリング部
を設けることとしたので、モールド材による応力負荷を
低減することかでさ、半導体素子の機能が損なわれるお
それがなく信頼性の向上を図ることができるという効果
がある。As explained above, according to the semiconductor device according to the present invention, since the guide ring portion made of a soft material is provided at the peripheral edge of the semiconductor element, the stress load due to the molding material can be reduced. This has the effect that reliability can be improved without fear of loss of functionality.
第１図は本発明にかかる半導体装置の一実施例を示す断
面図、第２図は第１図の破線部分を拡大して示す拡大図
、第３図は従来の半導体装置の一例を示す断面図である
。
図において、（１）は半導体素子、（２）はフレーム、
（３）はワイヤ、（４）は樹脂、（５）はコート層、（
２）はリード部、６υはガイドリング、６っけダイシン
グ面である。
なお、各図中同一符号は、同−又は相当部分を示すもの
とする。
−代理人 弁理士 木 村 三 朗
“Ｉｔ！Ｉ 、・′４−草４）第３図FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is an enlarged view showing the broken line portion in FIG. 1, and FIG. 3 is a cross-sectional view showing an example of a conventional semiconductor device. It is a diagram. In the figure, (1) is a semiconductor element, (2) is a frame,
(3) is wire, (4) is resin, (5) is coating layer, (
2) is the lead part, 6υ is the guide ring, and 6υ is the dicing surface. Note that the same reference numerals in each figure indicate the same or corresponding parts. -Representative Patent Attorney Sanro Kimura “It!
Claims (1)
る半導体装置において、 前記半導体素子のうち主表面側の周縁部に軟質材を設け
たことを特徴とする半導体装置。[Scope of Claim] A semiconductor device in which a semiconductor element is molded and sealed with a resin material, characterized in that a soft material is provided on a peripheral edge of the semiconductor element on the main surface side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60011001A JPS61171156A (en) | 1985-01-25 | 1985-01-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60011001A JPS61171156A (en) | 1985-01-25 | 1985-01-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61171156A true JPS61171156A (en) | 1986-08-01 |
| JPH0351301B2 JPH0351301B2 (en) | 1991-08-06 |
Family
ID=11765886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60011001A Granted JPS61171156A (en) | 1985-01-25 | 1985-01-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61171156A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006318988A (en) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS413776Y1 (en) * | 1964-03-03 | 1966-02-28 |
-
1985
- 1985-01-25 JP JP60011001A patent/JPS61171156A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS413776Y1 (en) * | 1964-03-03 | 1966-02-28 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006318988A (en) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0351301B2 (en) | 1991-08-06 |
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