KR950010111B1 - Semiconductor package manufacture method - Google Patents
Semiconductor package manufacture method Download PDFInfo
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- KR950010111B1 KR950010111B1 KR1019920014926A KR920014926A KR950010111B1 KR 950010111 B1 KR950010111 B1 KR 950010111B1 KR 1019920014926 A KR1019920014926 A KR 1019920014926A KR 920014926 A KR920014926 A KR 920014926A KR 950010111 B1 KR950010111 B1 KR 950010111B1
- Authority
- KR
- South Korea
- Prior art keywords
- adhesive
- lead frame
- chip
- semiconductor package
- manufacturing
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000853 adhesive Substances 0.000 claims abstract description 34
- 230000001070 adhesive effect Effects 0.000 claims abstract description 32
- 229920001169 thermoplastic Polymers 0.000 claims abstract description 4
- 239000004416 thermosoftening plastic Substances 0.000 claims abstract description 4
- 238000007639 printing Methods 0.000 claims abstract description 3
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000012774 insulation material Substances 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- 239000011148 porous material Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- -1 polysiloxane Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229920001646 UPILEX Polymers 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 239000004634 thermosetting polymer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
제1도는 종래 LOC장치의 부분구조도.1 is a partial structural diagram of a conventional LOC device.
제2도는 LOC장치의 단면도.2 is a cross-sectional view of the LOC device.
제3도는 본 발명 리이드 프레임의 내부리이드 접착면에 스크린 프린팅 또는 디스펜싱 툴을 이용하여 접착제를 도포한 상태를 나타낸 리이드프레임 평면도.3 is a plan view of a lead frame showing a state in which the adhesive is applied to the inner lead adhesive surface of the lead frame of the present invention using a screen printing or dispensing tool.
제4도는 본 발명 내부 리이드와 접착되는 칩 상부면에 접착제를 도포한 상태를 나타낸 다이평면도.Figure 4 is a die plan view showing a state where the adhesive is applied to the upper surface of the chip bonded to the inner lead of the present invention.
제5도는 본 발명에 의한 다이접착 방법을 보여주는 도면이다.5 is a view showing a die bonding method according to the present invention.
본 발명은 반도체 패키지 제조방법에 관한 것으로서 특히, LOC(Lead On Chip) 반도체 패키지 제조공정 단계중의 하나인 다이본딩(다이접착) 작업을 개선하여 패키지의 품질을 향상시킴은 물론, 원가절감에도 기여할 수 있는 반도체 패키지 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, and in particular, to improve die quality (die bonding), which is one of the steps of a manufacturing process of a lead on chip (LOC) semiconductor package, to improve the quality of a package and contribute to cost reduction. It relates to a semiconductor package manufacturing method that can be.
일반적으로 반도체 패키지는 트랜지스터, 다이오드, IC 등의 허어메틱시일용기를 칭하는것으로서, 반도체 제품에서는 반도체 표면에 습기나 먼지 따위의 불순물이 묻어 있으면, 특성이 열화하기 때문에 허어메틱시일 케이스에 넣어서 밀봉하게 되며, 플레이너와 같이 표면안정화가 되어 있는 것에서는 반드시 허어매틱 시일을 하지 않고 에폭시수지 따위로 모울드한 것도 있는데, 이 경우에도 역시 패키지라 칭한다. 패키지는 반도체 표면을 외부의 습기나 불순물로부터 보호할 뿐만 아니라, 내부의 펠렛이나 가느다란 리이드선에 외부로부터 직접 인장력이 가해지는 것을 방지한다. 또한, 파워 트랜지스터 등에 있어서는 접합부에 발생한 열을 효과적으로 발산시킬 수 있도록 패키지를 설계하는 것이 중요하다. 그런데, 메사형이나 플레이너형과 같은 확산형 계통의 트랜지스터에서는 보통 다이 자체가 콜렉터 접속이 된다.In general, a semiconductor package refers to a hermetic seal container such as a transistor, a diode, or an IC. In a semiconductor product, if impurities or impurities such as moisture are on the surface of the semiconductor, the characteristics deteriorate, so that the semiconductor package is sealed in a hermetic seal case. In the case of surface stabilizers such as planar, there is a mold that does not necessarily have a hermetic seal but a mold such as epoxy resin. In this case, it is also called a package. The package not only protects the semiconductor surface from external moisture or impurities, but also prevents tensile forces from being applied directly to the pellets or the thin lead wires from the outside. In power transistors and the like, it is important to design a package so as to effectively dissipate heat generated in the junction portion. However, in a transistor of a diffusion type system such as a mesa type or a planar type, the die itself is usually a collector connection.
이를 다이본딩 즉, 다이 접착이라 한다.This is called die bonding, or die bonding.
그런데, 종래의 LOC구조는 제1도에 도시한 바와같이, 베이스 필름의 양면에 접착제가 도포된 내열성수지인 폴리이미드(Polymide) 테이프(1)를 이용하여 리이드프레임(2)과 칩(3)을 접착하되, 상기 폴리이미드 테이프(1)는 고형상태로 150~400℃의 온도가 가열되면 도포된 접착제가 용해되어 상기 리이드프레임(2)과 칩(3)을 서로 접착시켰다.However, in the conventional LOC structure, as shown in FIG. 1, the lead frame 2 and the chip 3 are made of a polyimide tape 1, which is a heat resistant resin coated with adhesive on both sides of the base film. When the polyimide tape 1 was heated to a temperature of 150 to 400 ° C. in a solid state, the applied adhesive was dissolved to bond the lead frame 2 and the chip 3 to each other.
그러나, 이와같은 종래의 리이드프레임(2)과 칩(3)을 접착하는 방법은 폴리이미드 테이프(1)가 직접 접착되지 않는 부분에는 미소한 공간이 발생되어 기공이 형성되고, 고정밀도의 얼라인먼트를 얻을 수 없다는 문제점이 있었다.However, in the conventional method of bonding the lead frame 2 and the chip 3, a small space is generated in a portion where the polyimide tape 1 is not directly bonded to form pores, thereby providing a highly accurate alignment. There was a problem that could not be obtained.
상기 기공은 수분의 흡수경로로 이용되므로 결국은 제품의 품질을 저하시키는데, 이때 상기 기공을 통해 흡수된 수분을 제거하여 패키지 품질저하를 방지하려면 별도로 수분제거장치인 프리베이크장치(Prebake unit)를 사용해야하므로 오히려 원가절감이라는 측면에서는 역효과를 야기시켰던 것이다.Since the pores are used as an absorption path of water, the quality of the product is eventually reduced. At this time, in order to remove the water absorbed through the pores and prevent the package quality from being degraded, a prebake unit, which is a moisture removal device, must be used separately. Therefore, in terms of cost reduction rather than caused the adverse effect.
따라서, 본 발명은 이와같은 종래의 문제점을 감안하여 이루어진 것으로써, 본 발명의 목적은 리이드프레임과 칩을 접착시키는데 있어서, 폴리이미드 테이프를 사용하지 않고 액상의 접착제를 사용함으로써 패키지 자체의 품질을 향상시키는 것을 물론, 원가를 절감할 수 있는 반도체 패키지 제조방법을 제공하는데 있다.Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to improve the quality of the package itself by using a liquid adhesive without using polyimide tape in bonding the lead frame and the chip. Of course, to provide a method for manufacturing a semiconductor package that can reduce the cost.
상기 목적을 달성하기 위해서 본 발명에 의한 반도체 패키지 제조방법은 반도체 패키지 제조공정 단계중의 하나인 다이접착공정에 있어서, 리이드프레임의 접착면에 마스크를 제작하여 절연물질을 프린팅하는 방법으로 칩을 접착시키는 것을 특징으로 한다.In order to achieve the above object, the semiconductor package manufacturing method according to the present invention is a method of manufacturing a semiconductor package in a die bonding step, wherein a chip is bonded to a method of printing an insulating material by making a mask on an adhesive surface of a lead frame. It is characterized by.
또한, 본 발명에 의한 반도체 패키지 제조방법은 접착제를 돗팅하는 방법으로 상기 리이드프레임의 내부리이드와 다이를 서로 접착시키는 것을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention is characterized in that the inner lead and the die of the lead frame are adhered to each other by the method of dotting the adhesive.
이하, 본 발명의 실시예를 도면을 참조하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
제2도는 LOC장치의 단면도, 제3도는 본 발명 리이드프레임의 내부리이드 접착면에 스크린프린팅 또는 디스펜싱 툴을 이용하여 접착제를 도포한 상태를 나타낸 리이드프레임 평면도, 제4도는 본 발명 내부리이드와 접착되는 칩 상부면에 접착제를 도포한 상태를 나타낸 다이 평면도, 제5도는 본 발명에 의한 다이접착방법을 보여주는 도면이다.2 is a cross-sectional view of the LOC device, and FIG. 3 is a plan view of a lead frame showing a state where an adhesive is applied to the inner lead adhesive surface of the lead frame of the present invention by using a screen printing or dispensing tool, and FIG. 4 is an adhesive of the inner lead of the present invention. Die plan view showing a state where the adhesive is applied to the upper surface of the chip, Figure 5 is a view showing a die bonding method according to the present invention.
제2도 내지 제5도에 있어서 종래와 동일한 구성부분에는 동일부호를 명기하여 그 설명을 생략한다.In FIGS. 2-5, the same code | symbol is attached | subjected to the same component as before, and the description is abbreviate | omitted.
제2도 내지 제5도에 있어서, 접착제(4)로는 폴리이미드실록산(Polyimidesiloxane ; 실록산은 산화규소의 수소화합물)이나 비전도성 에폭시를 사용한다.2 to 5, polyimidesiloxane (polysiloxane is a hydrogen compound of silicon oxide) or a non-conductive epoxy is used as the adhesive agent 4.
LOC 리이드프레임(2)의 접착면에 마스크를 제작하여 절연물질을 프린팅함으로써 칩(3)을 접착시키고, 리이드프레임(2)의 내부리이드상에는 디스펜싱 툴을 상기 내부리이드의 디자인에 일치되도록 제작하여 접착제(4)를 돗팅한다.Bonding the chip 3 by making a mask on the adhesive surface of the LOC lead frame (2) to print an insulating material, and the dispensing tool on the inner lead of the lead frame (2) to match the design of the inner lead Dotting the adhesive (4).
또한, 상기 칩(3)상에는 디스펜싱 툴을 리이드프레임(2)과의 접착면에 일치되도록 제작하여 접착제(4)를 돗팅한다.In addition, the dispensing tool is manufactured on the chip 3 so as to match the adhesive surface with the lead frame 2, and the adhesive 4 is applied.
한편, 상기 절연물질은 열가소성물질인 써모플라스틱(thermo-plastic) 또는 열경화성수지(플라스틱)인 써모셋(thermo-set) 접착제를 사용한다.On the other hand, the insulating material is a thermo-plastic (thermo-plastic) or a thermo-set resin (plastic) thermo-set adhesive (thermo-set) using a thermoplastic material.
이와같이 접착제(4)가 리이드프레임(2)에 도포된 상태를 도시한 것이 제2도, 제3도, 제4도이다.Thus, the state which the adhesive agent 4 was apply | coated to the lead frame 2 is shown in FIG. 2, FIG. 3, and FIG.
상기 제2도 내지 제4도에 도시한 바와같이, 리이드프레임(2)에 도포되어 있는 접착제(4)를 이용하여 제5도에 도시한 바와같이 칩(3)을 접착하면 되는 것이다.As shown in Figs. 2 to 4, the chip 3 may be adhered as shown in Fig. 5 by using the adhesive 4 applied to the lead frame 2. Figs.
이와같이 본 발명 반도체 패키지 제조방법에 의하면, 종래 리이드프레임과 칩을 접착하기 위해 사용하는 폴리이미드 테이프(KAPTON, UPILEX)를 배제하고 폴리이미드 실록산 또는 비전도성 에폭시를 접착제로 사용하므로, LOC 제조공정에서 발생하는 테이프의 수분흡수를 방지하고, 기공발생을 억제하여 수분제거장치가 별도로 필요하지 않도록 함으로써 원가절감측면에서도 상당히 경제적인 발명이다.As described above, according to the method of manufacturing a semiconductor package of the present invention, polyimide tapes (KAPTON, UPILEX), which are conventionally used to bond a lead frame and a chip, are excluded and polyimide siloxane or non-conductive epoxy is used as an adhesive. It is a very economical invention in terms of cost reduction by preventing the water absorption of the tape, and suppressing pore generation so that a water removal device is not required separately.
또한 종래의 LOC 다이접착과는 다르게 폴리이미드 테이프를 사용하지 않고 상술한 바와같은 접착제를 리이드프레임이나 칩에 직접 도포한 상태에서 서로 접착시키므로 패키지의 두께를 더욱 얇게 할 수 있다.In addition, unlike the conventional LOC die-bonding, since the adhesive as described above is directly applied to the lead frame or chip without using a polyimide tape, the thickness of the package can be made thinner.
이와같이 함으로써 패키지 크기를 소형화하는 현재추세에도 부응할 수 있는 것이다.By doing so, it is possible to meet the current trend of miniaturization of package size.
또한, 본 발명에 의하면 칩과 리이드프레임의 접착제 도포 면적을 최소가 되도록 조절할 수 있으므로 종래의 접착물질로 인한 불량발생을 감소시킬 수 있다.In addition, according to the present invention, since the adhesive coating area of the chip and the lead frame can be adjusted to a minimum, defects caused by conventional adhesive materials can be reduced.
Claims (6)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920014926A KR950010111B1 (en) | 1992-08-19 | 1992-08-19 | Semiconductor package manufacture method |
| JP5204883A JPH06188281A (en) | 1992-08-19 | 1993-08-19 | Preparation of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920014926A KR950010111B1 (en) | 1992-08-19 | 1992-08-19 | Semiconductor package manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940004787A KR940004787A (en) | 1994-03-16 |
| KR950010111B1 true KR950010111B1 (en) | 1995-09-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920014926A KR950010111B1 (en) | 1992-08-19 | 1992-08-19 | Semiconductor package manufacture method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH06188281A (en) |
| KR (1) | KR950010111B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100493189B1 (en) * | 1997-12-29 | 2005-09-26 | 삼성테크윈 주식회사 | Method for manufacturing lead frame |
| SG97759A1 (en) * | 1998-02-06 | 2003-08-20 | Texas Instr Singapore Pte Ltd | Mehtod for assembling an integrated circuit package |
-
1992
- 1992-08-19 KR KR1019920014926A patent/KR950010111B1/en not_active IP Right Cessation
-
1993
- 1993-08-19 JP JP5204883A patent/JPH06188281A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06188281A (en) | 1994-07-08 |
| KR940004787A (en) | 1994-03-16 |
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